diff options
| author | David Hendricks <dhendricks@fb.com> | 2018-03-09 14:30:38 -0800 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2018-07-03 15:53:32 +0000 |
| commit | 7d48ac5c7dfb52fc470bbad1013b4d460bc6a1e0 (patch) | |
| tree | 42002ba1e86627339ff4a6cf38efb4b3f00033bb /src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c | |
| parent | d837e660074e0621d63f59515f933c209441b653 (diff) | |
soc/cavium: Integrate BDK files into coreboot
* Make it compile.
* Fix whitespace errors.
* Fix printf formats.
* Add missing headers includes
* Guard headers with ifdefs
Compile DRAM init code in romstage.
Compile QLM, PCIe, RNG, PHY, GPIO, MDIO init code in ramstage.
Change-Id: I0a93219a14bfb6ebe41103a825d5032b11e7f2c6
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25089
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c')
| -rw-r--r-- | src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c b/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c index 981ad231dc..fc9ac35735 100644 --- a/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c +++ b/src/vendorcode/cavium/bdk/libbdk-arch/bdk-csr.c @@ -37,9 +37,10 @@ * ARISING OUT OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU. ***********************license end**************************************/ #include <bdk.h> -#include <stdio.h> #include "libbdk-arch/bdk-csrs-pccpf.h" #include "libbdk-arch/bdk-csrs-pem.h" +#include "libbdk-arch/bdk-csrs-rst.h" +#include "libbdk-hal/bdk-pcie.h" #ifndef BDK_BUILD_HOST @@ -87,9 +88,6 @@ uint64_t __bdk_csr_read_slow(bdk_node_t node, bdk_csr_type_t type, int busnum, i case BDK_CSR_TYPE_PCICONFIGRC: { - /* Don't allow PCIe register access if PCIe wasn't linked in */ - if (!bdk_pcie_config_read32) - bdk_fatal("PCIe CSR access not supported when PCIe not linked in\n"); union bdk_pcc_dev_con_s dev_con; switch (busnum) { @@ -201,9 +199,6 @@ void __bdk_csr_write_slow(bdk_node_t node, bdk_csr_type_t type, int busnum, int case BDK_CSR_TYPE_PCICONFIGRC: { - /* Don't allow PCIe register access if PCIe wasn't linked in */ - if (!bdk_pcie_config_write32) - bdk_fatal("PCIe CSR access not supported when PCIe not linked in\n"); union bdk_pcc_dev_con_s dev_con; switch (busnum) { |