diff options
author | Felix Held <felix-coreboot@felixheld.de> | 2021-01-14 01:40:50 +0100 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2021-01-24 18:15:46 +0000 |
commit | 8d0a609e6d1bfb48de781e7223f73ff979d0ce2e (patch) | |
tree | d3f40d275aeff99da11287de34bcc1bb62f7a2d6 /src/vendorcode/amd | |
parent | 45b0714c89db4487074e87ada13b9886c43d9ccd (diff) |
soc,vendorcode/amd/cezanne: add basic FSP integration
This is a trimmed-down version of the Cezanne FSP integration code, so
for example the UPD definitions are empty, which will be addressed
later. Since coreboot just leaves the UPD values at their default, this
is not a problem during the initial platform bring-up.
Change-Id: Ie0fc30120c2455aa2160708251e9d2f229984305
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/vendorcode/amd')
-rw-r--r-- | src/vendorcode/amd/fsp/cezanne/FspUpd.h | 22 | ||||
-rw-r--r-- | src/vendorcode/amd/fsp/cezanne/FspmUpd.h | 26 | ||||
-rw-r--r-- | src/vendorcode/amd/fsp/cezanne/FspsUpd.h | 23 | ||||
-rw-r--r-- | src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h | 51 |
4 files changed, 122 insertions, 0 deletions
diff --git a/src/vendorcode/amd/fsp/cezanne/FspUpd.h b/src/vendorcode/amd/fsp/cezanne/FspUpd.h new file mode 100644 index 0000000000..c9202cea9c --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/FspUpd.h @@ -0,0 +1,22 @@ +/** @file + * + * This file is automatically generated. + * + */ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#ifdef EFI32 +# include <FspEas.h> +# include <stdint.h> +#else +# include <fsp_h_c99.h> +#endif + +#define FSPM_UPD_SIGNATURE 0x4d5f454e415a4543 /* 'CEZANE_M' */ + +#define FSPS_UPD_SIGNATURE 0x535f454e415a4543 /* 'CEZANE_S' */ + + +#endif diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h new file mode 100644 index 0000000000..338133c33c --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -0,0 +1,26 @@ +/** @file + * + * This file is automatically generated. + * + */ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +/** Fsp M Configuration +**/ +typedef struct __packed { + uint16_t UpdTerminator; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct __packed { + /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader; + /** Offset 0x0020**/ FSPM_ARCH_UPD FspmArchUpd; + /** Offset 0x0040**/ FSP_M_CONFIG FspmConfig; +} FSPM_UPD; + +#endif diff --git a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h new file mode 100644 index 0000000000..2b7f19c602 --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h @@ -0,0 +1,23 @@ +/** @file + * + * This file is automatically generated. + * + */ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +typedef struct __packed { + uint16_t UpdTerminator; +} FSP_S_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct __packed { + /** Offset 0x0000**/ FSP_UPD_HEADER FspUpdHeader; + /** Offset 0x0020**/ FSP_S_CONFIG FspsConfig; +} FSPS_UPD; + +#endif diff --git a/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h b/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h new file mode 100644 index 0000000000..c477a4ff1f --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/fsp_h_c99.h @@ -0,0 +1,51 @@ +/** @file + * + * C99 common FSP definitions from + * Intel Firmware Support Package External Architecture Specification v2.0 + * + * These definitions come in a format that is usable outside an EFI environment. + **/ +#ifndef FSP_H_C99_H +#define FSP_H_C99_H + +#include <stdint.h> + +enum { + FSP_STATUS_RESET_REQUIRED_COLD = 0x40000001, + FSP_STATUS_RESET_REQUIRED_WARM = 0x40000002, + FSP_STATUS_RESET_REQUIRED_3 = 0x40000003, + FSP_STATUS_RESET_REQUIRED_4 = 0x40000004, + FSP_STATUS_RESET_REQUIRED_5 = 0x40000005, + FSP_STATUS_RESET_REQUIRED_6 = 0x40000006, + FSP_STATUS_RESET_REQUIRED_7 = 0x40000007, + FSP_STATUS_RESET_REQUIRED_8 = 0x40000008, +}; + +typedef enum { + EnumInitPhaseAfterPciEnumeration = 0x20, + EnumInitPhaseReadyToBoot = 0x40, + EnumInitPhaseEndOfFirmware = 0xF0 +} FSP_INIT_PHASE; + +typedef struct __packed { + uint64_t Signature; + uint8_t Revision; + uint8_t Reserved[23]; +} FSP_UPD_HEADER; + +_Static_assert(sizeof(FSP_UPD_HEADER) == 32, "FSP_UPD_HEADER not packed"); + +typedef struct __packed { + uint8_t Revision; + uint8_t Reserved[3]; + void *NvsBufferPtr; + void *StackBase; + uint32_t StackSize; + uint32_t BootLoaderTolumSize; + uint32_t BootMode; + uint8_t Reserved1[8]; +} FSPM_ARCH_UPD; + +_Static_assert(sizeof(FSPM_ARCH_UPD) == 32, "FSPM_ARCH_UPD not packed"); + +#endif /* FSP_H_C99_H */ |