diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2018-05-07 08:37:31 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-06-13 21:20:32 +0000 |
| commit | 669ba237100da680fb56950feab2b6591218e184 (patch) | |
| tree | dad9f6ff0432f2ffc8d5958aa96c605d18d62d82 /src/vendorcode/amd/pi | |
| parent | 7a2a29d0e1f2ef48a2f90c190a8135da204f4d15 (diff) | |
vc/amd/00670F00: Sync AGESA.h with PI blob
Add a new callout definition for AgesaGetTempHeapBase and displace
AgesaHeapRebase (which was merged too soon) in the ordering. Also
add its structure.
AGESA will be modified to ask coreboot for the location for temporary
storage of heap data at the end of InitPost. The old methodology is
to use 0xb0000 but the change will allow coreboot to determine the
location.
BUG=b:74518368
Change-Id: I0bc894d7842cf4b3eb728a90704277b17f4bf7be
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26145
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/pi')
| -rw-r--r-- | src/vendorcode/amd/pi/00670F00/AGESA.h | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/src/vendorcode/amd/pi/00670F00/AGESA.h b/src/vendorcode/amd/pi/00670F00/AGESA.h index ba1e50582c..41180cb323 100644 --- a/src/vendorcode/amd/pi/00670F00/AGESA.h +++ b/src/vendorcode/amd/pi/00670F00/AGESA.h @@ -68,7 +68,8 @@ #define AGESA_IDLE_AN_AP 0x00028107ul #define AGESA_WAIT_FOR_ALL_APS 0x00028108ul #define AGESA_HALT_THIS_AP 0x00028109ul -#define AGESA_HEAP_REBASE 0x0002810aul +#define AGESA_GET_TEMP_HEAP_BASE 0x0002810Aul +#define AGESA_HEAP_REBASE 0x0002810Bul // AGESA ADVANCED CALLOUTS, Memory #define AGESA_READ_SPD 0x00028140ul @@ -2528,6 +2529,15 @@ typedef struct { /// be enabled } AGESA_HALT_THIS_AP_PARAMS; +/// Parameters structure for interface call-out AgesaGetTempHeapBase +typedef struct { + IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration + /// header + OUT UINTN TempHeapAddress; ///< The address where heap + /// contents will be stored + /// temporarily +} AGESA_TEMP_HEAP_BASE_PARAMS; + /// VoltageType values typedef enum { VTYPE_CPU_VREF, ///< Cpu side Vref @@ -2615,6 +2625,12 @@ AgesaHookBeforeDramInitRecovery ( ); AGESA_STATUS +AgesaGetTempHeapBase ( + IN UINTN FcnData, + IN OUT AGESA_TEMP_HEAP_BASE_PARAMS *TempHeapBaseParams + ); + +AGESA_STATUS AgesaRunFcnOnAp ( IN UINTN ApicIdOfCore, IN AP_EXE_PARAMS *LaunchApParams |