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authorSubrata Banik <subrata.banik@intel.com>2020-08-30 13:51:44 +0530
committerSubrata Banik <subrata.banik@intel.com>2020-09-01 03:06:04 +0000
commit8e6d5f2937c169914e46b5ebc973e5df5e4290a7 (patch)
tree1550c8877877a7a9b197da65bcff76f878bee560 /src/vendorcode/amd/pi/00670F00
parentb7a68d5b05259a07a84a546e6a7e40948ba705ac (diff)
{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent
Convert 0X -> 0x Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/pi/00670F00')
-rw-r--r--src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h2
-rw-r--r--src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h2
-rw-r--r--src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h12
-rw-r--r--src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc2
4 files changed, 9 insertions, 9 deletions
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h
index 1d53990b7d..3742c19059 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Table.h
@@ -317,7 +317,7 @@ typedef union {
} PERFORMANCE_PROFILE_FEATS;
// Initializer Values for Package Type
-#define PACKAGE_TYPE_ALL 0XFFFF ///< Package Type apply all packages
+#define PACKAGE_TYPE_ALL 0xFFFF ///< Package Type apply all packages
// Core Range Initializer values.
#define COUNT_RANGE_LOW 0ul
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h
index 46906a8783..bafe84fd08 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuRegisters.h
@@ -334,7 +334,7 @@ typedef struct {
#define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register
#define MSR_CPUID_NAME_STRING1 0xC0010031ul
-#define MSR_CPUID_NAME_STRING2 0XC0010032ul
+#define MSR_CPUID_NAME_STRING2 0xC0010032ul
#define MSR_CPUID_NAME_STRING3 0xC0010033ul
#define MSR_CPUID_NAME_STRING4 0xC0010034ul
#define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h
index ee8c961e96..653d92c911 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Fch.h
@@ -2553,12 +2553,12 @@ FCH_AOAC_REG4X-7x State field
#define SBTSI_REG10 0x10
#define SBTSI_READORDER BIT5
-#define FCH_EC_ENTER_CONFIG 0X5A
-#define FCH_EC_EXIT_CONFIG 0XA5
-#define FCH_EC_REG07 0X07
-#define FCH_EC_REG30 0X30
-#define FCH_EC_REG60 0X60
-#define FCH_EC_REG61 0X61
+#define FCH_EC_ENTER_CONFIG 0x5A
+#define FCH_EC_EXIT_CONFIG 0xA5
+#define FCH_EC_REG07 0x07
+#define FCH_EC_REG30 0x30
+#define FCH_EC_REG60 0x60
+#define FCH_EC_REG61 0x61
#define FCH_IMC_ROMSIG 0x55aa55aaul
diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
index 46946327ce..152e2799c6 100644
--- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
@@ -161,7 +161,7 @@ CR0_PG = 31 # Paging Enable
CPUID_MODEL = 1
AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */
-AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */
+AMD_CPUID_L2Cache = 0x80000006 /* L2/L3 cache info */
AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */
APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */