diff options
| author | Marc Jones <marc.jones@se-eng.com> | 2015-07-19 15:20:17 -0600 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-08-07 17:59:48 +0200 |
| commit | 0b11bd0d028089288e52f9f08cdcfafc9910511b (patch) | |
| tree | e561ef6110713f774cc71f95e5ad0f26302de85c /src/vendorcode/amd/pi/00660F01/Proc | |
| parent | 9b9400dc90906fddadc0303994422ec011a8f6e7 (diff) | |
vendorcode: Move AMD sources from blobs to vendorcode
The AMD AGESA binaryPI sources were incorrectly committed to
3rdparty/blobs. Move them from blobs to vendorcode and fix
Kconfig and Makefile.inc to match.
Change-Id: I55a777553c1203464d7f7f4293b361fedcfa3283
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10982
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/pi/00660F01/Proc')
21 files changed, 9113 insertions, 0 deletions
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h new file mode 100644 index 0000000000..c4be6286b6 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h @@ -0,0 +1,92 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Register Table Related Functions + * + * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _CPU_FAM_REGISTERS_H_ +#define _CPU_FAM_REGISTERS_H_ + +/* + *-------------------------------------------------------------- + * + * M O D U L E S U S E D + * + *--------------------------------------------------------------- + */ + +/* + *-------------------------------------------------------------- + * + * D E F I N I T I O N S / M A C R O S + * + *--------------------------------------------------------------- + */ + +// This define should be equal to the total number of families +// in the cpuFamily enum. +#define MAX_CPU_FAMILIES 15 +#define MAX_CPU_REVISIONS 15 // Max Cpu Revisions Per Family + +// CPU_LOGICAL_ID.Family equates +// Family 15h equates +#define AMD_FAMILY_15_CZ 0x0004u +#define AMD_FAMILY_CZ (AMD_FAMILY_15_CZ) +#define AMD_FAMILY_15 AMD_FAMILY_15_CZ + +// Family Unknown +#define AMD_FAMILY_UNKNOWN 0x8000u + + +// Family 15h CPU_LOGICAL_ID.Revision equates +// ------------------------------------- + + // Family 15h CZ steppings +#define AMD_F15_CZ_A0 0x0001u +#define AMD_F15_CZ_A1 0x0002u + // Family 15h Unknown stepping +#define AMD_F15_UNKNOWN 0x8000u +#define AMD_F15_CZ_Ax (AMD_F15_CZ_A0 | AMD_F15_CZ_A1) +#define AMD_F15_CZ_ALL (AMD_F15_CZ_Ax) + +#define AMD_F15_ALL AMD_F15_CZ_ALL + +#endif // _CPU_FAM_REGISTERS_H_ + diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Feature/cpuCacheInit.h new file mode 100644 index 0000000000..3ee71cd624 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Feature/cpuCacheInit.h @@ -0,0 +1,137 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Execution Cache Allocation functions. + * + * Contains code for doing Execution Cache Allocation for ROM space + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _CPU_CACHE_INIT_H_ +#define _CPU_CACHE_INIT_H_ + +/*---------------------------------------------------------------------------- + * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS) + * + *---------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------- + * DEFINITIONS AND MACROS + * + *----------------------------------------------------------------------------- + */ +#define BSP_STACK_SIZE_64K 65536 +#define BSP_STACK_SIZE_32K 32768 + +#define CORE0_STACK_SIZE 16384 +#define CORE1_STACK_SIZE 4096 + +#define AMD_MTRR_FIX4K_BASE 0x268 +#define AMD_MTRR_VARIABLE_BASE6 0x20C +#define AMD_MTRR_VARIABLE_BASE7 0x20E + +#define WP_IO 0x0505050505050505ull + +#define AGESA_CACHE_SIZE_REDUCED 1 +#define AGESA_CACHE_REGIONS_ACROSS_1MB 2 +#define AGESA_CACHE_REGIONS_ACROSS_4GB 3 +#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4 +#define AGESA_CACHE_START_ADDRESS_LESS_D0000 5 +#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6 +#define AGESA_DEALLOCATE_CACHE_REGIONS 7 + +/*---------------------------------------------------------------------------- + * TYPEDEFS, STRUCTURES, ENUMS + * + *---------------------------------------------------------------------------- + */ +/// Cache-As-Ram Executable region allocation modes +typedef enum { + LimitedByL2Size, ///< Execution space must be allocated from L2 + InfiniteExe, ///< Family can support unlimited Execution space + MaxCarExeMode ///< Used as limit or bounds check +} CAR_EXE_MODE; + +/// Cache Information +typedef struct { + IN UINT32 BspStackSize; ///< Stack size of BSP + IN UINT32 Core0StackSize; ///< Stack size of primary cores + IN UINT32 Core1StackSize; ///< Stack size of all non primary cores + IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size + IN UINT32 SharedMemSize; ///< Shared memory size + IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes + IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init. + IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings + IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space +} CACHE_INFO; + +/// Merged memory region overlap type +typedef enum { + EmptySet, ///< One of the regions is zero length + Disjoint, ///< The two regions do not touch + Adjacent, ///< one region is next to the other, no gap + CommonEnd, ///< regions overlap with a common end point + Extending, ///< the 2nd region is extending the size of the 1st + Contained, ///< the 2nd region is wholely contained inside the 1st + CommonStartContained, ///< the 2nd region is contained in the 1st with a common start + Identity, ///< the two regions are the same + CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size + NotCombinable ///< the combined regions do not follow the cache block rules +} OVERLAP_TYPE; + +/// Result of merging two memory regions for cache coverage +typedef struct { + IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions + IN OUT UINT32 MergedSize; ///< Size of the merged regions + OUT UINT32 OverlapAmount; ///< the size of the overlapping section + OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap +} MERGED_CACHE_REGION; + +/*---------------------------------------------------------------------------- + * FUNCTIONS PROTOTYPE + * + *---------------------------------------------------------------------------- + */ +AGESA_STATUS +AllocateExecutionCache ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr + ); + +#endif // _CPU_CACHE_INIT_H_ + diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuEarlyInit.h new file mode 100644 index 0000000000..7efbc523e4 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuEarlyInit.h @@ -0,0 +1,213 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Reset API, and related functions and structures. + * + * Contains code that initialized the CPU after early reset. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _CPU_EARLY_INIT_H_ +#define _CPU_EARLY_INIT_H_ + + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ +AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES); + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ +//---------------------------------------------------------------------------- +// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +#define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported +#define LOW_NODE_DEVICEID 24 +#define NB_CAPABILITIES 0xE8 //Function 3 Registers +//---------------------------------------------------------------------------- +// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +/* All lengths are in bytes */ +#define MICROCODE_TRIADE_SIZE 28 +#define MICROCODE_HEADER_LENGTH 64 + +/** + * @page ucodeflag Microcode Patches Signature Guide + * + * We mark patches in the ROM with a signature so that they can be easily found + * + * @anchor Microcode Patch Signature + * @li @e Microcode Patch Signature @n + * Microcode patches are marked by adding a signature before patches in the ROM image to + * help identify where they are located. + * There're two kind of signatures. One is '$UCODE2K', it indicates there's a following patch with 2K size. + * The other is '$UCODE4K', it indicates there's a following patch with 4K size. + * If you want to know the patch level / equivalent ID, please consult the BKDG for patch header format. + * + * + */ +/// Microcode patch flag for replacement +typedef struct { + IN UINT8 MicrocodePatchesFlag[8]; ///< a flag followed by microcode +} MICROCODE_PATCHES_FLAG; + +#define UCODE_2K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '2', 'K'}}; +#define UCODE_4K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '4', 'K'}}; +#define UCODE_VS_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', 'V', 'S'}}; + +/* Offsets in UCODE PATCH Header */ +/* Note: Header is 64 bytes */ +#define DATE_CODE_OFFSET 0 // 4 bytes +#define PATCH_ID 4 // 4 bytes +#define MICROCODE_PATH_DATA_ID 8 // 2 bytes +#define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte +#define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes +#define CHIPSET_1_DEVICE_ID 16 // 4 bytes +#define CHIPSET_2_DEVICE_ID 20 // 4 bytes +#define PROCESSOR_REV_ID 24 // 2 bytes +#define CHIPSET_1_REV_ID 26 // 1 byte +#define CHIPSET_2_REV_ID 27 // 1 byte + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ +//---------------------------------------------------------------------------- +// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +/// A structure representing BrandId[15:0] from +/// CPUID Fn8000_0001_EBX +typedef struct { + UINT8 String1:4; ///< An index to a string value used to create the name string + UINT8 String2:4; ///< An index to a string value used to create the name string + UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values + UINT8 Model:7; ///< A field used to create the model number in the name string + UINT8 Socket:4; ///< Specifies the package type + UINT8 Cores:4; ///< Identifies how many physical cores are present +} AMD_CPU_BRAND_DATA; + +/// A structure containing string1 and string2 values +/// as well as information pertaining to their usage +typedef struct { + IN UINT8 Cores; ///< Appropriate number of physical cores + IN UINT8 Page; ///< This string's page number + IN UINT8 Index; ///< String index + IN UINT8 Socket; ///< Package type information + IN CONST CHAR8 *Stringstart; ///< The literal string + IN UINT8 Stringlength; ///< Number of characters in the string +} AMD_CPU_BRAND; + +/// An entire CPU brand table. +typedef struct { + UINT8 NumberOfEntries; ///< The number of entries in the table. + CONST AMD_CPU_BRAND *Table; ///< The table entries. +} CPU_BRAND_TABLE; + +/** + * Set down core register + * + * @CpuServiceInstances + * + * @param[in] FamilySpecificServices The current Family Specific Services. + * @param[in] Socket Socket ID. + * @param[in] Module Module ID in socket. + * @param[in] LeveledCores Number of core. + * @param[in] CoreLevelMode Core level mode. + * @param[in] StdHeader Header for library and services. + * + * @retval TRUE Down Core register is updated. + * @retval FALSE Down Core register is not updated. + */ +typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) ( + IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices, + IN UINT32 *Socket, + IN UINT32 *Module, + IN UINT32 *LeveledCores, + IN CORE_LEVELING_TYPE CoreLevelMode, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Reference to a method +typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER; + +/** + * Provide the interface to the Core Leveling Family Specific Services. + * + * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!). + * Each supported Family must provide an implementation for all methods in this interface, even if the + * implementation is a CommonReturn(). + */ +struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above + UINT16 Revision; ///< Interface version + // Public Methods. + PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register. +}; + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +// These are P U B L I C functions, used by IBVs +AGESA_STATUS +AmdCpuEarly ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig + ); + +// These are P U B L I C functions, used by AGESA +AGESA_STATUS +PmInitializationAtEarly ( + IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +AmdCpuEarlyInitializer ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr + ); + +#endif // _CPU_EARLY_INIT_H_ + diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuLateInit.h new file mode 100644 index 0000000000..7cef71d4c3 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuLateInit.h @@ -0,0 +1,1045 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Late Init API functions Prototypes. + * + * Contains code for doing any late CPU initialization + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _CPU_LATE_INIT_H_ +#define _CPU_LATE_INIT_H_ + +#include "Filecode.h" + +// Forward declaration needed for multi-structure mutual references. +AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE); +/*---------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +//---------------------------------------------------------------------------- +// DMI DEFINITIONS AND MACROS +// +//---------------------------------------------------------------------------- +#define AP_LATE_TASK_GET_TYPE4_TYPE7 (PROC_CPU_FEATURE_CPUDMI_FILECODE) +// SMBIOS constant definition +#define CENTRAL_PROCESSOR 0x03 +#define EXTERNAL_CLOCK_DFLT 200 +#define EXTERNAL_CLOCK_100MHZ 100 +#define P_FAMILY_UNKNOWN 0x02 +#define P_ENGINEERING_SAMPLE 0x00 +#define P_CHARACTERISTICS 0x4 +#define CACHE_CFG_L1 0x180 +#define CACHE_CFG_L2 0x181 +#define CACHE_CFG_L3 0x182 +#define SRAM_TYPE 0x10 +#define ERR_CORRECT_TYPE 0x06 +#define CACHE_TYPE 0x05 +#define DMI_ASSOCIATIVE_OTHER 0x01 +#define DMI_ASSOCIATIVE_UNKNOWN 0x02 +#define DMI_ASSOCIATIVE_DIRECT_MAPPED 0x03 +#define DMI_ASSOCIATIVE_2_WAY 0x04 +#define DMI_ASSOCIATIVE_4_WAY 0x05 +#define DMI_ASSOCIATIVE_FULLY 0x06 +#define DMI_ASSOCIATIVE_8_WAY 0x07 +#define DMI_ASSOCIATIVE_16_WAY 0x08 +#define DMI_ASSOCIATIVE_12_WAY 0x09 +#define DMI_ASSOCIATIVE_24_WAY 0x0A +#define DMI_ASSOCIATIVE_32_WAY 0x0B +#define DMI_ASSOCIATIVE_48_WAY 0x0C +#define DMI_ASSOCIATIVE_64_WAY 0x0D +#define DMI_ASSOCIATIVE_20_WAY 0x0E +#define SOCKET_POPULATED 0x40 +#define CPU_STATUS_UNKNOWN 0x00 +#define CPU_STATUS_ENABLED 0x01 + +// Processor Upgrade Definition +#define P_UPGRADE_UNKNOWN 0x02 +#define P_UPGRADE_NONE 0x06 + +//---------------------------------------------------------------------------- +// CDIT DEFINITIONS AND MACROS +// +//---------------------------------------------------------------------------- +#define AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH 4 // Num domains is a 4-bytes unsigned integer + + +//---------------------------------------------------------------------------- +// P-STATE DEFINITIONS AND MACROS +// +//---------------------------------------------------------------------------- +//------------------------------------- +// ERROR Codes +//------------------------------------- +#define NO_ERROR 0x0 +#define USER_DISABLE_ERROR 0x01 // User disabled SSDT generation +#define CORES_MISSMATCH_PSS_ERROR 0x02 // No PSS match +#define PNOW_SUPPORT_ERROR 0x04 // One of the Cores do not support PNOW! +#define PWR_FREQ_MATCH_ERROR 0x08 // FREQ and PWR mismatch +#define NO_PSS_SIZE_ERROR 0x10 // Error in PSS Size +#define INVALID_PSTATE_ERROR 0x20 // Invalid Max or only 1 P-State available +#define NO_PSS_ENTRY 0x0FFFFul +#define INVALID_FREQ 0x0FFFFFFFFul + +//------------------------- +// Default definitions +// AMD BKDG default values +//------------------------- +#define DEFAULT_ISOCH_RELIEF_TIME IRT_80uS +#define DEFAULT_RAMP_VOLTAGE_OFFSET RVO_50mV +#define DEFAULT_MAX_VOLTAGE_STEP MVS_25mV +#define DEFAULT_PERF_PRESENT_CAP 0 // default for Desktop +#define DEFAULT_VOLTAGE_STABLE_TIME (100 / 20) // 100uS +#define DEFAULT_PLL_LOCK_TIME 2 // 2uS +#define DEFAULT_TRANSITION_LATENCY 100 // 100uS +#define DEFAULT_BUS_MASTER_LATENCY 9 // 9uS +#define DEFAULT_CPU_SCOPE_NUMBER "0UPC" + +// Defines for Common ACPI +// ----------------------------- +#define SCOPE_OPCODE 0x10 +#define NAME_OPCODE 0x08 +#define METHOD_OPCODE 0x14 +#define PACKAGE_OPCODE 0x12 +#define BUFFER_OPCODE 0x11 +#define BYTE_PREFIX_OPCODE 0x0A +#define WORD_PREFIX_OPCODE 0x0B +#define DWORD_PREFIX_OPCODE 0x0C +#define RETURN_OPCODE 0xA4 +#define ACPI_BUFFER 0x080A0B11ul + +// Generic Register Descriptor (GDR) Fields +#define GDR_ASI_SYSTEM_IO 0x01 // Address Space ID +#define GDR_ASZ_BYTE_ACCESS 0x01 // Address Size + +// Defines for ACPI Scope Table +// ---------------------------- +#define SCOPE_LENGTH (SCOPE_STRUCT_SIZE + \ + PCT_STRUCT_SIZE + \ + PSS_HEADER_STRUCT_SIZE + \ + PSS_BODY_STRUCT_SIZE + \ + PPC_HEADER_BODY_STRUCT_SIZE) +#define SCOPE_VALUE1 0x5C +#define SCOPE_VALUE2 0x2E +#define SCOPE_NAME__ '_' +#define SCOPE_NAME_P 'P' +#define SCOPE_NAME_R 'R' +#define SCOPE_NAME_S 'S' +#define SCOPE_NAME_B 'B' +#define SCOPE_NAME_C 'C' +#define SCOPE_NAME_U 'U' +#define SCOPE_NAME_0 '0' +#define SCOPE_NAME_1 '1' +#define SCOPE_NAME_2 '2' +#define SCOPE_NAME_3 '3' +#define SCOPE_NAME_A 'A' + +#ifdef OEM_SCOPE_NAME + #if (OEM_SCOPE_NAME > 'Z') || (OEM_SCOPE_NAME < 'A') + #error "OEM_SCOPE_NAME: it should be only one char long AND a valid letter (A~Z)" + #endif + #define SCOPE_NAME_VALUE OEM_SCOPE_NAME +#else + #define SCOPE_NAME_VALUE SCOPE_NAME_C +#endif // OEM_SCOPE_NAME + +#ifdef OEM_SCOPE_NAME1 + #if (!(((OEM_SCOPE_NAME1 >= 'A') && (OEM_SCOPE_NAME1 <= 'Z')) || \ + ((OEM_SCOPE_NAME1 >= '0') && (OEM_SCOPE_NAME1 <= '9')) || \ + (OEM_SCOPE_NAME1 == '_'))) + #error "OEM_SCOPE_NAME1: it should be only one char long AND a valid letter (0~9, A~F)" + #endif + #define SCOPE_NAME_VALUE1 OEM_SCOPE_NAME1 +#else + #define SCOPE_NAME_VALUE1 SCOPE_NAME_0 +#endif // OEM_SCOPE_NAME + +// Defines for PCT Control and Status Table +// ---------------------------------------- +#define PCT_NAME__ '_' +#define PCT_NAME_P 'P' +#define PCT_NAME_C 'C' +#define PCT_NAME_T 'T' +#define PCT_VALUE1 0x11022C12ul +#define PCT_VALUE2 0x0A14 +#define PCT_VALUE3 0x11 +#define GENERIC_REG_DESCRIPTION 0x82 +#define PCT_LENGTH 0x0C +#define PCT_ADDRESS_SPACE_ID 0x7F +#define PCT_REGISTER_BIT_WIDTH 0x40 +#define PCT_REGISTER_BIT_OFFSET 0x00 +#define PCT_RESERVED 0x00 +#define PCT_CONTROL_REG_LO 0xC0010062ul +#define PCT_CONTROL_REG_HI 0x00 +#define PCT_VALUE4 0x14110079ul +#define PCT_VALUE5 0x110A +#define PCT_STATUS_REG_LO 0x00 +#define PCT_STATUS_REG_HI 0x00 +#define PCT_VALUE6 0x0079 + + +// Defines for PSS Header Table +// ---------------------------- +#define PSS_NAME__ '_' +#define PSS_NAME_X 'X' +#define PSS_NAME_P 'P' +#define PSS_NAME_S 'S' +#define PSS_LENGTH (sizeof pssBodyStruct + 3) +#define NUM_OF_ITEMS_IN_PSS 0x00 + + +// Defines for PSS Header Table +// ---------------------------- +#define PSS_PKG_LENGTH 0x20 // PSS_BODY_STRUCT_SIZE - 1 +#define PSS_NUM_OF_ELEMENTS 0x06 +#define PSS_FREQUENCY 0x00 +#define PSS_POWER 0x00 +#define PSS_TRANSITION_LATENCY DEFAULT_TRANSITION_LATENCY +#define PSS_BUS_MASTER_LATENCY DEFAULT_BUS_MASTER_LATENCY +#define PSS_CONTROL ((DEFAULT_ISOCH_RELIEF_TIME << 30) + \ + (DEFAULT_RAMP_VOLTAGE_OFFSET << 28) + \ + (DEFAULT_EXT_TYPE << 27) + \ + (DEFAULT_PLL_LOCK_TIME << 20) + \ + (DEFAULT_MAX_VOLTAGE_STEP << 18) + \ + (DEFAULT_VOLTAGE_STABLE_TIME << 11) + \ + (PSS_VID << 6) + PSS_FID) +#define PSS_STATUS (DEFAULT_EXTENDED_TYPE << 11) + (PSS_VID << 6) + (PSS_FID) + +// Defines for XPSS Header Table +// ---------------------------- +#define XPSS_PKG_LENGTH 0x47 // XPSS_BODY_STRUCT_SIZE - 1 +#define XPSS_NUM_OF_ELEMENTS 0x08 +#define XPSS_ACPI_BUFFER 0x080A0B11ul + + +// Defines for PPC Header Table +// ---------------------------- +#define PPC_NAME__ '_' +#define PPC_NAME_P 'P' +#define PPC_NAME_C 'C' +#define PPC_NAME_V 'V' +#define PPC_METHOD_FLAGS 0x00; +#define PPC_VALUE1 0x0A; + +// Defines for PSD Header Table +// ---------------------------- +#define PSD_NAME__ '_' +#define PSD_NAME_P 'P' +#define PSD_NAME_S 'S' +#define PSD_NAME_D 'D' +#define PSD_HEADER_LENGTH (PSD_BODY_STRUCT_SIZE + 2) +#define PSD_VALUE1 0x01 + + +// Defines for PSD Header Table +// ---------------------------- +#define PSD_PKG_LENGTH (PSD_BODY_STRUCT_SIZE - 1) +#define NUM_OF_ENTRIES 0x05 +#define PSD_NUM_OF_ENTRIES 0x05 +#define PSD_REVISION 0x00 +#define PSD_DEPENDENCY_DOMAIN 0x00 +#define PSD_COORDINATION_TYPE_HW_ALL 0xFE +#define PSD_COORDINATION_TYPE_SW_ANY 0xFD +#define PSD_COORDINATION_TYPE_SW_ALL 0xFC +#define PSD_NUM_OF_PROCESSORS 0x01 +#define PSD_TWO_CORES_PER_COMPUTE_UNIT 0x02 +#define PSD_THREE_CORES_PER_COMPUTE_UNIT 0x03 +#define PSD_FOUR_CORES_PER_COMPUTE_UNIT 0x04 + + +#define CUSTOM_PSTATE_FLAG 0x55 +#define PSTATE_FLAG_1 0x55 +#define TARGET_PSTATE_FLAG 0xAA +#define PSTATE_FLAG_2 0xAA + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *---------------------------------------------------------------------------------------- + */ +//---------------------------------------------------------------------------- +// ACPI P-States AML TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- + +//-------------------------------------------- +// AML code definition +// (Scope) +//--------------------------------------------- +/// SCOPE +typedef struct _SCOPE { + UINT8 ScopeOpcode; ///< Opcode + UINT16 ScopeLength; ///< Scope Length + UINT8 ScopeValue1; ///< Value1 + UINT8 ScopeValue2; ///< Value2 + UINT8 ScopeNamePt1a__; ///< Name Pointer + UINT8 ScopeNamePt1a_P; ///< Name Pointer + UINT8 ScopeNamePt1a_R; ///< Name Pointer + UINT8 ScopeNamePt1b__; ///< Name Pointer + UINT8 ScopeNamePt2a_C; ///< Name Pointer + UINT8 ScopeNamePt2a_P; ///< Name Pointer + UINT8 ScopeNamePt2a_U; ///< Name Pointer + UINT8 ScopeNamePt2a_0; ///< Name Pointer +} SCOPE; +#define SCOPE_STRUCT_SIZE 13 // 13 Bytes + +//-------------------------------------------- +// AML code definition +// (PCT Header and Body) +//--------------------------------------------- + +///Performance Control Header +typedef struct _PCT_HEADER_BODY { + UINT8 NameOpcode; ///< Opcode + UINT8 PctName_a__; ///< String "_" + UINT8 PctName_a_P; ///< String "P" + UINT8 PctName_a_C; ///< String "C" + UINT8 PctName_a_T; ///< String "T" + UINT32 Value1; ///< Value1 + UINT16 Value2; ///< Value2 + UINT8 Value3; ///< Value3 + UINT8 GenericRegDescription1; ///< Generic Reg Description + UINT16 Length1; ///< Length1 + UINT8 AddressSpaceId1; ///< PCT Address Space ID + UINT8 RegisterBitWidth1; ///< PCT Register Bit Width + UINT8 RegisterBitOffset1; ///< PCT Register Bit Offset + UINT8 Reserved1; ///< Reserved + UINT32 ControlRegAddressLo; ///< Control Register Address Low + UINT32 ControlRegAddressHi; ///< Control Register Address High + UINT32 Value4; ///< Value4 + UINT16 Value5; ///< Value 5 + UINT8 GenericRegDescription2; ///< Generic Reg Description + UINT16 Length2; ///< Length2 + UINT8 AddressSpaceId2; ///< PCT Address Space ID + UINT8 RegisterBitWidth2; ///< PCT Register Bit Width + UINT8 RegisterBitOffset2; ///< PCT Register Bit Offset + UINT8 Reserved2; ///< Reserved + UINT32 StatusRegAddressLo; ///< Control Register Address Low + UINT32 StatusRegAddressHi; ///< Control Register Address High + UINT16 Value6; ///< Values +} PCT_HEADER_BODY; +#define PCT_STRUCT_SIZE 50 // 50 Bytes + + +//-------------------------------------------- +// AML code definition +// (PSS Header) +//-------------------------------------------- +///Performance Supported States Header +typedef struct _PSS_HEADER { + UINT8 NameOpcode; ///< Opcode + UINT8 PssName_a__; ///< String "_" + UINT8 PssName_a_P; ///< String "P" + UINT8 PssName_a_S; ///< String "S" + UINT8 PssName_b_S; ///< String "S" + UINT8 PkgOpcode; ///< Package Opcode + UINT16 PssLength; ///< PSS Length + UINT8 NumOfItemsInPss; ///< Number of Items in PSS +} PSS_HEADER; +#define PSS_HEADER_STRUCT_SIZE 9 // 9 Bytes + + +//-------------------------------------------- +// AML code definition +// (PSS Body) +//-------------------------------------------- +///Performance Supported States Body +typedef struct _PSS_BODY { + UINT8 PkgOpcode; ///< Package Opcode + UINT8 PkgLength; ///< Package Length + UINT8 NumOfElements; ///< Number of Elements + UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 + UINT32 Frequency; ///< Frequency + UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 + UINT32 Power; ///< Power + UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 + UINT32 TransitionLatency; ///< Transition Latency + UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4 + UINT32 BusMasterLatency; ///< Bus Master Latency + UINT8 DwordPrefixOpcode5; ///< Prefix Opcode5 + UINT32 Control; ///< Control + UINT8 DwordPrefixOpcode6; ///< Prefix Opcode6 + UINT32 Status; ///< Status +} PSS_BODY; +#define PSS_BODY_STRUCT_SIZE 33 // 33 Bytes + + +/*-------------------------------------------- + * AML code definition + * (XPSS Header) + *-------------------------------------------- + */ +/// Extended PSS Header +typedef struct _XPSS_HEADER { + UINT8 NameOpcode; ///< 08h + UINT8 XpssName_a_X; ///< String "X" + UINT8 XpssName_a_P; ///< String "P" + UINT8 XpssName_a_S; ///< String "S" + UINT8 XpssName_b_S; ///< String "S" + UINT8 PkgOpcode; ///< 12h + UINT16 XpssLength; ///< XPSS Length + UINT8 NumOfItemsInXpss; ///< Number of Items in XPSS +} XPSS_HEADER; +#define XPSS_HEADER_STRUCT_SIZE 9 // 9 Bytes + +/*-------------------------------------------- + * AML code definition + * (XPSS Body) + *-------------------------------------------- + */ +/// Extended PSS Body +typedef struct _XPSS_BODY { + UINT8 PkgOpcode; ///< 12h + UINT8 PkgLength; ///< Package Length + UINT8 XpssValueTbd; ///< XPSS Value + UINT8 NumOfElements; ///< Number of Elements + UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 + UINT32 Frequency; ///< Frequency + UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 + UINT32 Power; ///< Power + UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 + UINT32 TransitionLatency; ///< Transition Latency + UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4 + UINT32 BusMasterLatency; ///< Bus Master Latency + UINT32 ControlBuffer; ///< Control Buffer + UINT32 ControlLo; ///< Control Low + UINT32 ControlHi; ///< Control High + UINT32 StatusBuffer; ///< Status Buffer + UINT32 StatusLo; ///< Status Low + UINT32 StatusHi; ///< Status High + UINT32 ControlMaskBuffer; ///< Control Mask Buffer + UINT32 ControlMaskLo; ///< Control Mask Low + UINT32 ControlMaskHi; ///< Control Mask High + UINT32 StatusMaskBuffer; ///< Status Mask Buffer + UINT32 StatusMaskLo; ///< Status Mask Low + UINT32 StatusMaskHi; ///< Status Mask High +} XPSS_BODY; +#define XPSS_BODY_STRUCT_SIZE 72 // 72 Bytes + +/*-------------------------------------------- + * AML code definition + * (PPC Header and Body) + *-------------------------------------------- + */ +/// Performance Present Capabilities Header +typedef struct _PPC_HEADER_BODY { + UINT8 NameOpcode; ///< Name Opcode + UINT8 PpcName_a_P; ///< String "P" + UINT8 PpcName_b_P; ///< String "P" + UINT8 PpcName_a_C; ///< String "C" + UINT8 PpcName_a_V; ///< String "V" + UINT8 Value1; ///< Value + UINT8 DefaultPerfPresentCap; ///< Default Perf Present Cap + UINT8 MethodOpcode; ///< Method Opcode + UINT8 PpcLength; ///< Method Length + UINT8 PpcName_a__; ///< String "_" + UINT8 PpcName_c_P; ///< String "P" + UINT8 PpcName_d_P; ///< String "P" + UINT8 PpcName_b_C; ///< String "C" + UINT8 MethodFlags; ///< Method Flags + UINT8 ReturnOpcode; ///< Return Opcoce + UINT8 PpcName_e_P; ///< String "P" + UINT8 PpcName_f_P; ///< String "P" + UINT8 PpcName_c_C; ///< String "C" + UINT8 PpcName_b_V; ///< String "V" + +} PPC_HEADER_BODY; +#define PPC_HEADER_BODY_STRUCT_SIZE 19 // 19 Bytes +#define PPC_METHOD_LENGTH 11 // 11 Bytes + + +/*-------------------------------------------- + * AML code definition + * (PSD Header) + *-------------------------------------------- + */ +/// P-State Dependency Header +typedef struct _PSD_HEADER { + UINT8 NameOpcode; ///< Name Opcode + UINT8 PsdName_a__; ///< String "_" + UINT8 PsdName_a_P; ///< String "P" + UINT8 PsdName_a_S; ///< String "S" + UINT8 PsdName_a_D; ///< String "D" + UINT8 PkgOpcode; ///< Package Opcode + UINT8 PsdLength; ///< PSD Length + UINT8 Value1; ///< Value +} PSD_HEADER; +#define PSD_HEADER_STRUCT_SIZE 8 // 8 Bytes + +/*-------------------------------------------- + * AML code definition + * (PSD Body) + *-------------------------------------------- + */ +/// P-State Dependency Body +typedef struct _PSD_BODY { + UINT8 PkgOpcode; ///< Package Opcode + UINT8 PkgLength; ///< Package Length + UINT8 NumOfEntries; ///< Number of Entries + UINT8 BytePrefixOpcode1; ///< Prefix Opcode1 in Byte + UINT8 PsdNumOfEntries; ///< PSD Number of Entries + UINT8 BytePrefixOpcode2; ///< Prefix Opcode2 in Byte + UINT8 PsdRevision; ///< PSD Revision + UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 in DWord + UINT32 DependencyDomain; ///< Dependency Domain + UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 in DWord + UINT32 CoordinationType; ///< (0xFC = SW_ALL, 0xFD = SW_ANY, 0xFE = HW_ALL) + UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 in DWord + UINT32 NumOfProcessors; ///< Number of Processors +} PSD_BODY; +#define PSD_BODY_STRUCT_SIZE 22 // 22 Bytes + +//---------------------------------------------------------------------------- +// WHEA TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- + +/// HEST MCE TABLE +typedef struct _AMD_HEST_MCE_TABLE { + UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_MCE structure. + UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into + UINT32 GlobCapInitDataMSD; ///< the machine check global capability register(MCG_CAP). + UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will program into + UINT32 GlobCtrlInitDataMSD; ///< the machine check global control register(MCG_CTL). + UINT8 NumHWBanks; ///< The number of hardware error reporting banks. + UINT8 Rsvd[7]; ///< reserve 7 bytes as spec's required +} AMD_HEST_MCE_TABLE; + +/// HEST CMC TABLE +typedef struct _AMD_HEST_CMC_TABLE { + UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_CMC structure. + UINT8 NumHWBanks; ///< The number of hardware error reporting banks. + UINT8 Rsvd[3]; ///< reserve 3 bytes as spec's required +} AMD_HEST_CMC_TABLE; + +/// HEST BANK +typedef struct _AMD_HEST_BANK { + UINT8 BankNum; ///< Zero-based index identifies the machine check error bank. + UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check bank + ///< is to be cleared during system initialization. + UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register + UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be + ///< modified by the OS. If the bit for the associated parameter is + ///< set, the parameter is writable by the OS. + UINT32 CtrlRegMSRAddr; ///< Address of the hardware bank's control MSR. Ignored if zero. + + UINT32 CtrlInitDataLSD; ///< This is the value the OS will program into the machine check + UINT32 CtrlInitDataMSD; ///< bank's control register + UINT32 StatRegMSRAddr; ///< Address of the hardware bank's MCi_STAT MSR. Ignored if zero. + UINT32 AddrRegMSRAddr; ///< Address of the hardware bank's MCi_ADDR MSR. Ignored if zero. + UINT32 MiscRegMSRAddr; ///< Address of the hardware bank's MCi_MISC MSR. Ignored if zero. +} AMD_HEST_BANK; + +/// Initial data of AMD_HEST_BANK +typedef struct _AMD_HEST_BANK_INIT_DATA { + UINT32 CtrlInitDataLSD; ///< Initial data of CtrlInitDataLSD + UINT32 CtrlInitDataMSD; ///< Initial data of CtrlInitDataMSD + UINT32 CtrlRegMSRAddr; ///< Initial data of CtrlRegMSRAddr + UINT32 StatRegMSRAddr; ///< Initial data of StatRegMSRAddr + UINT32 AddrRegMSRAddr; ///< Initial data of AddrRegMSRAddr + UINT32 MiscRegMSRAddr; ///< Initial data of MiscRegMSRAddr +} AMD_HEST_BANK_INIT_DATA; + +/// MSR179 Global Machine Check Capabilities data struct +typedef struct _MSR_MCG_CAP_STRUCT { + UINT64 Count:8; ///< Indicates the number of + ///< error-reporting banks visible to each core + UINT64 McgCtlP:1; ///< 1=The machine check control registers + UINT64 Rsvd:55; ///< reserved +} MSR_MCG_CAP_STRUCT; + +/// Initial data of WHEA +typedef struct _AMD_WHEA_INIT_DATA { + UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into the machine + UINT32 GlobCapInitDataMSD; ///< Check global capability register + UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will grogram into the machine + UINT32 GlobCtrlInitDataMSD; ///< Check global control register + UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check + ///< bank is to be cleared during system initialization + UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register + UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be + ///< modified by the OS. If the bit for the associated parameter is + ///< set, the parameter is writable by the OS. + UINT8 HestBankNum; ///< Number of HEST Bank + AMD_HEST_BANK_INIT_DATA *HestBankInitData; ///< Pointer to Initial data of HEST Bank +} AMD_WHEA_INIT_DATA; + +//---------------------------------------------------------------------------- +// DMI TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +/// DMI brand information +typedef struct { + UINT16 String1:4; ///< String1 + UINT16 String2:4; ///< String2 + UINT16 Model:7; ///< Model + UINT16 Pg:1; ///< Page +} BRAND_ID; + +/// DMI cache information +typedef struct { + UINT32 L1CacheSize; ///< L1 cache size + UINT8 L1CacheAssoc; ///< L1 cache associativity + UINT32 L2CacheSize; ///< L2 cache size + UINT8 L2CacheAssoc; ///< L2 cache associativity + UINT32 L3CacheSize; ///< L3 cache size + UINT8 L3CacheAssoc; ///< L3 cache associativity +} CPU_CACHE_INFO; + +/// DMI processor information +typedef struct { + UINT8 ExtendedFamily; ///< Extended Family + UINT8 ExtendedModel; ///< Extended Model + UINT8 BaseFamily; ///< Base Family + UINT8 BaseModel; ///< Base Model + UINT8 Stepping; ///< Stepping + UINT8 PackageType; ///< PackageType + BRAND_ID BrandId; ///< BrandId which contains information about String1, String2, Model and Page + UINT8 TotalCoreNumber; ///< Number of total cores + UINT8 EnabledCoreNumber; ///< Number of enabled cores + UINT8 ProcUpgrade; ///< ProcUpdrade + CPU_CACHE_INFO CacheInfo; ///< CPU cache info +} CPU_TYPE_INFO; + +/// A structure containing processor name string and +/// the value that should be provide to DMI type 4 processor family +typedef struct { + IN CONST CHAR8 *Stringstart; ///< The literal string + IN UINT8 T4ProcFamilySetting; ///< The value set to DMI type 4 processor family +} CPU_T4_PROC_FAMILY; + +/// DMI ECC information +typedef struct { + BOOLEAN EccCapable; ///< ECC Capable +} CPU_GET_MEM_INFO; + +/* Transfer vectors for DMI family specific routines */ +typedef VOID OPTION_DMI_GET_CPU_INFO ( + IN OUT CPU_TYPE_INFO *CpuInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef VOID OPTION_DMI_GET_PROC_FAMILY ( + IN OUT UINT8 *T4ProcFamily, + IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, + IN CPU_TYPE_INFO *CpuInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef UINT8 OPTION_DMI_GET_VOLTAGE ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef UINT16 OPTION_DMI_GET_MAX_SPEED ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef UINT16 OPTION_DMI_GET_EXT_CLOCK ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +typedef VOID OPTION_DMI_GET_MEM_INFO ( + IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +/// Brand table entry format +typedef struct { + UINT8 PackageType; ///< Package type + UINT8 PgOfBrandId; ///< Page + UINT8 NumberOfCores; ///< Number of cores + UINT8 String1ofBrandId; ///< String1 + UINT8 ValueSetToDmiTable; ///< The value which will should be set to DMI table +} DMI_BRAND_ENTRY; + +/// Family specific data table structure +struct _PROC_FAMILY_TABLE { + UINT64 ProcessorFamily; ///< processor + OPTION_DMI_GET_CPU_INFO *DmiGetCpuInfo; ///< transfer vectors + OPTION_DMI_GET_PROC_FAMILY *DmiGetT4ProcFamily; ///< Get DMI type 4 processor family information + OPTION_DMI_GET_VOLTAGE *DmiGetVoltage; ///< vector for reading voltage + OPTION_DMI_GET_MAX_SPEED *DmiGetMaxSpeed; ///< vector for reading speed + OPTION_DMI_GET_EXT_CLOCK *DmiGetExtClock; ///< vector for reading external clock speed + OPTION_DMI_GET_MEM_INFO *DmiGetMemInfo; ///< Get memory information + UINT8 LenBrandList; ///< size of brand table + CONST DMI_BRAND_ENTRY *DmiBrandList; ///< translate brand info to DMI identifier +}; + +//---------------------------------------------------------------------------- +// TYPEDEFS, STRUCTURES, ENUMS +// +//---------------------------------------------------------------------------- +/// Format for Header +typedef struct { + UINT8 Sign[4]; ///< Signature + UINT32 TableLength; ///< Table Length + UINT8 Revision; ///< Revision + UINT8 Checksum; ///< Checksum + UINT8 OemId[6]; ///< OEM ID + UINT8 OemTableId[8]; ///< OEM Tabled ID + UINT32 OemRev; ///< OEM Revision + UINT8 CreatorId[4]; ///< Creator ID + UINT32 CreatorRev; ///< Creator Revision +} ACPI_TABLE_HEADER; + +//---------------------------------------------------------------------------- +// CRAT TYPEDEFS, STRUCTURES, ENUMS +// Component Resource Affinity Table +//---------------------------------------------------------------------------- +/// Format for CRAT Header +typedef struct { + UINT8 Sign[4]; ///< CRAT, Signature for the Component Resource Affinity Table. + UINT32 Length; ///< Length, in bytes, of the entire CRAT + UINT8 Revision; ///< 0 + UINT8 Checksum; ///< Entire table must sum to zero. + UINT8 OemId[6]; ///< OEM ID + UINT8 OemTableId[8]; ///< OEM Tabled ID + UINT32 OemRev; ///< OEM Revision + UINT8 CreatorId[4]; ///< Creator ID + UINT32 CreatorRev; ///< Creator Revision + UINT32 TotalEntries; ///< total number[n] of entries in the CRAT + UINT16 NumDomains; ///< Number of HSA proximity domains + UINT8 Reserved[6]; ///< Reserved +} CRAT_HEADER; + +/// Flags field of the CRAT HSA Processing Unit Affinity Structure +typedef struct { + UINT32 Enabled:1; ///< Enabled + UINT32 HotPluggable:1; ///< Hot Pluggable + UINT32 CpuPresent:1; ///< Cpu Present + UINT32 GpuPresent:1; ///< Gpu Present + UINT32 IommuPresent:1; ///< IOMMU Present + UINT32 :27; ///< Reserved +} CRAT_HSA_PROCESSING_UNIT_FLAG; + +/// CRAT HSA Processing Unit Affinity Structure +typedef struct { + UINT8 Type; ///< 0 - CRAT HSA Processing Unit Structure + UINT8 Length; ///< 40 + UINT16 Reserved; ///< Reserved + CRAT_HSA_PROCESSING_UNIT_FLAG Flags; ///< Flags - HSA Processing Unit Affinity Structure + UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to + UINT32 ProcessorIdLow; ///< Low value of the logical processor included in this HSA proximity domain + UINT16 NumCPUCores; ///< Indicates count of CCompute execution units present in this APU node. + UINT16 NumSIMDCores; ///< Indicates maximum count of HCompute SIMD cores present in this node. + UINT16 MaxWavesSIMD; ///< This identifies the max. number of launched waves per SIMD. + UINT16 IoCount; ///< Number of discoverable IO Interfaces connecting this node to other components. + UINT16 HSACapability; ///< Must be 0 + UINT16 LDSSizeInKB; ///< Size of LDS memory per SIMD Wavefront + UINT8 WaveFrontSize; ///< 64, may be 32 for some FSA based architectures + UINT8 NumBanks; ///< Number of Banks or "Shader Engines", typically 1 or 2 + UINT16 uEngineIdentifier; ///< Identifier (Rev) of the GPU uEngine or firmware + UINT8 NumArrays; ///< Number of SIMD Arrays per Engine + UINT8 NumCUPerArray; ///< Number of Compute Units (CU) per SIMD Array + UINT8 NumSIMDPerCU; ///< Number of SIMD representing a Compute Unit + UINT8 MaxSlotsScratchCU; ///< Max. Number of temp. memory ("scratch") wave slots + ///< available to access, may be 0 if HW has no restrictions + UINT8 Reserved1[4]; ///< Reserved +} CRAT_HSA_PROCESSING_UNIT; + +/// Flags field of the CRAT Memory Affinity Structure +typedef struct { + UINT32 Enabled:1; ///< Enabled + UINT32 HotPluggable:1; ///< Hot Pluggable + UINT32 NonVolatile:1; ///< If set, the memory region represents Non-Volatile memory + UINT32 :29; ///< Reserved +} CRAT_MEMORY_FLAG; + +/// CRAT Memory Affinity Structure +typedef struct { + UINT8 Type; ///< 1 - CRAT Memory Affinity Structure + UINT8 Length; ///< 40 + UINT16 Reserved; ///< Reserved + CRAT_MEMORY_FLAG Flags; ///< Flags - Memory Affinity Structure. Indicates whether the region of memory is enabled and can be hot plugged + UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to + UINT32 BaseAddressLow; ///< Low 32Bits of the Base Address of the memory range + UINT32 BaseAddressHigh; ///< High 32Bits of the Base Address of the memory range + UINT32 LengthLow; ///< Low 32Bits of the length of the memory range + UINT32 LengthHigh; ///< High 32Bits of the length of the memory range + UINT32 Width; ///< Memory width - Specifies the number of parallel bits of the memory interface + UINT8 Reserved1[8]; ///< Reserved +} CRAT_MEMORY; + +/// Flags field of the CRAT Cache Affinity structure +typedef struct { + UINT32 Enabled:1; ///< Enabled + UINT32 DataCache:1; ///< 1 if cache includes data + UINT32 InstructionCache:1; ///< 1 if cache includes instructions + UINT32 CpuCache:1; ///< 1 if cache is part of CPU functionality + UINT32 SimdCache:1; ///< 1 if cache is part of SIMD functionality + UINT32 :27; ///< Reserved +} CRAT_CACHE_FLAG; + +/// CRAT Cache Affinity Structure +typedef struct { + UINT8 Type; ///< 2 - CRAT Cache Affinity Structure + UINT8 Length; ///< 64 + UINT16 Reserved; ///< Reserved + CRAT_CACHE_FLAG Flags; ///< Flags - Cache Affinity Structure. Indicates whether the region of cache is enabled + UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component + UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor + UINT32 CacheSize; ///< Cache size in KB + UINT8 CacheLevel; ///< Integer representing level: 1, 2, 3, 4, etc. + UINT8 LinesPerTag; ///< Cache Lines per tag + UINT16 CacheLineSize; ///< Cache line size in bytes + UINT8 Associativity; ///< Cache associativity + ///< The associativity fields are encoded as follows: + ///< 00h: Reserved. + ///< 01h: Direct mapped. + ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.) + ///< FFh: Fully associative + UINT8 CacheProperties; ///< Cache Properties bits [2:0] represent Inclusive/Exclusive property encoded. + ///< 0: Cache is strictly exclusive to lower level caches. + ///< 1: Cache is mostly exclusive to lower level caches. + ///< 2: Cache is strictly inclusive to lower level caches. + ///< 3: Cache is mostly inclusive to lower level caches. + ///< 4: Cache is a "constant cache" (= explicit update) + ///< 5: Cache is a "specialty cache" (e.g. Texture cache) + ///< 6-7: Reserved + ///< CacheProperties bits [7:3] are reserved + UINT16 CacheLatency; ///< Cost of time to access cache described in nanoseconds. + UINT8 Reserved1[8]; ///< Reserved +} CRAT_CACHE; + +/// Flags field of the CRAT TLB Affinity structure +typedef struct { + UINT32 Enabled:1; ///< Enabled + UINT32 DataTLB:1; ///< 1 if TLB includes translation information for data. + UINT32 InstructionTLB:1; ///< 1 if TLB includes translation information for instructions. + UINT32 CpuTLB:1; ///< 1 if TLB is part of CPU functionality + UINT32 SimdTLB:1; ///< 1 if TLB is part of SIMD functionality + UINT32 TLB4KBase256:1; ///< 1 if value in table is factored by 256 to get number of 4K entries + UINT32 :1; ///< Reserved + UINT32 TLB2MBase256:1; ///< 1 if value in table is factored by 256 to get number of 2M entries + UINT32 :1; ///< Reserved + UINT32 TLB1GBase256:1; ///< 1 if value in table is factored by 256 to get number of 1G entries + UINT32 :22; ///< Reserved +} CRAT_TLB_FLAG; + +/// CRAT TLB Affinity Structure +typedef struct { + UINT8 Type; ///< 3 - CRAT TLB Affinity Structure + UINT8 Length; ///< 64 + UINT16 Reserved; ///< Reserved + CRAT_TLB_FLAG Flags; ///< Flags - TLB Affinity Structure. Indicates whether the TLB is enabled and defined + UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component. + UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor + UINT32 TlbLevel; ///< Integer representing level: 1, 2, 3, 4, etc. + UINT8 DataTlbAssociativity2MB; ///< Data TLB associativity for 2MB pages + ///< The associativity fields are encoded as follows: + ///< 00h: Reserved. + ///< 01h: Direct mapped. + ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.) + ///< FFh: Fully associative. + UINT8 DataTlbSize2MB; ///< Data TLB number of entries for 2MB. + UINT8 InstructionTlbAssociativity2MB; ///< Instruction TLB associativity for 2MB pages + ///< The associativity fields are encoded as follows: + ///< 00h: Reserved. + ///< 01h: Direct mapped. + ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.) + ///< FFh: Fully associative. + UINT8 InstructionTlbSize2MB; ///< Instruction TLB number of entries for 2MB pages. + UINT8 DataTlbAssociativity4K; ///< Data TLB Associativity for 4KB pages + UINT8 DataTlbSize4K; ///< Data TLB number of entries for 4KB pages + UINT8 InstructionTlbAssociativity4K; ///< Instruction TLB Associativity for 4KB pages + UINT8 InstructionTlbSize4K; ///< Instruction TLB number of entries for 4KB pages + UINT8 DataTlbAssociativity1G; ///< Data TLB Associativity for 1GB pages + UINT8 DataTlbSize1G; ///< Data TLB number of entries for 1GB pages + UINT8 InstructionTlbAssociativity1G; ///< Instruction TLB Associativity for 1GB pages + UINT8 InstructionTlbSize1G; ///< Instruction TLB number of entries for 1GB pages + UINT8 Reserved1[4]; ///< Reserved +} CRAT_TLB; + +/// Flags field of the CRAT FPU Affinity structure +typedef struct { + UINT32 Enabled:1; ///< Enabled + UINT32 :31; ///< Reserved +} CRAT_FPU_FLAG; + +/// CRAT FPU Affinity Structure +typedef struct { + UINT8 Type; ///< 4 - CRAT FPU Affinity Structure + UINT8 Length; ///< 64 + UINT16 Reserved; ///< Reserved + CRAT_FPU_FLAG Flags; ///< Flags - FPU Affinity Structure. Indicates whether the region of FPU affinity structure is enabled and defined + UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component. + UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor + UINT32 FPUSize; ///< Product specific + UINT8 Reserved1[16]; ///< Reserved +} CRAT_FPU; + +/// Flags field of the CRAT IO Affinity structure +typedef struct { + UINT32 Enabled:1; ///< Enabled + UINT32 Coherency:1; ///< If set, IO interface supports coherent transactions (natively or through protocol extensions) + UINT32 :30; ///< Reserved +} CRAT_IO_FLAG; + +/// CRAT IO Affinity Structure +typedef struct { + UINT8 Type; ///< 5 - CRAT IO Affinity Structure + UINT8 Length; ///< 64 + UINT16 Reserved; ///< Reserved + CRAT_IO_FLAG Flags; ///< Flags - IO Affinity Structure. Indicates whether the region of IO affinity structure is enabled and defined. + UINT32 ProximityDomainFrom; ///< Integer that represents the proximity domain to which the IO Interface belongs to + UINT32 ProximityDomainTo; ///< Integer that represents the other proximity domain to which the IO Interface belongs to + UINT8 IoType; ///< IO Interface type. Values defined are + ///< 0: Undefined + ///< 1: Hypertransport + ///< 2: PCI Express + ///< 3: Other (e.g. internal) + ///< 4-255: Reserved + UINT8 VersionMajor; ///< Major version of the Bus interface + UINT16 VersionMinor; ///< Minor version of the Bus interface ((optional) + UINT32 MinimumLatency; ///< Cost of time to transfer, described in nanoseconds. + UINT32 MaximumLatency; ///< Cost of time to transfer, described in nanoseconds. + UINT32 MinimumBandwidth; ///< Minimum interface Bandwidth in MB/s + UINT32 MaximumBandwidth; ///< Maximum interface Bandwidth in MB/s + UINT32 RecommendedTransferSize; ///< Recommended transfer size to reach maximum interface bandwidth in Bytes + UINT8 Reserved1[24]; ///< Reserved +} CRAT_IO; + +#define CRAT_MAX_LENGTH 0x800ul ///< Reserve 2K for CRAT +#define LOW_NODE_DEVICEID 24 +/// CRAT entry type +typedef enum { + CRAT_TYPE_HSA_PROC_UNIT = 0, ///< 0 - CRAT HSA Processing Unit Structure + CRAT_TYPE_MEMORY, ///< 1 - CRAT Memory Affinity Structure + CRAT_TYPE_CACHE, ///< 2 - CRAT Cache Affinity Structure + CRAT_TYPE_TLB, ///< 3 - CRAT TLB Affinity Structure + CRAT_TYPE_FPU, ///< 4 - CRAT FPU Affinity Structure + CRAT_TYPE_IO, ///< 5 - CRAT IO Affinity Structure +} CRAT_ENTRY_TYPE; + +/*---------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +AmdCpuLate ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig + ); + +AGESA_STATUS +CreateAcpiWhea ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN OUT VOID **WheaMcePtr, + IN OUT VOID **WheaCmcPtr + ); + +AGESA_STATUS +CreateDmiRecords ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN OUT DMI_INFO **DmiTable + ); + +AGESA_STATUS +GetType4Type7Info ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN DMI_INFO *DmiBufferPtr + ); + +VOID +DmiGetT4ProcFamilyFromBrandId ( + IN OUT UINT8 *T4ProcFamily, + IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable, + IN CPU_TYPE_INFO *CpuInfo, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +GetNameString ( + IN OUT CHAR8 *String, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +BOOLEAN +IsSourceStrContainTargetStr ( + IN OUT CHAR8 *SourceStr, + IN OUT CONST CHAR8 *TargetStr, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +CreateAcpiCrat ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + OUT VOID **CratPtr + ); + +AGESA_STATUS +CreateAcpiCdit ( + IN OUT AMD_CONFIG_PARAMS *StdHeader, + IN PLATFORM_CONFIGURATION *PlatformConfig, + OUT VOID **CditPtr + ); + +VOID +ChecksumAcpiTable ( + IN OUT ACPI_TABLE_HEADER *Table, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +RunLateApTaskOnAllAPs ( + IN AP_EXE_PARAMS *ApParams, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +IdleAllAps ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT32 +InterlockedIncrement ( + IN UINT32 *Value + ); + +UINT32 +InterlockedDecrement ( + IN UINT32 *Value + ); + +#endif // _CPU_LATE_INIT_H_ diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h new file mode 100644 index 0000000000..e51a01feb5 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h @@ -0,0 +1,502 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD CPU Register Table Related Functions + * + * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _CPU_REGISTERS_H_ +#define _CPU_REGISTERS_H_ + +#include "cpuFamRegisters.h" +/* + *-------------------------------------------------------------- + * + * M O D U L E S U S E D + * + *--------------------------------------------------------------- + */ + +/* + *-------------------------------------------------------------- + * + * D E F I N I T I O N S / M A C R O S + * + *--------------------------------------------------------------- + */ + +#undef BIT0 +#undef BIT1 +#undef BIT2 +#undef BIT3 +#undef BIT4 +#undef BIT5 +#undef BIT6 +#undef BIT7 +#undef BIT8 +#undef BIT9 +#undef BIT10 +#undef BIT10 +#undef BIT11 +#undef BIT12 +#undef BIT13 +#undef BIT14 +#undef BIT15 +#undef BIT16 +#undef BIT17 +#undef BIT18 +#undef BIT19 +#undef BIT20 +#undef BIT21 +#undef BIT22 +#undef BIT23 +#undef BIT24 +#undef BIT25 +#undef BIT26 +#undef BIT27 +#undef BIT28 +#undef BIT29 +#undef BIT30 +#undef BIT31 +#undef BIT32 +#undef BIT33 +#undef BIT34 +#undef BIT35 +#undef BIT36 +#undef BIT37 +#undef BIT38 +#undef BIT39 +#undef BIT40 +#undef BIT41 +#undef BIT42 +#undef BIT43 +#undef BIT44 +#undef BIT45 +#undef BIT46 +#undef BIT47 +#undef BIT48 +#undef BIT49 +#undef BIT40 +#undef BIT41 +#undef BIT42 +#undef BIT43 +#undef BIT44 +#undef BIT45 +#undef BIT46 +#undef BIT47 +#undef BIT48 +#undef BIT49 +#undef BIT50 +#undef BIT51 +#undef BIT52 +#undef BIT53 +#undef BIT54 +#undef BIT55 +#undef BIT56 +#undef BIT57 +#undef BIT58 +#undef BIT59 +#undef BIT60 +#undef BIT61 +#undef BIT62 +#undef BIT63 + +#define BIT0 0x0000000000000001ull +#define BIT1 0x0000000000000002ull +#define BIT2 0x0000000000000004ull +#define BIT3 0x0000000000000008ull +#define BIT4 0x0000000000000010ull +#define BIT5 0x0000000000000020ull +#define BIT6 0x0000000000000040ull +#define BIT7 0x0000000000000080ull +#define BIT8 0x0000000000000100ull +#define BIT9 0x0000000000000200ull +#define BIT10 0x0000000000000400ull +#define BIT11 0x0000000000000800ull +#define BIT12 0x0000000000001000ull +#define BIT13 0x0000000000002000ull +#define BIT14 0x0000000000004000ull +#define BIT15 0x0000000000008000ull +#define BIT16 0x0000000000010000ull +#define BIT17 0x0000000000020000ull +#define BIT18 0x0000000000040000ull +#define BIT19 0x0000000000080000ull +#define BIT20 0x0000000000100000ull +#define BIT21 0x0000000000200000ull +#define BIT22 0x0000000000400000ull +#define BIT23 0x0000000000800000ull +#define BIT24 0x0000000001000000ull +#define BIT25 0x0000000002000000ull +#define BIT26 0x0000000004000000ull +#define BIT27 0x0000000008000000ull +#define BIT28 0x0000000010000000ull +#define BIT29 0x0000000020000000ull +#define BIT30 0x0000000040000000ull +#define BIT31 0x0000000080000000ull +#define BIT32 0x0000000100000000ull +#define BIT33 0x0000000200000000ull +#define BIT34 0x0000000400000000ull +#define BIT35 0x0000000800000000ull +#define BIT36 0x0000001000000000ull +#define BIT37 0x0000002000000000ull +#define BIT38 0x0000004000000000ull +#define BIT39 0x0000008000000000ull +#define BIT40 0x0000010000000000ull +#define BIT41 0x0000020000000000ull +#define BIT42 0x0000040000000000ull +#define BIT43 0x0000080000000000ull +#define BIT44 0x0000100000000000ull +#define BIT45 0x0000200000000000ull +#define BIT46 0x0000400000000000ull +#define BIT47 0x0000800000000000ull +#define BIT48 0x0001000000000000ull +#define BIT49 0x0002000000000000ull +#define BIT50 0x0004000000000000ull +#define BIT51 0x0008000000000000ull +#define BIT52 0x0010000000000000ull +#define BIT53 0x0020000000000000ull +#define BIT54 0x0040000000000000ull +#define BIT55 0x0080000000000000ull +#define BIT56 0x0100000000000000ull +#define BIT57 0x0200000000000000ull +#define BIT58 0x0400000000000000ull +#define BIT59 0x0800000000000000ull +#define BIT60 0x1000000000000000ull +#define BIT61 0x2000000000000000ull +#define BIT62 0x4000000000000000ull +#define BIT63 0x8000000000000000ull + +/// CPUID related registers +#define AMD_CPUID_FMF 0x80000001ul // Family Model Features information +#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID +#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006ul +#define CPUID_ASSOCIATIVITY_DISABLED 0x00 +#define CPUID_ASSOCIATIVITY_1_WAY 0x01 +#define CPUID_ASSOCIATIVITY_2_WAY 0x02 +#define CPUID_ASSOCIATIVITY_4_WAY 0x04 +#define CPUID_ASSOCIATIVITY_8_WAY 0x06 +#define CPUID_ASSOCIATIVITY_16_WAY 0x08 +#define CPUID_ASSOCIATIVITY_32_WAY 0x0A +#define CPUID_ASSOCIATIVITY_48_WAY 0x0B +#define CPUID_ASSOCIATIVITY_64_WAY 0x0C +#define CPUID_ASSOCIATIVITY_96_WAY 0x0D +#define CPUID_ASSOCIATIVITY_128_WAY 0x0E +#define CPUID_ASSOCIATIVITY_FULLY 0x0F +#define AMD_CPUID_TLB_L1Cache 0x80000005ul +#define AMD_CPUID_L1L2Tlb1GIdentifiers 0x80000019ul +#define AMD_CPUID_APM 0x80000007ul +#define LOCAL_APIC_ID 24 +#define LOGICAL_PROCESSOR_COUNT 16 +#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008ul // Address Size, Physical Core Count + +/// CPU Logical ID Transfer +typedef struct { + UINT32 RawId; ///< RawID + UINT16 LogicalId; ///< LogicalID +} CPU_LOGICAL_ID_XLAT; + +/// Logical CPU ID Table +typedef struct { + IN UINT32 Elements; ///< Number of Elements + IN CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer +} LOGICAL_ID_TABLE; + +// MSRs +// ------------------------ +#define MCG_CTL_P 0x00000100ul // bit 8 for MCG_CTL_P under MSRR +#define MSR_MCG_CAP 0x00000179ul +#define DBG_CTL_MSR 0x000001D9ul +#define MSR_MC0_CTL 0x00000400ul +#define MSR_MC0_STATUS 0x00000401ul +#define MSR_MC0_MISC 0x00000403ul +#define MSR_MC1_MISC 0x00000407ul +#define MSR_MC2_MISC 0x0000040Bul +#define MSR_MC4_MISC0 0x00000413ul +#define MSR_MC5_MISC 0x00000417ul +#define MSR_MC4_MISC1 0xC0000408ul +#define MSR_MC5_STATUS 0x00000415ul +#define MSR_MC6_STATUS 0x00000419ul + +#define MSR_APIC_BAR 0x0000001Bul +#define MSR_PATCH_LEVEL 0x0000008Bul + +#define CPUID_LONG_MODE_ADDR 0x80000008ul + +#define MSR_EXTENDED_FEATURE_EN 0xC0000080ul +#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408ul +#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409ul +#define MSR_PATCH_LOADER 0xC0010020ul + +/// Patch Loader Register +typedef struct { + UINT64 PatchBase:32; ///< Linear address of patch header address block + UINT64 SBZ:32; ///< Should be zero +} PATCH_LOADER_MSR; + +#define AMD_MTRR_VARIABLE_BASE0 0x200 +#define AMD_MTRR_VARIABLE_BASE6 0x20C +#define AMD_MTRR_FIX64k_00000 0x250 +#define AMD_MTRR_FIX16k_80000 0x258 +#define AMD_MTRR_FIX16k_A0000 0x259 +#define AMD_MTRR_FIX4k_C0000 0x268 +#define AMD_MTRR_FIX4k_C8000 0x269 +#define AMD_MTRR_FIX4k_D0000 0x26A +#define AMD_MTRR_FIX4k_D8000 0x26B +#define AMD_MTRR_FIX4k_E0000 0x26C +#define AMD_MTRR_FIX4k_E8000 0x26D +#define AMD_MTRR_FIX4k_F0000 0x26E +#define AMD_MTRR_FIX4k_F8000 0x26F + +#define AMD_MTRR_FIX64K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull +#define AMD_MTRR_FIX64K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull +#define AMD_MTRR_FIX64K_UC_DRAM 0x1818181818181818ull +#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull +#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull +#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818ull +#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull +#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull +#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818ull + + +#define MSR_SYS_CFG 0xC0010010ul // SYSCFG +#define MSR_TOM 0xC001001Aul // TOP_MEM +#define MSR_TOM2 0xC001001Dul // TOP_MEM2 +#define MSR_MC0_CTL_MASK 0xC0010044ul // MC0 Control Mask +#define MSR_MC1_CTL_MASK 0xC0010045ul // MC1 Control Mask +#define MSR_MC2_CTL_MASK 0xC0010046ul // MC2 Control Mask +#define MSR_MC4_CTL_MASK 0xC0010048ul // MC4 Control Mask + +#define MSR_CPUID_FEATS 0xC0011004ul // CPUID Features +#define MSR_CPUID_EXT_FEATS 0xC0011005ul // CPUID Extended Features +#define MSR_HDT_CFG 0xC001100Aul +#define MSR_HWCR 0xC0010015ul +#define MSR_NB_CFG 0xC001001Ful // NB Config +#define MSR_HTC 0xC001003Eul +#define CPU_WDT_CFG 0xC0010074ul +#define ENABLE_CF8_EXT_CFG 0x00004000ul // [46] +#define INIT_APIC_CPUID_LO 0x00400000ul // [54] +#define MSR_CU_SPMCTL 0xC0010281ul +#define MSR_LS_CFG 0xC0011020ul +#define MSR_IC_CFG 0xC0011021ul // ICache Config - F15 Shared +#define MSR_DC_CFG 0xC0011022ul +#define MSR_ME_CFG 0xC0011029ul +#define MSR_BU_CFG 0xC0011023ul +#define MSR_CU_CFG 0xC0011023ul // F15 Shared +#define MSR_DE_CFG 0xC0011029ul // F15 Shared +#define MSR_BU_CFG2 0xC001102Aul +#define MSR_CU_CFG2 0xC001102Aul // F15 Shared +#define MSR_BU_CFG3 0xC001102Bul +#define MSR_CU_CFG3 0xC001102Bul // F15 Shared +#define MSR_LS_CFG2 0xC001102Dul +#define MSR_CU_PFTCFG 0xC001102Ful +#define MSR_IBS_OP_DATA3 0xC0011037ul +#define MSR_C001_1070 0xC0011070ul // F15 Shared +#define MSR_CU_CBBCFG 0xC00110A1ul // F15 CZ + + +#define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register +#define MSR_CPUID_NAME_STRING1 0xC0010031ul +#define MSR_CPUID_NAME_STRING2 0XC0010032ul +#define MSR_CPUID_NAME_STRING3 0xC0010033ul +#define MSR_CPUID_NAME_STRING4 0xC0010034ul +#define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register +#define MSR_MMIO_Cfg_Base 0xC0010058ul // MMIO Configuration Base Address Register +#define MSR_BIST 0xC0010060ul // BIST Results register +#define MSR_OSVW_ID_Length 0xC0010140ul +#define MSR_OSVW_Status 0xC0010141ul +#define MSR_NB_PERF_CTL0 0xC0010240ul +#define MSR_NB_PERF_CTR0 0xC0010241ul +#define MSR_NB_PERF_CTL1 0xC0010242ul +#define MSR_NB_PERF_CTR1 0xC0010243ul +#define MSR_NB_PERF_CTL2 0xC0010244ul +#define MSR_NB_PERF_CTR2 0xC0010245ul +#define MSR_NB_PERF_CTL3 0xC0010246ul +#define MSR_NB_PERF_CTR3 0xC0010247ul +#define CU_SPMCTL 0xC0010281ul // Streaming Performance Monitor Control +#define MSR_PERF_CONTROL3 0xC0010003ul // Performance control register number 3 +#define MSR_PERF_COUNTER3 0xC0010007ul // Performance counter register number 3 +#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFFull // Mask of the Performance control Reserve bits +#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2ul // Configure the controller to capture the + // CAR Corruption +// FUNC_0 registers +// ---------------- +#define LINK_INIT_CTRL 0x6C +#define LINK_INIT_CTRL_REQ_DIS 0x02 // [1] = ReqDis +#define LINK_INIT_COLD_RST_DET BIT4 +#define LINK_INIT_BIOS_RST_DET_0 BIT5 +#define LINK_INIT_BIOS_RST_DET_1 BIT9 +#define LINK_INIT_BIOS_RST_DET_2 BIT10 +#define LINK_INIT_BIOS_RST_DET BIT9 | BIT10 +#define EXTENDED_NODE_ID 0x160 + +#define CORE_CTRL 0x1DC +#define CORE_CTRL_CORE1_EN 0x00000002ul +#define CORE_CTRL_CORE2_EN 0x00000004ul +#define CORE_CTRL_CORE3_EN 0x00000008ul +#define CORE_CTRL_CORE4_EN 0x00000010ul +#define CORE_CTRL_CORE5_EN 0x00000020ul +#define CORE_CTRL_CORE6_EN 0x00000040ul +#define CORE_CTRL_CORE7_EN 0x00000080ul +#define CORE_CTRL_CORE8_EN 0x00000100ul +#define CORE_CTRL_CORE9_EN 0x00000200ul + +// FUNC_3 registers +// ---------------- +#define HARDWARE_THERMAL_CTRL_REG 0x64 +#define SOFTWARE_THERMAL_CTRL_REG 0x68 + +#define ACPI_PSC_0_REG 0x80 // ACPI Power State Control Registers +#define ACPI_PSC_4_REG 0x84 + +#define NB_CFG_HIGH_REG 0x8C +#define POWER_CTRL_MISCELLANEOUS_REG 0xA0 +#define CLOCK_POWER_TIMING_CTRL2_REG 0xDC +#define NORTH_BRIDGE_CAPABILITIES_REG 0xE8 +#define MULTI_NODE_CPU 29 +#define CPUID_FMR 0xFC // Family / Model registers +#define DOWNCORE_CTRL 0x190 // Downcore Control Register + +#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148 +#define REG_HT4_PHY_OFFSET_BASE_4X180 0x180 +#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184 + +// FUNC_4 registers +// ---------------- +/* Native Die CPUID Register F4x160 */ +#define NATIVE_DIE_CPUID_REG 0x160 +#define NATIVE_DIE_CPUID_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, NATIVE_DIE_CPUID_REG)) + +/// Native Die CPUID PCI Register +typedef struct { + UINT32 Stepping:4; ///< Stepping + UINT32 BaseModel:4; ///< Base Model + UINT32 BaseFamily:4; ///< Base Family + UINT32 :4; ///< Reserved + UINT32 ExtModel:4; ///< Extended Model + UINT32 ExtFamily:8; ///< Extended Family + UINT32 :4; ///< Reserved +} NATIVE_DIE_CPUID_REGISTER; + +// FUNC_5 registers +// ---------------- +#define COMPUTE_UNIT_STATUS 0x80 +#define NORTH_BRIDGE_CAPABILITIES_2_REG 0x84 + + +// Misc. defines. +#define PCI_DEV_BASE 24 + +#define CPUID_STEPPING_MASK 0x0000000Ful +#define CPUID_BASE_MODEL_MASK 0x000000F0ul +#define CPUID_BASE_FAMILY_MASK 0x00000F00ul +#define CPUID_EXT_MODEL_MASK 0x000F0000ul +#define CPUID_EXT_FAMILY_MASK 0x0FF00000ul + +#define CZ_SOCKET_FP4 0 +#define SOCKET_IGNORE 0xF + +#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull +#define APIC_EXT_BRDCST_MASK 0x000E0000ul +#define APIC_ENABLE_BIT 0x00000800ul +#ifndef LOCAL_APIC_ADDR +#define LOCAL_APIC_ADDR 0xFEE00000ul +#endif +#define INT_CMD_REG_LO 0x300 +#define INT_CMD_REG_HI 0x310 +#define REMOTE_MSG_REG 0x380 +#define REMOTE_READ_REG 0xC0 +#define APIC_ID_REG 0x20 +#define APIC20_ApicId 24 +#define CMD_REG_TO_READ_DATA 0x338 + +#define MAX_CORE_ID_SIZE 8 +#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1) + +/*------------------------- + * Default definitions + *------------------------- + */ +#define DOWNCORE_MASK_SINGLE 0xFFFFFFFEul +#define DOWNCORE_MASK_DUAL 0xFFFFFFFCul +#define DOWNCORE_MASK_TRI 0xFFFFFFF8ul +#define DOWNCORE_MASK_FOUR 0xFFFFFFF0ul +#define DOWNCORE_MASK_FIVE 0xFFFFFFE0ul +#define DOWNCORE_MASK_SIX 0xFFFFFFC0ul +#define DOWNCORE_MASK_SEVEN 0xFFFFFF80ul +#define DOWNCORE_MASK_EIGHT 0xFFFFFF00ul +#define DOWNCORE_MASK_TEN 0xFFFFFC00ul +#define DOWNCORE_MASK_TWELVE 0xFFFFF000ul +#define DOWNCORE_MASK_FOURTEEN 0xFFFFC000ul +#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFAul +#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEAul +#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAAul +#define DOWNCORE_MASK_FIVE_COMPUTE_UNIT 0xFFFFFEAAul +#define DOWNCORE_MASK_SIX_COMPUTE_UNIT 0xFFFFFAAAul +#define DOWNCORE_MASK_SEVEN_COMPUTE_UNIT 0xFFFFEAAAul +#define DOWNCORE_MASK_EIGHT_COMPUTE_UNIT 0xFFFFAAAAul + +#define DELIVERY_STATUS BIT13 +#define REMOTE_READ_STAT_MASK 0x00030000ul +#define REMOTE_DELIVERY_PENDING 0x00010000ul +#define REMOTE_DELIVERY_DONE 0x00020000ul + +/* + * -------------------------------------------------------------------------------------- + * + * D E F I N E S / T Y P E D E F S / S T R U C T U R E S + * + * -------------------------------------------------------------------------------------- + */ + +/// CpuEarly param type +typedef struct { + IN UINT8 MemInitPState; ///< Pstate value during memory initial + IN PLATFORM_CONFIGURATION PlatformConfig; ///< Runtime configurable user options +} AMD_CPU_EARLY_PARAMS; + +/// CPUID +typedef enum { + REG_EAX, ///< EAX + REG_EBX, ///< EBX + REG_ECX, ///< ECX + REG_EDX ///< EDX +} CPUID_REG; + +#endif // _CPU_REGISTERS_H_ + diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/heapManager.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/heapManager.h new file mode 100644 index 0000000000..915144f8f9 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/heapManager.h @@ -0,0 +1,241 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD Heap Manager and Heap Allocation APIs, and related functions. + * + * Contains code that initialize, maintain, and allocate the heap space. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: CPU + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _HEAP_MANAGER_H_ +#define _HEAP_MANAGER_H_ + +/*--------------------------------------------------------------------------------------- + * M I X E D (Definitions And Macros / Typedefs, Structures, Enums) + *--------------------------------------------------------------------------------------- + */ + + +/*--------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *--------------------------------------------------------------------------------------- + */ +#define AMD_MTRR_VARIABLE_BASE0 0x200 +#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A +#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1) + +#define AMD_HEAP_START_ADDRESS 0x400000ul +#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFFul +#define AMD_HEAP_SIZE_PER_CORE 0x010000ul +#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFFul +#define AMD_HEAP_MTRR_MASK ((0xFFFFFFFFFFFFF800ull & (((UINT64)AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1)) | 0x800) +#define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4) + +#define AMD_TEMP_TOM 0x20000000ul // Set TOM to 512 MB (temporary value) +#define AMD_VAR_MTRR_ENABLE_BIT 0x100000ul // bit 20 + +#define AMD_HEAP_RAM_ADDRESS 0xB0000ul + +#define HEAP_SIGNATURE_VALID 0x50414548ul // Signature: 'HEAP' +#define HEAP_SIGNATURE_INVALID 0x00000000ul // Signature cleared + +///Heap Manager Life cycle +#define HEAP_DO_NOT_EXIST_YET 1 +#define HEAP_LOCAL_CACHE 2 +#define HEAP_TEMP_MEM 3 +#define HEAP_SYSTEM_MEM 4 +#define HEAP_DO_NOT_EXIST_ANYMORE 5 +#define HEAP_S3_RESUME 6 +#define HEAP_RUNTIME_SYSTEM_MEM 7 + +///Heap callout +#define HEAP_CALLOUT_BOOTTIME 0 +#define HEAP_CALLOUT_RUNTIME 1 + +/*--------------------------------------------------------------------------------------- + * T Y P E D E F S, S T R U C T U R E S, E N U M S + *--------------------------------------------------------------------------------------- + */ +/// Allocate Heap Parameters +typedef struct _ALLOCATE_HEAP_PARAMS { + UINT32 RequestedBufferSize; ///< Size of buffer. + UINT32 BufferHandle; ///< An unique ID of buffer. + UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate. + UINT8 *BufferPtr; ///< Pointer to buffer. +} ALLOCATE_HEAP_PARAMS; + +/// Locate Heap Parameters +typedef struct _LOCATE_HEAP_PTR { + UINT32 BufferHandle; ///< An unique ID of buffer. + UINT32 BufferSize; ///< Data buffer size. + UINT8 *BufferPtr; ///< Pointer to buffer. +} LOCATE_HEAP_PTR; + +/// Heap Node Header +typedef struct _BUFFER_NODE { + UINT32 BufferHandle; ///< An unique ID of buffer. + UINT32 BufferSize; ///< Size of buffer. + UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate. + UINT8 PadSize; ///< Size of pad. + UINT32 OffsetOfNextNode; ///< Offset of next node (relative to the base). +} BUFFER_NODE; + +/// Heap Manager +typedef struct _HEAP_MANAGER { + UINT32 Signature; ///< a signature to indicate if the heap is valid. + UINT32 UsedSize; ///< Used size of heap. + UINT32 FirstActiveBufferOffset; ///< Offset of the first active buffer. + UINT32 FirstFreeSpaceOffset; ///< Offset of the first free space. +} HEAP_MANAGER; + +/// AGESA Buffer Handles (These are reserved) +typedef enum { + AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine. + AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine. + AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine. + AMD_INIT_ENV_HANDLE, ///< Assign 0x000A003 buffer handle to AmdInitEnv routine. + AMD_INIT_MID_HANDLE, ///< Assign 0x000A004 buffer handle to AmdInitMid routine. + AMD_INIT_LATE_HANDLE, ///< Assign 0x000A005 buffer handle to AmdInitLate routine. + AMD_INIT_RESUME_HANDLE, ///< Assign 0x000A006 buffer handle to AmdInitResume routine. + AMD_LATE_RUN_AP_TASK_HANDLE, ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine. + AMD_INIT_RTB_HANDLE, ///< Assign 0x000A008 buffer handle to AmdInitRtb routine. + AMD_S3_LATE_RESTORE_HANDLE, ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine. + AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, ///< Assign 0x000A00A buffer handle to be used for S3 save table + AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, ///< Assign 0x000A00B buffer handle to be used for S3 save table + AMD_CPU_AP_TASKING_HANDLE, ///< Assign 0x000A00C buffer handle to AP tasking input parameters. + AMD_REC_MEM_SOCKET_HANDLE, ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode. + AMD_MEM_AUTO_HANDLE, ///< Assign 0x000A00E buffer handle to AmdMemAuto routine. + AMD_MEM_SPD_HANDLE, ///< Assign 0x000A00F buffer handle to AmdMemSpd routine. + AMD_MEM_DATA_HANDLE, ///< Assign 0x000A010 buffer handle to MemData + AMD_MEM_TRAIN_BUFFER_HANDLE, ///< Assign 0x000A011 buffer handle to allocate buffer for training + AMD_MEM_S3_DATA_HANDLE, ///< Assign 0x000A012 buffer handle to special case register for S3 + AMD_MEM_S3_NB_HANDLE, ///< Assign 0x000A013 buffer handle to NB block for S3 + AMD_MEM_S3_MR0_DATA_HANDLE, ///< Assign 0x000A014 buffer handle to MR0 data block for S3 + AMD_UMA_INFO_HANDLE, ///< Assign 0x000A015 buffer handle to be used for Uma information + AMD_DMI_MEM_DEV_INFO_HANDLE, ///< Assign 0x000A016 buffer handle to DMI Type16 17 19 20 information + EVENT_LOG_BUFFER_HANDLE, ///< Assign 0x000A017 buffer handle to Event Log + IDS_CONTROL_HANDLE, ///< Assign 0x000A018 buffer handle to AmdIds routine. + IDS_HDT_OUT_BUFFER_HANDLE, ///< Assign 0x000A019 buffer handle to be used for HDTOUT support. + IDS_CHECK_POINT_PERF_HANDLE, ///< Assign 0x000A01A buffer handle to Performance analysis + AMD_PCIE_COMPLEX_DATA_HANDLE, ///< Assign 0x000A01B buffer handle to be used for PCIe support + AMD_MEM_SYS_DATA_HANDLE, ///< Assign 0x000A01C buffer handle to be used for memory data structure + AMD_GNB_SMU_CONFIG_HANDLE, ///< Assign 0x000A01D buffer handle to be used for GNB SMU configuration + AMD_PP_FUSE_TABLE_HANDLE, ///< Assign 0x000A01E buffer handle to be used for TT fuse table + AMD_GFX_PLATFORM_CONFIG_HANDLE, ///< Assign 0x000A01F buffer handle to be used for Gfx platform configuration + AMD_GNB_TEMP_DATA_HANDLE, ///< Assign 0x000A020 buffer handle for GNB general purpose data block + AMD_MEM_2D_RDQS_HANDLE, ///< Assign 0x000A021 buffer handle for 2D training + AMD_MEM_2D_RD_WR_HANDLE, ///< Assign 0x000A022 buffer handle for 2D Read/Write training + AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE, ///< Assign 0x000A023 buffer handle to be used for GNB IOMMU scratch memory + AMD_MEM_S3_SAVE_HANDLE, ///< Assign 0x000A024 buffer handle for memory data saved right after memory init + AMD_MEM_2D_RDQS_RIM_HANDLE, ///< Assign 0x000A025 buffer handle for 2D training Eye RIM Search + AMD_MEM_2D_RD_WR_RIM_HANDLE, ///< Assign 0x000A026 buffer handle for 2D Read/Write training Eye RIM Search + AMD_CPU_NB_PSTATE_FIXUP_HANDLE, ///< Assign 0x000A027 buffer handle for an NB P-state workaround + AMD_MEM_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000A028 buffer handle for CRAT Memory affinity component structure + AMD_SKIP_MEM_S3_SAVE, ///< Assign 0x000A029 buffer handle for the flag to skip memory S3 save + AMD_IS_FEATURE_ENABLED, ///< Assign 0x000A02A buffer handle for keeping the result of IsFeatureEnabled + AMD_MEM_DATAEYE_WORK_AREA_HANDLE, ///< Assign 0x000A02B buffer handle for Composite Data Eye Compression Work Area + AMD_GNB_SAMU_PATCH_HANDLE, ///< Assign 0x000A02C buffer handle for Samu patch buffer + AMD_GNB_SAMU_BOOT_CONTROL_HANDLE, ///< Assign 0x000A02D buffer handle for Samu boot control buffer + AMD_GNB_ACP_ENGINE_HANDLE, ///< Assign 0x000A02E buffer handle for GNB ACP engine buffer + AMD_MEM_PMU_SRAM_MSG_BLOCK_HANDLE, ///< Assign 0x000A02F buffer handle for PMU SRAM Message Block buffer + AMD_MEM_DRAM_CAD_BUS_CONFIG_HANDLE, ///< Assign 0x000A030 buffer handle for DRAM CAD Bus Configuration + AMD_GNB_SMU_TABLE_HANDLE, ///< Assign 0x000A031 buffer handle for GNB SMU table buffer + AMD_GNB_CRAT_HSA_TABLE_HANDLE, ///< Assign 0x000A032 buffer handle for GNB CRAT HSA unit table + AMD_GNB_BUILD_OPTIONS_HANDLE, ///< Assign 0x000A033 buffer handle for GNB build options + AMD_S3_FINAL_RESTORE_HANDLE, ///< Assign 0x000A034 buffer handle to AmdS3FinalRestore routine. + AMD_GNB_PCIE_AER_CONFIG_HANDLE, ///< Assign 0x000A035 buffer handle for GNB PCIE AER configuration. + AMD_BTC_SCRATCH_HANDLE, ///< Assign 0x000A036 buffer handle for boot time calibration workloads + AMD_BTC_XMM_SAVE_HANDLE, ///< Assign 0x000A037 buffer handle for boot time calibration xmm register save + AMD_S3_SAVE_HANDLE, ///< Assign 0x000A038 buffer handle to memory context data + AMD_MEM_DDR_MAX_RATE_HANDLE, ///< Assign 0x000A039 buffer handle to memory DDR max rate + AMD_GNB_TDP_HANDLE, ///< Assign 0x000A03A buffer handle to GNB TDP + AMD_MEM_MISC_HANDLES_START = 0x1000000, ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle + AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF, ///< miscellaneous memory init tasks' buffers. + AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000, ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE. + SOCKET_DIE_MAP_HANDLE = 0x534F4B54, ///< 'sokt' + NODE_ID_MAP_HANDLE = 0x4E4F4445, ///< 'node' + HOP_COUNT_TABLE_HANDLE = 0x484F5053, ///< 'hops' + AMD_FCH_RESET_DATA_BLOCK_HANDLE = 0x46434852, ///< 'FCHR' Buffer handle for FCH private data block at InitReset + AMD_FCH_DATA_BLOCK_HANDLE = 0x46434845, ///< 'FCHE' Buffer handle for FCH private data block at InitEnv + IDS_TRAP_TABLE_HANDLE = 0x49524547, ///< 'IREG' Handle for IDS register table + IDS_SAVE_IDTR_HANDLE = 0x49445452, ///< 'IDTR' + IDS_BSC_IDT_HANDLE = 0x42534349, ///< 'BSCI' BSC Idt table + IDS_NV_TO_CMOS_HANDLE = 0x534D4349, ///< 'ICMS' Handle for IDS CMOS save + IDS_GRA_HANDLE = 0x41524749, ///< 'IGRA' Handle for IDS GRA save + IDS_EXTEND_HANDLE = 0x54584549, ///< 'IEXT' Handle for IDS extend module + IDS_TEMP_DATA_HANDLE = 0x504D5459, ///< 'ITMP' Handle for IDS temp data +} AGESA_BUFFER_HANDLE; + + +/*--------------------------------------------------------------------------------------- + * F U N C T I O N P R O T O T Y P E + *--------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +HeapManagerInit ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +HeapAllocateBuffer ( + IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams, + IN OUT AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +HeapDeallocateBuffer ( + IN UINT32 BufferHandle, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +HeapLocateBuffer ( + IN OUT LOCATE_HEAP_PTR *LocateHeap, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +UINT64 +HeapGetBaseAddress ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +AGESA_STATUS +EventLogInitialization ( + IN AMD_CONFIG_PARAMS *StdHeader + ); +#endif // _HEAP_MANAGER_H_ diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Common/AmdFch.h b/src/vendorcode/amd/pi/00660F01/Proc/Common/AmdFch.h new file mode 100644 index 0000000000..f75f881601 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Common/AmdFch.h @@ -0,0 +1,63 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * AMD FCH Component + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _AMD_FCH_H_ +#define _AMD_FCH_H_ + +typedef AGESA_STATUS FCH_INIT (IN VOID *DataPtr); +typedef VOID FCH_TASK_ENTRY (IN VOID *FchCfg); + + +/// FCH API build options +typedef struct { + FCH_INIT *InitReset; ///< InitReset + FCH_INIT *InitResetConstructor; ///< InitResetConstructor + FCH_INIT *InitEnv; ///< InitEnv + FCH_INIT *InitEnvConstructor; ///< InitEnvConstructor + FCH_INIT *InitMid; ///< InitMid + FCH_INIT *InitMidConstructor; ///< InitMidConstructor + FCH_INIT *InitLate; ///< InitLate + FCH_INIT *InitLateConstructor; ///< InitLateConstructor +} BLDOPT_FCH_FUNCTION; + +#endif diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/AcpiLib.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/AcpiLib.h new file mode 100644 index 0000000000..6f87842a30 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/AcpiLib.h @@ -0,0 +1,90 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH ACPI lib + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#ifndef _FCH_ACPILIB_H_ +#define _FCH_ACPILIB_H_ +/// +/// RSDP - ACPI 2.0 table RSDP +/// +typedef struct _RSDP_HEADER { + UINT64 Signature; ///< RSDP signature "RSD PTR" + UINT8 CheckSum; ///< checksum of the first 20 bytes + UINT8 OEMID[6]; ///< OEM ID + UINT8 Revision; ///< 0 for APCI 1.0, 2 for ACPI 2.0 + UINT32 RsdtAddress; ///< physical address of RSDT + UINT32 Length; ///< total length of RSDP (including extended part) + UINT64 XsdtAddress; ///< physical address of XSDT + UINT8 ExtendedCheckSum; ///< chechsum of whole table + UINT8 Reserved[3]; ///< Reserved +} RSDP_HEADER; + +/// +/// DESCRIPTION_HEADER - ACPI common table header +/// +typedef struct _DESCRIPTION_HEADER { + UINT32 Signature; ///< ACPI signature (4 ASCII characters) + UINT32 Length; ///< Length of table, in bytes, including header + UINT8 Revision; ///< ACPI Specification minor version # + UINT8 CheckSum; ///< To make sum of entire table == 0 + UINT8 OemId[6]; ///< OEM identification + UINT8 OemTableId[8]; ///< OEM table identification + UINT32 OemRevision; ///< OEM revision number + UINT32 CreatorId; ///< ASL compiler vendor ID + UINT32 CreatorRevision; ///< ASL compiler revision number +} DESCRIPTION_HEADER; + +/// +/// _AcpiRegWrite - ACPI MMIO register R/W structure +/// +typedef struct _ACPI_REG_WRITE { + UINT8 MmioBase; /// MmioBase: Index of Fch block (For instance GPIO_BASE:0x01 SMI_BASE:0x02) + UINT8 MmioReg; /// MmioReg : Register index + UINT8 DataAndMask; /// DataANDMask : AND Register Data + UINT8 DataOrMask; /// DataOrMask : Or Register Data +} ACPI_REG_WRITE; + +VOID* AcpiLocateTable (IN UINT32 Signature); +VOID AcpiSetTableCheckSum (IN VOID *TablePtr); +UINT8 AcpiGetTableCheckSum (IN VOID *TablePtr); +UINT8 GetByteSum (IN VOID *DataPtr, IN UINT32 Length); + +#endif diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchBiosRamUsage.h new file mode 100644 index 0000000000..a694d11543 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchBiosRamUsage.h @@ -0,0 +1,66 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH BIOS Ram usage + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#ifndef _FCH_BIOS_RAM_USAGE_H_ +#define _FCH_BIOS_RAM_USAGE_H_ + +#define RESTORE_MEMORY_CONTROLLER_START 0 +#define XHCI_REGISTER_BAR00 0xD0 +#define XHCI_REGISTER_BAR01 0xD1 +#define XHCI_REGISTER_BAR02 0xD2 +#define XHCI_REGISTER_BAR03 0xD3 +#define XHCI_REGISTER_04H 0xD4 +#define XHCI_REGISTER_0CH 0xD5 +#define XHCI_REGISTER_3CH 0xD6 +#define XHCI1_REGISTER_BAR00 0xE0 +#define XHCI1_REGISTER_BAR01 0xE1 +#define XHCI1_REGISTER_BAR02 0xE2 +#define XHCI1_REGISTER_BAR03 0xE3 +#define XHCI1_REGISTER_04H 0xE4 +#define XHCI1_REGISTER_0CH 0xE5 +#define XHCI1_REGISTER_3CH 0xE6 +#define RTC_WORKAROUND_DATA_START 0xF0 +#define BOOT_TIME_FLAG_SEC 0xF8 +#define BOOT_TIME_FLAG_INT19 0xFC + +#endif + diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h new file mode 100644 index 0000000000..fb2bae22a0 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h @@ -0,0 +1,1359 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH Function Support Definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 311507 $ @e \$Date: 2015-01-22 06:57:51 +0800 (Thu, 22 Jan 2015) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#ifndef _FCH_COMMON_CFG_H_ +#define _FCH_COMMON_CFG_H_ + +#pragma pack (push, 1) + +//----------------------------------------------------------------------------- +// FCH DEFINITIONS AND MACROS +//----------------------------------------------------------------------------- + +// +// FCH Component Data Structure Definitions +// + +/// PCI_ADDRESS - PCI access structure +#define PCI_ADDRESS(bus, dev, func, reg) \ + (UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) ) + +#define CPUID_FMF 0x80000001ul // Family Model Features information +/// +/// - Byte Register R/W structure +/// +typedef struct _REG8_MASK { + UINT8 RegIndex; /// RegIndex - Reserved + UINT8 AndMask; /// AndMask - Reserved + UINT8 OrMask; /// OrMask - Reserved +} REG8_MASK; + + +/// +/// PCIE Reset Block +/// +typedef enum { + NbBlock, ///< Reset for NB PCIE + FchBlock ///< Reset for FCH GPP +} RESET_BLOCK; + +/// +/// PCIE Reset Operation +/// +typedef enum { + DeassertReset, ///< DeassertRese - Deassert reset + AssertReset ///< AssertReset - Assert reset +} RESET_OP; + + +/// +/// Fch Run Time Parameters +/// +typedef struct { + UINT32 PcieMmioBase; ///< PcieMmioBase + UINT32 FchDeviceEnableMap; ///< FchDeviceEnableMap + UINT32 FchDeviceD3ColdMap; ///< FchDeviceD3ColdMap + UINT16 XHCI_PMx04_XhciFwRomAddr_Rom; ///< XHCI_PMx04_XhciFwRomAddr_Rom + UINT32 XHCI_PMx08_xHCI_Firmware_Addr_1_Rom; ///< XHCI_PMx08_xHCI_Firmware_Addr_1_Ram + UINT16 XHCI_PMx04_XhciFwRomAddr_Ram; ///< XHCI_PMx04_XhciFwRomAddr_Rom + UINT32 XHCI_PMx08_xHCI_Firmware_Addr_1_Ram; ///< XHCI_PMx08_xHCI_Firmware_Addr_1_Ram + UINT8 SataDevSlpPort0S5Pin; ///< SataDevSlpPort0S5Pin - Reserved + UINT8 SataDevSlpPort1S5Pin; ///< SataDevSlpPort1S5Pin - Reserved + UINT16 Dummy16; ///< Dummy16 - Reserved + UINT32 SdMmioBase; ///< Sd Mmio Base - Reserved + UINT32 EhciMmioBase; ///< Ehci Mmio Base - Reserved + UINT32 XhciMmioBase; ///< Xhci Mmio Base - Reserved + UINT32 SataMmioBase; ///< Sata Mmio Base - Reserved +} FCH_RUNTIME; + +/// +/// SD structure +/// +typedef struct { + SD_MODE SdConfig; ///< SD Mode configuration + /// @li <b>00</b> - Disabled + /// @li <b>00</b> - AMDA + /// @li <b>01</b> - DMA + /// @li <b>10</b> - PIO + /// + UINT8 SdSpeed; ///< SD Speed + /// @li <b>0</b> - Low speed + /// @li <b>1</b> - High speed + /// + UINT8 SdBitWidth; ///< SD Bit Width + /// @li <b>0</b> - 32BIT clear 23 + /// @li <b>1</b> - 64BIT, set 23,default + /// + UINT32 SdSsid; ///< SD Subsystem ID + SD_CLOCK_CONTROL SdClockControl; ///< SD Clock Control + BOOLEAN SdClockMultiplier; ///< SD Clock Multiplier enable/disable + UINT8 SdReTuningMode; ///< SD Re-tuning modes select + /// @li <b>0</b> - mode 1 + /// @li <b>1</b> - mode 2 + /// @li <b>2</b> - mode 3 + UINT8 SdHostControllerVersion; ///< SD controller Version + /// @li <b>1</b> - SD 2.0 + /// @li <b>2</b> - SD 3.0 + UINT8 SdrCapabilities; ///< SDR Capability mode select + /// @li <b>00</b> - SDR25/15 + /// @li <b>01</b> - SDR50 + /// @li <b>11</b> - SDR104 + UINT8 SdSlotType; ///< SDR Slot Type select + /// @li <b>00</b> - Removable Card Slot + /// @li <b>01</b> - Embedded Slot for One Device + /// @li <b>10</b> - Shared Bus Slot + BOOLEAN SdForce18; ///< SD Force18 + UINT8 SdDbgConfig; ///< SD Mode configuration + /// @li <b>00</b> - Disabled + /// @li <b>00</b> - AMDA + /// @li <b>01</b> - DMA + /// @li <b>10</b> - PIO + /// +} FCH_SD; + +/// +/// CODEC_ENTRY - Fch HD Audio OEM Codec structure +/// +typedef struct _CODEC_ENTRY { + UINT8 Nid; /// Nid - Reserved + UINT32 Byte40; /// Byte40 - Reserved +} CODEC_ENTRY; + +/// +/// CODEC_TBL_LIST - Fch HD Audio Codec table list +/// +typedef struct _CODEC_TBL_LIST { + UINT32 CodecId; /// CodecID - Codec ID + CODEC_ENTRY* CodecTablePtr; /// CodecTablePtr - Codec table pointer +} CODEC_TBL_LIST; + +/// +/// AZALIA_PIN - HID Azalia or GPIO define structure. +/// +typedef struct _AZALIA_PIN { + UINT8 AzaliaSdin0; ///< AzaliaSdin0 + /// @par + /// @li <b>00</b> - GPIO PIN + /// @li <b>10</b> - As a Azalia SDIN pin + + UINT8 AzaliaSdin1; ///< AzaliaSdin1 + /// @par + /// SDIN1 is define at BIT2 & BIT3 + /// @li <b>00</b> - GPIO PIN + /// @li <b>10</b> - As a Azalia SDIN pin + + UINT8 AzaliaSdin2; ///< AzaliaSdin2 + /// @par + /// SDIN2 is define at BIT4 & BIT5 + /// @li <b>00</b> - GPIO PIN + /// @li <b>10</b> - As a Azalia SDIN pin + + UINT8 AzaliaSdin3; ///< AzaliaSdin3 + /// @par + /// SDIN3 is define at BIT6 & BIT7 + /// @li <b>00</b> - GPIO PIN + /// @li <b>10</b> - As a Azalia SDIN pin +} AZALIA_PIN; + +/// +/// Azalia structure +/// +typedef struct { + HDA_CONFIG AzaliaEnable; ///< AzaliaEnable - Azalia function configuration + BOOLEAN AzaliaMsiEnable; ///< AzaliaMsiEnable - Azalia MSI capability + UINT32 AzaliaSsid; ///< AzaliaSsid - Azalia Subsystem ID + UINT8 AzaliaPinCfg; ///< AzaliaPinCfg - Azalia Controller SDIN pin Configuration + /// @par + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + + UINT8 AzaliaFrontPanel; ///< AzaliaFrontPanel - Azalia Controller Front Panel Configuration + /// @par + /// Support Front Panel configuration + /// @li <b>0</b> - Auto + /// @li <b>1</b> - disable + /// @li <b>2</b> - enable + + UINT8 FrontPanelDetected; ///< FrontPanelDetected - Force Azalia Controller Front Panel Configuration + /// @par + /// Force Front Panel configuration + /// @li <b>0</b> - Not Detected + /// @li <b>1</b> - Detected + + UINT8 AzaliaSnoop; ///< AzaliaSnoop - Azalia Controller Snoop feature Configuration + /// @par + /// Azalia Controller Snoop feature Configuration + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + + UINT8 AzaliaDummy; /// AzaliaDummy - Reserved */ + + AZALIA_PIN AzaliaConfig; /// AzaliaConfig - Azaliz Pin Configuration + +/// +/// AZOEMTBL - Azalia Controller OEM Codec Table Pointer +/// + CODEC_TBL_LIST *AzaliaOemCodecTablePtr; /// AzaliaOemCodecTablePtr - Oem Azalia Codec Table Pointer + +/// +/// AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer +/// + VOID *AzaliaOemFpCodecTablePtr; /// AzaliaOemFpCodecTablePtr - Oem Front Panel Codec Table Pointer +} FCH_AZALIA; + +/// +/// _SPI_DEVICE_PROFILE Spi Device Profile structure +/// +typedef struct _SPI_DEVICE_PROFILE { + UINT32 JEDEC_ID; /// JEDEC ID + UINT32 RomSize; /// ROM Size + UINT32 SectorSize; /// Sector Size + UINT16 MaxNormalSpeed; /// Max Normal Speed + UINT16 MaxFastSpeed; /// Max Fast Speed + UINT16 MaxDualSpeed; /// Max Dual Speed + UINT16 MaxQuadSpeed; /// Max Quad Speed + UINT8 QeReadRegister; /// QE Read Register + UINT8 QeWriteRegister; /// QE Write Register + UINT8 QeOperateSize; /// QE Operate Size 1byte/2bytes + UINT16 QeLocation; // QE Location in the register +} SPI_DEVICE_PROFILE; + +/// +/// _SPI_CONTROLLER_PROFILE Spi Device Profile structure +/// +typedef struct _SPI_CONTROLLER_PROFILE { +// UINT32 SPI_CONTROLLER_ID; /// SPI Controller ID + UINT16 FifoSize; /// FIFO Size + UINT16 MaxNormalSpeed; /// Max Normal Speed + UINT16 MaxFastSpeed; /// Max Fast Speed + UINT16 MaxDualSpeed; /// Max Dual Speed + UINT16 MaxQuadSpeed; /// Max Quad Speed +} SPI_CONTROLLER_PROFILE; + +/// +/// SPI structure +/// +typedef struct { + BOOLEAN LpcMsiEnable; ///< LPC MSI capability + UINT32 LpcSsid; ///< LPC Subsystem ID + UINT32 RomBaseAddress; ///< SpiRomBaseAddress + /// @par + /// SPI ROM BASE Address + /// + UINT8 SpiSpeed; ///< SpiSpeed - Spi Frequency + /// @par + /// SPI Speed [1.0] - the clock speed for non-fast read command + /// @li <b>00</b> - 66Mhz + /// @li <b>01</b> - 33Mhz + /// @li <b>10</b> - 22Mhz + /// @li <b>11</b> - 16.5Mhz + /// + UINT8 SpiFastSpeed; ///< FastSpeed - Spi Fast Speed feature + /// SPIFastSpeed [1.0] - the clock speed for Fast Speed Feature + /// @li <b>00</b> - 66Mhz + /// @li <b>01</b> - 33Mhz + /// @li <b>10</b> - 22Mhz + /// @li <b>11</b> - 16.5Mhz + /// + UINT8 WriteSpeed; ///< WriteSpeed - Spi Write Speed + /// @par + /// WriteSpeed [1.0] - the clock speed for Spi write command + /// @li <b>00</b> - 66Mhz + /// @li <b>01</b> - 33Mhz + /// @li <b>10</b> - 22Mhz + /// @li <b>11</b> - 16.5Mhz + /// + UINT8 SpiMode; ///< SpiMode - Spi Mode Setting + /// @par + /// @li <b>101</b> - Qual-io 1-4-4 + /// @li <b>100</b> - Dual-io 1-2-2 + /// @li <b>011</b> - Qual-io 1-1-4 + /// @li <b>010</b> - Dual-io 1-1-2 + /// @li <b>111</b> - FastRead + /// @li <b>110</b> - Normal + /// + UINT8 AutoMode; ///< AutoMode - Spi Auto Mode + /// @par + /// SPI Auto Mode + /// @li <b>0</b> - Disabled + /// @li <b>1</b> - Enabled + /// + UINT8 SpiBurstWrite; ///< SpiBurstWrite - Spi Burst Write Mode + /// @par + /// SPI Burst Write + /// @li <b>0</b> - Disabled + /// @li <b>1</b> - Enabled + BOOLEAN LpcClk0; ///< Lclk0En - LPCCLK0 + /// @par + /// LPC Clock 0 mode + /// @li <b>0</b> - forced to stop + /// @li <b>1</b> - functioning with CLKRUN protocol + BOOLEAN LpcClk1; ///< Lclk1En - LPCCLK1 + /// @par + /// LPC Clock 1 mode + /// @li <b>0</b> - forced to stop + /// @li <b>1</b> - functioning with CLKRUN protocol +// UINT32 SPI100_RX_Timing_Config_Register_38; ///< SPI100_RX_Timing_Config_Register_38 +// UINT16 SPI100_RX_Timing_Config_Register_3C; ///< SPI100_RX_Timing_Config_Register_3C +// UINT8 SpiProtectEn0_1d_34; /// + UINT8 SPI100_Enable; ///< Spi 100 Enable + SPI_DEVICE_PROFILE SpiDeviceProfile; ///< Spi Device Profile +} FCH_SPI; + + +/// +/// IDE structure +/// +typedef struct { + BOOLEAN IdeEnable; ///< IDE function switch + BOOLEAN IdeMsiEnable; ///< IDE MSI capability + UINT32 IdeSsid; ///< IDE controller Subsystem ID +} FCH_IDE; + +/// +/// IR Structure +/// +typedef struct { + IR_CONFIG IrConfig; ///< IrConfig + UINT8 IrPinControl; ///< IrPinControl +} FCH_IR; + + +/// +/// PCI Bridge Structure +/// +typedef struct { + BOOLEAN PcibMsiEnable; ///< PCI-PCI Bridge MSI capability + UINT32 PcibSsid; ///< PCI-PCI Bridge Subsystem ID + UINT8 PciClks; ///< 33MHz PCICLK0/1/2/3 Enable, bits [0:3] used + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + UINT16 PcibClkStopOverride; ///< PCIB_CLK_Stop Override + BOOLEAN PcibClockRun; ///< Enable the auto clkrun functionality + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// +} FCH_PCIB; + + +/// +/// - SATA Phy setting structure +/// +typedef struct _SATA_PHY_SETTING { + UINT16 PhyCoreControlWord; /// PhyCoreControlWord - Reserved + UINT32 PhyFineTuneDword; /// PhyFineTuneDword - Reserved +} SATA_PHY_SETTING; + +/// +/// SATA main setting structure +/// +typedef struct _SATA_ST { + UINT8 SataModeReg; ///< SataModeReg - Sata Controller Mode + BOOLEAN SataEnable; ///< SataEnable - Sata Controller Function + /// @par + /// Sata Controller + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + UINT8 Sata6AhciCap; ///< Sata6AhciCap - Reserved */ + BOOLEAN SataSetMaxGen2; ///< SataSetMaxGen2 - Set Sata Max Gen2 mode + /// @par + /// Sata Controller Set to Max Gen2 mode + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + BOOLEAN IdeEnable; ///< IdeEnable - Hidden IDE + /// @par + /// Sata IDE Controller Combined Mode + /// Enable - SATA controller has control over Port0 through Port3, + /// IDE controller has control over Port4 and Port7. + /// Disable - SATA controller has full control of all 8 Ports + /// when operating in non-IDE mode. + /// @li <b>0</b> - enable + /// @li <b>1</b> - disable + /// + UINT8 SataClkMode; /// SataClkMode - Reserved +} SATA_ST; + +/// +/// SATA_PORT_ST - SATA PORT structure +/// +typedef struct _SATA_PORT_ST { + UINT8 SataPortReg; ///< SATA Port bit map - bits[0:7] for ports 0 ~ 7 + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + BOOLEAN Port0; ///< PORT0 - 0:disable, 1:enable + BOOLEAN Port1; ///< PORT1 - 0:disable, 1:enable + BOOLEAN Port2; ///< PORT2 - 0:disable, 1:enable + BOOLEAN Port3; ///< PORT3 - 0:disable, 1:enable + BOOLEAN Port4; ///< PORT4 - 0:disable, 1:enable + BOOLEAN Port5; ///< PORT5 - 0:disable, 1:enable + BOOLEAN Port6; ///< PORT6 - 0:disable, 1:enable + BOOLEAN Port7; ///< PORT7 - 0:disable, 1:enable +} SATA_PORT_ST; + +/// +///< _SATA_PORT_MD - Force Each PORT to GEN1/GEN2 mode +/// +typedef struct _SATA_PORT_MD { + UINT16 SataPortMode; ///< SATA Port GEN1/GEN2 mode bit map - bits [0:15] for ports 0 ~ 7 + UINT8 Port0; ///< PORT0 - set BIT0 to GEN1, BIT1 - PORT0 set to GEN2 + UINT8 Port1; ///< PORT1 - set BIT2 to GEN1, BIT3 - PORT1 set to GEN2 + UINT8 Port2; ///< PORT2 - set BIT4 to GEN1, BIT5 - PORT2 set to GEN2 + UINT8 Port3; ///< PORT3 - set BIT6 to GEN1, BIT7 - PORT3 set to GEN2 + UINT8 Port4; ///< PORT4 - set BIT8 to GEN1, BIT9 - PORT4 set to GEN2 + UINT8 Port5; ///< PORT5 - set BIT10 to GEN1, BIT11 - PORT5 set to GEN2 + UINT8 Port6; ///< PORT6 - set BIT12 to GEN1, BIT13 - PORT6 set to GEN2 + UINT8 Port7; ///< PORT7 - set BIT14 to GEN1, BIT15 - PORT7 set to GEN2 +} SATA_PORT_MD; +/// +/// SATA structure +/// +typedef struct { + BOOLEAN SataMsiEnable; ///< SATA MSI capability + UINT32 SataIdeSsid; ///< SATA IDE mode SSID + UINT32 SataRaidSsid; ///< SATA RAID mode SSID + UINT32 SataRaid5Ssid; ///< SATA RAID 5 mode SSID + UINT32 SataAhciSsid; ///< SATA AHCI mode SSID + + SATA_ST SataMode; /// SataMode - Reserved + SATA_CLASS SataClass; ///< SataClass - SATA Controller mode [2:0] + UINT8 SataIdeMode; ///< SataIdeMode - Sata IDE Controller mode + /// @par + /// @li <b>0</b> - Legacy IDE mode + /// @li <b>1</b> - Native IDE mode + /// + UINT8 SataDisUnusedIdePChannel; ///< SataDisUnusedIdePChannel-Disable Unused IDE Primary Channel + /// @par + /// @li <b>0</b> - Channel Enable + /// @li <b>1</b> - Channel Disable + /// + UINT8 SataDisUnusedIdeSChannel; ///< SataDisUnusedIdeSChannel - Disable Unused IDE Secondary Channel + /// @par + /// @li <b>0</b> - Channel Enable + /// @li <b>1</b> - Channel Disable + /// + UINT8 IdeDisUnusedIdePChannel; ///< IdeDisUnusedIdePChannel-Disable Unused IDE Primary Channel + /// @par + /// @li <b>0</b> - Channel Enable + /// @li <b>1</b> - Channel Disable + /// + UINT8 IdeDisUnusedIdeSChannel; ///< IdeDisUnusedIdeSChannel-Disable Unused IDE Secondary Channel + /// @par + /// @li <b>0</b> - Channel Enable + /// @li <b>1</b> - Channel Disable + /// + UINT8 SataOptionReserved; /// SataOptionReserved - Reserved + + SATA_PORT_ST SataEspPort; ///< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:) + + SATA_PORT_ST SataPortPower; ///< SataPortPower - Port Power configuration + + SATA_PORT_MD SataPortMd; ///< SataPortMd - Port Mode + + UINT8 SataAggrLinkPmCap; /// SataAggrLinkPmCap - 0:OFF 1:ON + UINT8 SataPortMultCap; /// SataPortMultCap - 0:OFF 1:ON + UINT8 SataClkAutoOff; /// SataClkAutoOff - AutoClockOff 0:Disabled, 1:Enabled + UINT8 SataPscCap; /// SataPscCap 1:Enable PSC, 0:Disable PSC capability + UINT8 BiosOsHandOff; /// BiosOsHandOff - Reserved + UINT8 SataFisBasedSwitching; /// SataFisBasedSwitching - Reserved + UINT8 SataCccSupport; /// SataCccSupport - Reserved + UINT8 SataSscCap; /// SataSscCap - 1:Enable, 0:Disable SSC capability + UINT8 SataMsiCapability; /// SataMsiCapability 0:Hidden 1:Visible + UINT8 SataForceRaid; /// SataForceRaid 0:No function 1:Force RAID + UINT8 SataInternal100Spread; /// SataInternal100Spread - Reserved + UINT8 SataDebugDummy; /// SataDebugDummy - Reserved + UINT8 SataTargetSupport8Device; /// SataTargetSupport8Device - Reserved + UINT8 SataDisableGenericMode; /// SataDisableGenericMode - Reserved + BOOLEAN SataAhciEnclosureManagement; /// SataAhciEnclosureManagement - Reserved + UINT8 SataSgpio0; /// SataSgpio0 - Reserved + UINT8 SataSgpio1; /// SataSgpio1 - Reserved + UINT8 SataPhyPllShutDown; /// SataPhyPllShutDown - Reserved + BOOLEAN SataHotRemovalEnh; /// SataHotRemovalEnh - Reserved + + SATA_PORT_ST SataHotRemovalEnhPort; ///< SataHotRemovalEnhPort - Hot Remove + + BOOLEAN SataOobDetectionEnh; /// SataOobDetectionEnh - TRUE + BOOLEAN SataPowerSavingEnh; /// SataPowerSavingEnh - TRUE + UINT8 SataMemoryPowerSaving; /// SataMemoryPowerSaving - 0-3 Default [3] + BOOLEAN SataRasSupport; /// SataRasSupport - Support RAS function TRUE: Enable FALSE: Disable + BOOLEAN SataAhciDisPrefetchFunction; /// SataAhciDisPrefetchFunction - Disable AHCI Prefetch Function Support + BOOLEAN SataDevSlpPort0; /// SataDevSlpPort0 - Reserved + BOOLEAN SataDevSlpPort1; /// SataDevSlpPort1 - Reserved +// UINT8 SataDevSlpPort0S5Pin; /// SataDevSlpPort0S5Pin - Reserved +// UINT8 SataDevSlpPort1S5Pin; /// SataDevSlpPort1S5Pin - Reserved + UINT8 SataDbgTX_DRV_STR ; /// TX_DRV_STR - Reserved + UINT8 SataDbgTX_DE_EMPH_STR ; /// TX_DE_EMPH_STR - Reserved + UINT32 TempMmio; /// TempMmio - Reserved +} FCH_SATA; + + +// +// IMC Message Register Software Interface +// +#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3) + +#define MSG_SYS_TO_IMC 0x80 +#define Fun_80 0x80 +#define Fun_81 0x81 +#define Fun_82 0x82 +#define Fun_83 0x83 +#define Fun_84 0x84 +#define Fun_85 0x85 +#define Fun_86 0x86 +#define Fun_87 0x87 +#define Fun_88 0x88 +#define Fun_89 0x89 +#define Fun_90 0x90 +#define MSG_IMC_TO_SYS 0x81 +#define MSG_REG0 0x82 +#define MSG_REG1 0x83 +#define MSG_REG2 0x84 +#define MSG_REG3 0x85 +#define MSG_REG4 0x86 +#define MSG_REG5 0x87 +#define MSG_REG6 0x88 +#define MSG_REG7 0x89 +#define MSG_REG8 0x8A +#define MSG_REG9 0x8B +#define MSG_REGA 0x8C +#define MSG_REGB 0x8D +#define MSG_REGC 0x8E +#define MSG_REGD 0x8F + +#define DISABLED 0 +#define ENABLED 1 + + + +/// +/// EC structure +/// +typedef struct _FCH_EC { + UINT8 MsgFun81Zone0MsgReg0; ///<Thermal zone + UINT8 MsgFun81Zone0MsgReg1; ///<Thermal zone + UINT8 MsgFun81Zone0MsgReg2; ///<Thermal zone control byte 1 + UINT8 MsgFun81Zone0MsgReg3; ///<Thermal zone control byte 2 + UINT8 MsgFun81Zone0MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. + UINT8 MsgFun81Zone0MsgReg5; ///<Hysteresis information + UINT8 MsgFun81Zone0MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 + UINT8 MsgFun81Zone0MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. + UINT8 MsgFun81Zone0MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage + UINT8 MsgFun81Zone0MsgReg9; ///<Fan PWM ramping rate in 5ms unit +// +// EC LDN9 function 81 zone 1 +// + UINT8 MsgFun81Zone1MsgReg0; ///<Thermal zone + UINT8 MsgFun81Zone1MsgReg1; ///<Thermal zone + UINT8 MsgFun81Zone1MsgReg2; ///<Thermal zone control byte 1 + UINT8 MsgFun81Zone1MsgReg3; ///<Thermal zone control byte 2 + UINT8 MsgFun81Zone1MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. + UINT8 MsgFun81Zone1MsgReg5; ///<Hysteresis information + UINT8 MsgFun81Zone1MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 + UINT8 MsgFun81Zone1MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. + UINT8 MsgFun81Zone1MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage + UINT8 MsgFun81Zone1MsgReg9; ///<Fan PWM ramping rate in 5ms unit +// +//EC LDN9 function 81 zone 2 +// + UINT8 MsgFun81Zone2MsgReg0; ///<Thermal zone + UINT8 MsgFun81Zone2MsgReg1; ///<Thermal zone + UINT8 MsgFun81Zone2MsgReg2; ///<Thermal zone control byte 1 + UINT8 MsgFun81Zone2MsgReg3; ///<Thermal zone control byte 2 + UINT8 MsgFun81Zone2MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. + UINT8 MsgFun81Zone2MsgReg5; ///<Hysteresis information + UINT8 MsgFun81Zone2MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 + UINT8 MsgFun81Zone2MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. + UINT8 MsgFun81Zone2MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage + UINT8 MsgFun81Zone2MsgReg9; ///<Fan PWM ramping rate in 5ms unit +// +//EC LDN9 function 81 zone 3 +// + UINT8 MsgFun81Zone3MsgReg0; ///<Thermal zone + UINT8 MsgFun81Zone3MsgReg1; ///<Thermal zone + UINT8 MsgFun81Zone3MsgReg2; ///<Thermal zone control byte 1 + UINT8 MsgFun81Zone3MsgReg3; ///<Thermal zone control byte 2 + UINT8 MsgFun81Zone3MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius. + UINT8 MsgFun81Zone3MsgReg5; ///<Hysteresis information + UINT8 MsgFun81Zone3MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 + UINT8 MsgFun81Zone3MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located. + UINT8 MsgFun81Zone3MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage + UINT8 MsgFun81Zone3MsgReg9; ///<Fan PWM ramping rate in 5ms unit +// +//EC LDN9 function 83 zone 0 +// + UINT8 MsgFun83Zone0MsgReg0; ///<Thermal zone + UINT8 MsgFun83Zone0MsgReg1; ///<Thermal zone + UINT8 MsgFun83Zone0MsgReg2; ///<_AC0 + UINT8 MsgFun83Zone0MsgReg3; ///<_AC1 + UINT8 MsgFun83Zone0MsgReg4; ///<_AC2 + UINT8 MsgFun83Zone0MsgReg5; ///<_AC3 + UINT8 MsgFun83Zone0MsgReg6; ///<_AC4 + UINT8 MsgFun83Zone0MsgReg7; ///<_AC5 + UINT8 MsgFun83Zone0MsgReg8; ///<_AC6 + UINT8 MsgFun83Zone0MsgReg9; ///<_AC7 + UINT8 MsgFun83Zone0MsgRegA; ///<_CRT + UINT8 MsgFun83Zone0MsgRegB; ///<_PSV +// +//EC LDN9 function 83 zone 1 +// + UINT8 MsgFun83Zone1MsgReg0; ///<Thermal zone + UINT8 MsgFun83Zone1MsgReg1; ///<Thermal zone + UINT8 MsgFun83Zone1MsgReg2; ///<_AC0 + UINT8 MsgFun83Zone1MsgReg3; ///<_AC1 + UINT8 MsgFun83Zone1MsgReg4; ///<_AC2 + UINT8 MsgFun83Zone1MsgReg5; ///<_AC3 + UINT8 MsgFun83Zone1MsgReg6; ///<_AC4 + UINT8 MsgFun83Zone1MsgReg7; ///<_AC5 + UINT8 MsgFun83Zone1MsgReg8; ///<_AC6 + UINT8 MsgFun83Zone1MsgReg9; ///<_AC7 + UINT8 MsgFun83Zone1MsgRegA; ///<_CRT + UINT8 MsgFun83Zone1MsgRegB; ///<_PSV +// +//EC LDN9 function 83 zone 2 +// + UINT8 MsgFun83Zone2MsgReg0; ///<Thermal zone + UINT8 MsgFun83Zone2MsgReg1; ///<Thermal zone + UINT8 MsgFun83Zone2MsgReg2; ///<_AC0 + UINT8 MsgFun83Zone2MsgReg3; ///<_AC1 + UINT8 MsgFun83Zone2MsgReg4; ///<_AC2 + UINT8 MsgFun83Zone2MsgReg5; ///<_AC3 + UINT8 MsgFun83Zone2MsgReg6; ///<_AC4 + UINT8 MsgFun83Zone2MsgReg7; ///<_AC5 + UINT8 MsgFun83Zone2MsgReg8; ///<_AC6 + UINT8 MsgFun83Zone2MsgReg9; ///<_AC7 + UINT8 MsgFun83Zone2MsgRegA; ///<_CRT + UINT8 MsgFun83Zone2MsgRegB; ///<_PSV +// +//EC LDN9 function 83 zone 3 +// + UINT8 MsgFun83Zone3MsgReg0; ///<Thermal zone + UINT8 MsgFun83Zone3MsgReg1; ///<Thermal zone + UINT8 MsgFun83Zone3MsgReg2; ///<_AC0 + UINT8 MsgFun83Zone3MsgReg3; ///<_AC1 + UINT8 MsgFun83Zone3MsgReg4; ///<_AC2 + UINT8 MsgFun83Zone3MsgReg5; ///<_AC3 + UINT8 MsgFun83Zone3MsgReg6; ///<_AC4 + UINT8 MsgFun83Zone3MsgReg7; ///<_AC5 + UINT8 MsgFun83Zone3MsgReg8; ///<_AC6 + UINT8 MsgFun83Zone3MsgReg9; ///<_AC7 + UINT8 MsgFun83Zone3MsgRegA; ///<_CRT + UINT8 MsgFun83Zone3MsgRegB; ///<_PSV +// +//EC LDN9 function 85 zone 0 +// + UINT8 MsgFun85Zone0MsgReg0; ///<Thermal zone + UINT8 MsgFun85Zone0MsgReg1; ///<Thermal zone + UINT8 MsgFun85Zone0MsgReg2; ///<AL0 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg3; ///<AL1 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg4; ///<AL2 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg5; ///<AL3 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg6; ///<AL4 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg7; ///<AL5 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg8; ///<AL6 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone0MsgReg9; ///<AL7 PWM level in percentage (0 - 100%) +// +//EC LDN9 function 85 zone 1 +// + UINT8 MsgFun85Zone1MsgReg0; ///<Thermal zone + UINT8 MsgFun85Zone1MsgReg1; ///<Thermal zone + UINT8 MsgFun85Zone1MsgReg2; ///<AL0 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg3; ///<AL1 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg4; ///<AL2 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg5; ///<AL3 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg6; ///<AL4 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg7; ///<AL5 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg8; ///<AL6 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone1MsgReg9; ///<AL7 PWM level in percentage (0 - 100%) +// +//EC LDN9 function 85 zone 2 +// + UINT8 MsgFun85Zone2MsgReg0; ///<Thermal zone + UINT8 MsgFun85Zone2MsgReg1; ///<Thermal zone + UINT8 MsgFun85Zone2MsgReg2; ///<AL0 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg3; ///<AL1 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg4; ///<AL2 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg5; ///<AL3 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg6; ///<AL4 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg7; ///<AL5 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg8; ///<AL6 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone2MsgReg9; ///<AL7 PWM level in percentage (0 - 100%) +// +//EC LDN9 function 85 zone 3 +// + UINT8 MsgFun85Zone3MsgReg0; ///<Thermal zone + UINT8 MsgFun85Zone3MsgReg1; ///<Thermal zone + UINT8 MsgFun85Zone3MsgReg2; ///<AL0 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg3; ///<AL1 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg4; ///<AL2 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg5; ///<AL3 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg6; ///<AL4 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg7; ///<AL5 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg8; ///<AL6 PWM level in percentage (0 - 100%) + UINT8 MsgFun85Zone3MsgReg9; ///<AL7 PWM level in percentage (0 - 100%) +// +//EC LDN9 function 89 TEMPIN channel 0 +// + UINT8 MsgFun89Zone0MsgReg0; ///<Thermal zone + UINT8 MsgFun89Zone0MsgReg1; ///<Thermal zone + UINT8 MsgFun89Zone0MsgReg2; ///<At DWORD bit 0-7 + UINT8 MsgFun89Zone0MsgReg3; ///<At DWORD bit 15-8 + UINT8 MsgFun89Zone0MsgReg4; ///<At DWORD bit 23-16 + UINT8 MsgFun89Zone0MsgReg5; ///<At DWORD bit 31-24 + UINT8 MsgFun89Zone0MsgReg6; ///<Ct DWORD bit 0-7 + UINT8 MsgFun89Zone0MsgReg7; ///<Ct DWORD bit 15-8 + UINT8 MsgFun89Zone0MsgReg8; ///<Ct DWORD bit 23-16 + UINT8 MsgFun89Zone0MsgReg9; ///<Ct DWORD bit 31-24 + UINT8 MsgFun89Zone0MsgRegA; ///<Mode bit 0-7 +// +//EC LDN9 function 89 TEMPIN channel 1 +// + UINT8 MsgFun89Zone1MsgReg0; ///<Thermal zone + UINT8 MsgFun89Zone1MsgReg1; ///<Thermal zone + UINT8 MsgFun89Zone1MsgReg2; ///<At DWORD bit 0-7 + UINT8 MsgFun89Zone1MsgReg3; ///<At DWORD bit 15-8 + UINT8 MsgFun89Zone1MsgReg4; ///<At DWORD bit 23-16 + UINT8 MsgFun89Zone1MsgReg5; ///<At DWORD bit 31-24 + UINT8 MsgFun89Zone1MsgReg6; ///<Ct DWORD bit 0-7 + UINT8 MsgFun89Zone1MsgReg7; ///<Ct DWORD bit 15-8 + UINT8 MsgFun89Zone1MsgReg8; ///<Ct DWORD bit 23-16 + UINT8 MsgFun89Zone1MsgReg9; ///<Ct DWORD bit 31-24 + UINT8 MsgFun89Zone1MsgRegA; ///<Mode bit 0-7 +// +//EC LDN9 function 89 TEMPIN channel 2 +// + UINT8 MsgFun89Zone2MsgReg0; ///<Thermal zone + UINT8 MsgFun89Zone2MsgReg1; ///<Thermal zone + UINT8 MsgFun89Zone2MsgReg2; ///<At DWORD bit 0-7 + UINT8 MsgFun89Zone2MsgReg3; ///<At DWORD bit 15-8 + UINT8 MsgFun89Zone2MsgReg4; ///<At DWORD bit 23-16 + UINT8 MsgFun89Zone2MsgReg5; ///<At DWORD bit 31-24 + UINT8 MsgFun89Zone2MsgReg6; ///<Ct DWORD bit 0-7 + UINT8 MsgFun89Zone2MsgReg7; ///<Ct DWORD bit 15-8 + UINT8 MsgFun89Zone2MsgReg8; ///<Ct DWORD bit 23-16 + UINT8 MsgFun89Zone2MsgReg9; ///<Ct DWORD bit 31-24 + UINT8 MsgFun89Zone2MsgRegA; ///<Mode bit 0-7 +// +//EC LDN9 function 89 TEMPIN channel 3 +// + UINT8 MsgFun89Zone3MsgReg0; ///<Thermal zone + UINT8 MsgFun89Zone3MsgReg1; ///<Thermal zone + UINT8 MsgFun89Zone3MsgReg2; ///<At DWORD bit 0-7 + UINT8 MsgFun89Zone3MsgReg3; ///<At DWORD bit 15-8 + UINT8 MsgFun89Zone3MsgReg4; ///<At DWORD bit 23-16 + UINT8 MsgFun89Zone3MsgReg5; ///<At DWORD bit 31-24 + UINT8 MsgFun89Zone3MsgReg6; ///<Ct DWORD bit 0-7 + UINT8 MsgFun89Zone3MsgReg7; ///<Ct DWORD bit 15-8 + UINT8 MsgFun89Zone3MsgReg8; ///<Ct DWORD bit 23-16 + UINT8 MsgFun89Zone3MsgReg9; ///<Ct DWORD bit 31-24 + UINT8 MsgFun89Zone3MsgRegA; ///<Mode bit 0-7 +// +// FLAG for Fun83/85/89 support +// + UINT16 IMCFUNSupportBitMap; ///< Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3; +} FCH_EC; + +/// +/// IMC structure +/// +typedef struct _FCH_IMC { + UINT8 ImcEnable; ///< ImcEnable - IMC Enable + UINT8 ImcEnabled; ///< ImcEnabled - IMC Enable + UINT8 ImcSureBootTimer; ///< ImcSureBootTimer - IMc SureBootTimer function + FCH_EC EcStruct; ///< EC structure + UINT8 ImcEnableOverWrite; ///< OverWrite IMC with the EC structure + /// @li <b>00</b> - by default strapping + /// @li <b>01</b> - enable + /// @li <b>10</b> - disable + /// +} FCH_IMC; + + +/// +/// Hpet structure +/// +typedef struct { + BOOLEAN HpetEnable; ///< HPET function switch + + BOOLEAN HpetMsiDis; ///< HpetMsiDis - South Bridge HPET MSI Configuration + /// @par + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT32 HpetBase; ///< HpetBase + /// @par + /// HPET Base address +} FCH_HPET; + + +/// +/// GCPU related parameters +/// +typedef struct { + UINT8 AcDcMsg; ///< Send a message to CPU to indicate the power mode (AC vs battery) + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT8 TimerTickTrack; ///< Send a message to CPU to indicate the latest periodic timer interval + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT8 ClockInterruptTag; ///< Mark the periodic timer interrupt + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT8 OhciTrafficHanding; ///< Cause CPU to break out from C state when USB OHCI has pending traffic + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT8 EhciTrafficHanding; ///< Cause CPU to break out from C state when USB EHCI has pending traffic + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT8 GcpuMsgCMultiCore; ///< Track of CPU C state by monitoring each core's C state message + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable + + UINT8 GcpuMsgCStage; ///< Enable the FCH C state coordination logic + /// @li <b>1</b> - disable + /// @li <b>0</b> - enable +} FCH_GCPU; + + +/// +/// Timer +/// +typedef struct { + BOOLEAN Enable; ///< Whether to register timer SMI in POST + BOOLEAN StartNow; ///< Whether to start the SMI immediately during registration + UINT16 CycleDuration; ///< [14:0] - Actual cycle duration = CycleDuration + 1 +} TIMER_SMI; + +/// +/// CS support +/// +typedef struct { + BOOLEAN FchCsD3Cold; ///< FCH Cs D3 Cold function + BOOLEAN FchCsHwReduced; ///< FCH Cs hardware reduced ACPI flag + BOOLEAN FchCsPwrBtn; ///< FCH Cs Power Button function + BOOLEAN FchCsAcDc; ///< FCH Cs AcDc function + BOOLEAN AsfNfcEnable; ///< FCH Cs NFC function + UINT8 AsfNfcInterruptPin; ///< NFC Interrupt pin define + UINT8 AsfNfcRegPuPin; ///< NFC RegPu pin define + UINT8 AsfNfcWakePin; ///< NFC Wake Pin define + UINT8 PowerButtonGpe; ///< GPE# used by Power Button device + UINT8 AcDcTimerGpe; ///< GPE# used by Timer device +} FCH_CS; + + +/// +/// MISC structure +/// +typedef struct { + BOOLEAN NativePcieSupport; /// PCIe NativePcieSupport - Debug function. 1:Enabled, 0:Disabled + BOOLEAN S3Resume; /// S3Resume - Flag of ACPI S3 Resume. + BOOLEAN RebootRequired; /// RebootRequired - Flag of Reboot system is required. + UINT8 FchVariant; /// FchVariant - FCH Variant value. + UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable + TIMER_SMI LongTimer; ///< Long Timer SMI + TIMER_SMI ShortTimer; ///< Short Timer SMI + UINT32 FchCpuId; ///< Saving CpuId for FCH Module. + BOOLEAN NoneSioKbcSupport; ///< NoneSioKbcSupport - No KBC/SIO controller ( Turn on Inchip KBC emulation function ) + FCH_CS FchCsSupport; ///< FCH Cs function structure +} FCH_MISC; + + +/// +/// SMBus structure +/// +typedef struct { + UINT32 SmbusSsid; ///< SMBUS controller Subsystem ID +} FCH_SMBUS; + + +/// +/// Acpi structure +/// +typedef struct { + UINT16 Smbus0BaseAddress; ///< Smbus0BaseAddress + /// @par + /// Smbus BASE Address + /// + UINT16 Smbus1BaseAddress; ///< Smbus1BaseAddress + /// @par + /// Smbus1 (ASF) BASE Address + /// + UINT16 SioPmeBaseAddress; ///< SioPmeBaseAddress + /// @par + /// SIO PME BASE Address + /// + UINT32 WatchDogTimerBase; ///< WatchDogTimerBase + /// @par + /// Watch Dog Timer Address + /// + UINT16 AcpiPm1EvtBlkAddr; ///< AcpiPm1EvtBlkAddr + /// @par + /// ACPI PM1 event block Address + /// + UINT16 AcpiPm1CntBlkAddr; ///< AcpiPm1CntBlkAddr + /// @par + /// ACPI PM1 Control block Address + /// + UINT16 AcpiPmTmrBlkAddr; ///< AcpiPmTmrBlkAddr + /// @par + /// ACPI PM timer block Address + /// + UINT16 CpuControlBlkAddr; ///< CpuControlBlkAddr + /// @par + /// ACPI CPU control block Address + /// + UINT16 AcpiGpe0BlkAddr; ///< AcpiGpe0BlkAddr + /// @par + /// ACPI GPE0 block Address + /// + UINT16 SmiCmdPortAddr; ///< SmiCmdPortAddr + /// @par + /// SMI command port Address + /// + UINT16 AcpiPmaCntBlkAddr; ///< AcpiPmaCntBlkAddr + /// @par + /// ACPI PMA Control block Address + /// + BOOLEAN AnyHt200MhzLink; ///< AnyHt200MhzLink + /// @par + /// HT Link Speed on 200MHz option for each CPU specific LDTSTP# (Force enable) + /// + BOOLEAN SpreadSpectrum; ///< SpreadSpectrum + /// @par + /// Spread Spectrum function + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + POWER_FAIL PwrFailShadow; ///< PwrFailShadow = PM_Reg: 5Bh [3:0] + /// @par + /// @li <b>00</b> - Always off + /// @li <b>01</b> - Always on + /// @li <b>11</b> - Use previous + /// + UINT8 StressResetMode; ///< StressResetMode 01-10 + /// @li <b>00</b> - Disabed + /// @li <b>01</b> - Io Write 0x64 with 0xfe + /// @li <b>10</b> - Io Write 0xcf9 with 0x06 + /// @li <b>11</b> - Io Write 0xcf9 with 0x0e + /// + BOOLEAN MtC1eEnable; /// MtC1eEnable - Enable MtC1e + VOID* OemProgrammingTablePtr; /// Pointer of ACPI OEM table + UINT8 SpreadSpectrumOptions; /// SpreadSpectrumOptions - Spread Spectrum Option + BOOLEAN PwrDownDisp2ClkPcieR; /// Power down DISP2_CLK and PCIE_RCLK_Output for power savings +} FCH_ACPI; + + +/// +/// HWM temp parameter structure +/// +typedef struct _FCH_HWM_TEMP_PAR { + UINT16 At; ///< At + UINT16 Ct; ///< Ct + UINT8 Mode; ///< Mode BIT0:HiRatio BIT1:HiCurrent +} FCH_HWM_TEMP_PAR; + +/// +/// HWM Current structure +/// +typedef struct _FCH_HWM_CUR { + UINT16 FanSpeed[5]; ///< FanSpeed - fan Speed + UINT16 Temperature[5]; ///< Temperature - temperature + UINT16 Voltage[8]; ///< Voltage - voltage +} FCH_HWM_CUR; + +/// +/// HWM fan control structure +/// +typedef struct _FCH_HWM_FAN_CTR { + UINT8 InputControlReg00; /// Fan Input Control register, PM2 offset [0:4]0 + UINT8 ControlReg01; /// Fan control register, PM2 offset [0:4]1 + UINT8 FreqReg02; /// Fan frequency register, PM2 offset [0:4]2 + UINT8 LowDutyReg03; /// Low Duty register, PM2 offset [0:4]3 + UINT8 MedDutyReg04; /// Med Duty register, PM2 offset [0:4]4 + UINT8 MultiplierReg05; /// Multiplier register, PM2 offset [0:4]5 + UINT16 LowTempReg06; /// Low Temp register, PM2 offset [0:4]6 + UINT16 MedTempReg08; /// Med Temp register, PM2 offset [0:4]8 + UINT16 HighTempReg0A; /// High Temp register, PM2 offset [0:4]A + UINT8 LinearRangeReg0C; /// Linear Range register, PM2 offset [0:4]C + UINT8 LinearHoldCountReg0D; /// Linear Hold Count register, PM2 offset [0:4]D +} FCH_HWM_FAN_CTR; + +/// +/// Hwm structure +/// +typedef struct _FCH_HWM { + UINT8 HwMonitorEnable; ///< HwMonitorEnable + UINT32 HwmControl; ///< hwmControl + /// @par + /// HWM control configuration + /// @li <b>0</b> - HWM is Enabled + /// @li <b>1</b> - IMC is Enabled + /// + UINT8 FanSampleFreqDiv; ///< Sampling rate of Fan Speed + /// @li <b>00</b> - Base(22.5KHz) + /// @li <b>01</b> - Base(22.5KHz)/2 + /// @li <b>10</b> - Base(22.5KHz)/4 + /// @li <b>11</b> - Base(22.5KHz)/8 + /// + UINT8 HwmFchtsiAutoPoll; ///< TSI Auto Polling + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + UINT8 HwmFchtsiAutoPollStarted; ///< HwmSbtsiAutoPollStarted + UINT8 FanLinearEnhanceEn; ///< FanLinearEnhanceEn + UINT8 FanLinearHoldFix; ///< FanLinearHoldFix + UINT8 FanLinearRangeOutLimit; ///< FanLinearRangeOutLimit + UINT16 HwmCalibrationFactor; /// Calibration Factor + FCH_HWM_CUR HwmCurrent; /// HWM Current structure + FCH_HWM_CUR HwmCurrentRaw; /// HWM Current Raw structure + FCH_HWM_TEMP_PAR HwmTempPar[5]; /// HWM Temp parameter structure + FCH_HWM_FAN_CTR HwmFanControl[5]; /// HWM Fan Control structure + FCH_HWM_FAN_CTR HwmFanControlCooked[5]; /// HWM Fan Control structure +} FCH_HWM; + + +/// +/// Gec structure +/// +typedef struct { + BOOLEAN GecEnable; ///< GecEnable - GEC function switch + UINT8 GecPhyStatus; /// GEC PHY Status + UINT8 GecPowerPolicy; /// GEC Power Policy + /// @li <b>00</b> - GEC is powered down in S3 and S5 + /// @li <b>01</b> - GEC is powered down only in S5 + /// @li <b>10</b> - GEC is powered down only in S3 + /// @li <b>11</b> - GEC is never powered down + /// + UINT8 GecDebugBus; /// GEC Debug Bus + /// @li <b>0</b> - disable + /// @li <b>1</b> - enable + /// + UINT32 GecShadowRomBase; ///< GecShadowRomBase + /// @par + /// GEC (NIC) SHADOWROM BASE Address + /// + VOID *PtrDynamicGecRomAddress; /// Pointer of Dynamic GEC ROM Address +} FCH_GEC; + + +/// +/// _ABTblEntry - AB link register table R/W structure +/// +typedef struct _AB_TBL_ENTRY { + UINT8 RegType; /// RegType : AB Register Type (ABCFG, AXCFG and so on) + UINT32 RegIndex; /// RegIndex : AB Register Index + UINT32 RegMask; /// RegMask : AB Register Mask + UINT32 RegData; /// RegData : AB Register Data +} AB_TBL_ENTRY; + +/// +/// AB structure +/// +typedef struct { + BOOLEAN AbMsiEnable; ///< ABlink MSI capability + UINT8 ALinkClkGateOff; /// Alink Clock Gate-Off function - 0:disable, 1:enable *KR + UINT8 BLinkClkGateOff; /// Blink Clock Gate-Off function - 0:disable, 1:enable *KR + UINT8 GppClockRequest0; /// GPP Clock Request. + UINT8 GppClockRequest1; /// GPP Clock Request. + UINT8 GppClockRequest2; /// GPP Clock Request. + UINT8 GppClockRequest3; /// GPP Clock Request. + UINT8 GfxClockRequest; /// GPP Clock Request. + UINT8 AbClockGating; /// AB Clock Gating - 0:disable, 1:enable *KR *CZ + UINT8 GppClockGating; /// GPP Clock Gating - 0:disable, 1:enable + UINT8 UmiL1TimerOverride; /// UMI L1 inactivity timer overwrite value + UINT8 UmiLinkWidth; /// UMI Link Width + UINT8 UmiDynamicSpeedChange; /// UMI Dynamic Speed Change - 0:disable, 1:enable + UINT8 PcieRefClockOverClocking; /// PCIe Ref Clock OverClocking value + UINT8 UmiGppTxDriverStrength; /// UMI GPP TX Driver Strength + BOOLEAN NbSbGen2; /// UMI link Gen2 - 0:Gen1, 1:Gen2 + UINT8 PcieOrderRule; /// PCIe Order Rule - 0:disable, 1:enable *KR AB Posted Pass Non-Posted + UINT8 SlowSpeedAbLinkClock; /// Slow Speed AB Link Clock - 0:disable, 1:enable *KR + BOOLEAN ResetCpuOnSyncFlood; /// Reset Cpu On Sync Flood - 0:disable, 1:enable *KR + BOOLEAN AbDmaMemoryWrtie3264B; /// AB DMA Memory Write 32/64 BYTE Support *KR only + BOOLEAN AbMemoryPowerSaving; /// AB Memory Power Saving *KR *CZ + BOOLEAN SbgDmaMemoryWrtie3264ByteCount; /// SBG DMA Memory Write 32/64 BYTE Count Support *KR only + BOOLEAN SbgMemoryPowerSaving; /// SBG Memory Power Saving *KR *CZ + BOOLEAN SbgClockGating; /// SBG Clock Gate *CZ + BOOLEAN XdmaDmaWrite16ByteMode; /// XDMA DMA Write 16 byte mode *CZ + BOOLEAN XdmaMemoryPowerSaving; /// XDMA memory power saving *CZ + UINT8 XdmaPendingNprThreshold; /// XDMA PENDING NPR THRESHOLD *CZ + BOOLEAN XdmaDncplOrderDis; /// XDMA DNCPL ORDER DIS *CZ +} FCH_AB; + + +/** + * PCIE_CAP_ID - PCIe Cap ID + * + */ +#define PCIE_CAP_ID 0x10 + +/// +/// FCH_GPP_PORT_CONFIG - Fch GPP port config structure +/// +typedef struct { + BOOLEAN PortPresent; ///< Port connection + /// @par + /// @li <b>0</b> - Port doesn't have slot. No need to train the link + /// @li <b>1</b> - Port connection defined and needs to be trained + /// + BOOLEAN PortDetected; ///< Link training status + /// @par + /// @li <b>0</b> - EP not detected + /// @li <b>1</b> - EP detected + /// + BOOLEAN PortIsGen2; ///< Port link speed configuration + /// @par + /// @li <b>00</b> - Auto + /// @li <b>01</b> - Forced GEN1 + /// @li <b>10</b> - Forced GEN2 + /// @li <b>11</b> - Reserved + /// + BOOLEAN PortHotPlug; ///< Support hot plug? + /// @par + /// @li <b>0</b> - No support + /// @li <b>1</b> - support + /// + UINT8 PortMisc; /// PortMisc - Reserved +} FCH_GPP_PORT_CONFIG; + +/// +/// GPP structure +/// +typedef struct { + FCH_GPP_PORT_CONFIG PortCfg[4]; /// GPP port configuration structure + GPP_LINKMODE GppLinkConfig; ///< GppLinkConfig - PCIE_GPP_Enable[3:0] + /// @li <b>0000</b> - Port ABCD -> 4:0:0:0 + /// @li <b>0010</b> - Port ABCD -> 2:2:0:0 + /// @li <b>0011</b> - Port ABCD -> 2:1:1:0 + /// @li <b>0100</b> - Port ABCD -> 1:1:1:1 + /// + BOOLEAN GppFunctionEnable; ///< GPP Function - 0:disable, 1:enable + BOOLEAN GppToggleReset; ///< Toggle GPP core reset + UINT8 GppHotPlugGeventNum; ///< Hotplug GEVENT # - valid value 0-31 + UINT8 GppFoundGfxDev; ///< Gpp Found Gfx Device + /// @li <b>0</b> - Not found + /// @li <b>1</b> - Found + /// + BOOLEAN GppGen2; ///< GPP Gen2 - 0:disable, 1:enable + UINT8 GppGen2Strap; ///< GPP Gen2 Strap - 0:disable, 1:enable, FCH itself uses this + BOOLEAN GppMemWrImprove; ///< GPP Memory Write Improve - 0:disable, 1:enable + BOOLEAN GppUnhidePorts; ///< GPP Unhide Ports - 0:disable, 1:enable + UINT8 GppPortAspm; ///< GppPortAspm - ASPM state for all GPP ports + /// @li <b>01</b> - Disabled + /// @li <b>01</b> - L0s + /// @li <b>10</b> - L1 + /// @li <b>11</b> - L0s + L1 + /// + BOOLEAN GppLaneReversal; ///< GPP Lane Reversal - 0:disable, 1:enable + BOOLEAN GppPhyPllPowerDown; ///< GPP PHY PLL Power Down - 0:disable, 1:enable + BOOLEAN GppDynamicPowerSaving; ///< GPP Dynamic Power Saving - 0:disable, 1:enable + BOOLEAN PcieAer; ///< PcieAer - Advanced Error Report: 0/1-disable/enable + BOOLEAN PcieRas; ///< PCIe RAS - 0:disable, 1:enable + BOOLEAN PcieCompliance; ///< PCIe Compliance - 0:disable, 1:enable + BOOLEAN PcieSoftwareDownGrade; ///< PCIe Software Down Grade + BOOLEAN UmiPhyPllPowerDown; ///< UMI PHY PLL Power Down - 0:disable, 1:enable + BOOLEAN SerialDebugBusEnable; ///< Serial Debug Bus Enable + UINT8 GppHardwareDownGrade; ///< GppHardwareDownGrade - Gpp HW Down Grade function 0:Disable, 1-4: portA-D + UINT8 GppL1ImmediateAck; ///< GppL1ImmediateAck - Gpp L1 Immediate ACK 0: enable, 1: disable + BOOLEAN NewGppAlgorithm; ///< NewGppAlgorithm - New GPP procedure + UINT8 HotPlugPortsStatus; ///< HotPlugPortsStatus - Save Hot-Plug Ports Status + UINT8 FailPortsStatus; ///< FailPortsStatus - Save Failure Ports Status + UINT8 GppPortMinPollingTime; ///< GppPortMinPollingTime - Min. Polling time for Gpp Port Training + BOOLEAN IsCapsuleMode; ///< IsCapsuleMode - Support Capsule Mode in FCH +} FCH_GPP; + + +/// +/// FCH USB3 Debug Sturcture +/// +typedef struct { + BOOLEAN ServiceIntervalEnable; ///< Service Interval Enable + BOOLEAN BandwidthExpandEnable; ///< Bandwidth Expand Enable + BOOLEAN AoacEnable; ///< Aoac Enable + BOOLEAN HwLpmEnable; ///< HwLpm Enable + BOOLEAN DbcEnable; ///< DBC Enable + BOOLEAN MiscPlusEnable; ///< Misc Plus Enable + BOOLEAN EcoFixEnable; ///< Eco Fix Enable + BOOLEAN SsifEnable; ///< SSIF Enable + BOOLEAN U2ifEnable; ///< U2IF Enable + BOOLEAN FseEnable; ///< FSE Enable + BOOLEAN XhcPmeEnable; ///< Xhc Pme Enable +} USB3_DEBUG; + +/// +/// FCH IoMux Sturcture +/// +typedef struct { + UINT8 CbsDbgFchSmbusI2c2Egpio; ///< SMBUS/I2C_2/EGPIO_113_114 + UINT8 CbsDbgFchAsfI2c3Egpio; ///< ASF/I2C_3/EGPIO_019_020 +} FCH_IOMUX; + +/// +/// FCH USB sturcture +/// +typedef struct { + BOOLEAN Ohci1Enable; ///< OHCI1 controller enable + BOOLEAN Ohci2Enable; ///< OHCI2 controller enable + BOOLEAN Ohci3Enable; ///< OHCI3 controller enable + BOOLEAN Ohci4Enable; ///< OHCI4 controller enable + BOOLEAN Ehci1Enable; ///< EHCI1 controller enable + BOOLEAN Ehci2Enable; ///< EHCI2 controller enable + BOOLEAN Ehci3Enable; ///< EHCI3 controller enable + BOOLEAN Xhci0Enable; ///< XHCI0 controller enable + BOOLEAN Xhci1Enable; ///< XHCI1 controller enable + BOOLEAN UsbMsiEnable; ///< USB MSI capability + UINT32 OhciSsid; ///< OHCI SSID + UINT32 Ohci4Ssid; ///< OHCI 4 SSID + UINT32 EhciSsid; ///< EHCI SSID + UINT32 XhciSsid; ///< XHCI SSID + BOOLEAN UsbPhyPowerDown; ///< USB PHY Power Down - 0:disable, 1:enable + UINT32 UserDefineXhciRomAddr; ///< XHCI ROM address define by platform BIOS + UINT8 Ehci1Phy[5]; ///< EHCI1 USB PHY Driving Strength value table + UINT8 Ehci2Phy[5]; ///< EHCI2 USB PHY Driving Strength value table + UINT8 Ehci3Phy[4]; ///< EHCI3 USB PHY Driving Strength value table + UINT8 Xhci20Phy[4]; ///< XHCI USB 2.0 PHY Driving Strength value table + UINT8 Ehci1DebugPortSel; ///< DebugPortSel for Ehci1 Hub + /// @li <b>000</b> - Disable + /// @li <b>001</b> - HubDownStreamPort0 + /// @li <b>010</b> - HubDownStreamPort1 + /// @li <b>011</b> - HubDownStreamPort2 + /// @li <b>100</b> - HubDownStreamPort3 + UINT8 Ehci2DebugPortSel; ///< DebugPortSel for Ehci2 Hub + /// @li <b>000</b> - Disable + /// @li <b>001</b> - HubDownStreamPort0 + /// @li <b>010</b> - HubDownStreamPort1 + /// @li <b>011</b> - HubDownStreamPort2 + /// @li <b>100</b> - HubDownStreamPort3 + UINT8 Ehci3DebugPortSel; ///< DebugPortSel for Ehci3 Hub + /// @li <b>000</b> - Disable + /// @li <b>001</b> - HubDownStreamPort0 + /// @li <b>010</b> - HubDownStreamPort1 + /// @li <b>011</b> - HubDownStreamPort2 + /// @li <b>100</b> - HubDownStreamPort3 + UINT8 Ehci1NPort; ///< N_Port for Ehci1, 2 to 4 + UINT8 Ehci2NPort; ///< N_Port for Ehci2, 2 to 4 + USB3_DEBUG Usb3Debug; ///< Usb3 Debug Options + BOOLEAN EhciSimpleDebugPort; ///< Ehci Simple Debug Port + BOOLEAN UsbBatteryChargeEnable; ///< USB Battery Charge Enable + BOOLEAN ReduceUSB3PortToLastTwo; ///< Reduce USB3.0 ports to last 2 + UINT8 USB30PortInit; ///< USB 3.0 Port Init +} FCH_USB; + + +/// Private: FCH_DATA_BLOCK_RESET +typedef struct _FCH_RESET_DATA_BLOCK { + AMD_CONFIG_PARAMS *StdHeader; ///< Header structure + FCH_RESET_INTERFACE FchReset; ///< Reset interface + + UINT8 FastSpeed; ///< SPI FastSpeed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz + UINT8 WriteSpeed; ///< SPI Write Speed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz + UINT8 Mode; ///< SPI Mode + /// @li <b>101</b> - Qual-io 1-4-4 + /// @li <b>100</b> - Dual-io 1-2-2 + /// @li <b>011</b> - Qual-io 1-1-4 + /// @li <b>010</b> - Dual-io 1-1-2 + /// @li <b>111</b> - FastRead + /// @li <b>110</b> - Normal + /// + UINT8 AutoMode; ///< SPI Auto Mode - 0:disable, 1:enable + UINT8 BurstWrite; ///< SPI Burst Write - 0:disable, 1:enable + BOOLEAN Sata6AhciCap; ///< SATA 6 AHCI Capability - TRUE:enable, FALSE:disable + UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable + BOOLEAN EcKbd; ///< EC KBD - 0:disable, 1:enable + BOOLEAN LegacyFree; ///< Legacy Free - 0:disable, 1:enable + BOOLEAN SataSetMaxGen2; ///< SATA enable maximum GEN2 + UINT8 SataClkMode; ///< SATA reference clock selector and divider + UINT8 SataModeReg; ///< Output: SATAConfig PMIO:0xDA + BOOLEAN SataInternal100Spread; ///< SATA internal 100MHz spread ON/OFF + UINT8 SpiSpeed; ///< SPI NormSpeed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz +// UINT32 SPI100_RX_Timing_Config_Register_38; ///< SPI100_RX_Timing_Config_Register_38 +// UINT16 SPI100_RX_Timing_Config_Register_3C; ///< SPI100_RX_Timing_Config_Register_3C +// UINT8 SpiProtectEn0_1d_34; /// + UINT8 SPI100_Enable; /// + BOOLEAN EcChannel0; ///< Enable EC channel 0 + FCH_GPP Gpp; ///< GPP subsystem + FCH_SPI Spi; ///< SPI subsystem + BOOLEAN QeEnabled; /// Quad Mode Enabled + BOOLEAN FchOscout1ClkContinous; ///< FCH OSCOUT1_CLK Continous + UINT8 LpcClockDriveStrength; ///< Lpc Clock Drive Strength + const VOID* EarlyOemGpioTable; /// Pointer of Early OEM GPIO table +// VOID* OemSpiDeviceTable; /// Pointer of OEM Spi Device table +} FCH_RESET_DATA_BLOCK; + + +/// Private: FCH_DATA_BLOCK +typedef struct _FCH_DATA_BLOCK { + AMD_CONFIG_PARAMS *StdHeader; ///< Header structure + FCH_RUNTIME FchRunTime; ///< FCH Run Time Parameters + + FCH_ACPI HwAcpi; ///< ACPI structure + FCH_AB Ab; ///< AB structure + FCH_GPP Gpp; ///< GPP structure + FCH_USB Usb; ///< USB structure + FCH_SATA Sata; ///< SATA structure + FCH_SMBUS Smbus; ///< SMBus structure + FCH_IDE Ide; ///< IDE structure + FCH_AZALIA Azalia; ///< Azalia structure + FCH_SPI Spi; ///< SPI structure + FCH_PCIB Pcib; ///< PCIB structure + FCH_GEC Gec; ///< GEC structure + FCH_SD Sd; ///< SD structure + FCH_HWM Hwm; ///< Hardware Moniter structure + FCH_IR Ir; ///< IR structure + FCH_HPET Hpet; ///< HPET structure + FCH_GCPU Gcpu; ///< GCPU structure + FCH_IMC Imc; ///< IMC structure + FCH_MISC Misc; ///< MISC structure + FCH_IOMUX IoMux; ///< MISC structure + VOID* PostOemGpioTable; /// Pointer of Post OEM GPIO table +} FCH_DATA_BLOCK; + +#pragma pack (pop) + +#endif diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h new file mode 100644 index 0000000000..d0063a4836 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h @@ -0,0 +1,421 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH routine definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#ifndef _FCH_DEF_H_ +#define _FCH_DEF_H_ + + +UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr); +VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr); +VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); +VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); +VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl); +VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); +VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader); +VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader); +UINT8 ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader); +UINT8 ReadFchChipsetRevision (IN AMD_CONFIG_PARAMS *StdHeader); + +/// +/// Fch Ab Routines +/// +/// Pei Phase +/// +VOID FchInitResetAb (IN VOID* FchDataPtr); +VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvAb (IN VOID* FchDataPtr); +VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr); +VOID FchInitMidAb (IN VOID* FchDataPtr); +VOID FchInitLateAb (IN VOID* FchDataPtr); +/// +/// Other Public Routines +/// +VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr); +BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchAbLateProgram (IN VOID* FchDataPtr); + +/// +/// Fch Pcie Routines +/// +/// +/// Dxe Phase +/// +VOID ProgramPcieNativeMode (IN VOID* FchDataPtr); + +/// +/// Fch Gpp Routines +/// + +/// +/// Common Gpp Routines +/// +VOID FchGppDynamicPowerSaving (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader); + +/// +/// Fch Azalia Routines +/// +/// Pei Phase +/// +VOID FchInitResetAzalia (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvAzalia (IN VOID *FchDataPtr); +VOID FchInitMidAzalia (IN VOID *FchDataPtr); +VOID FchInitLateAzalia (IN VOID *FchDataPtr); + + +/// +/// Fch HwAcpi Routines +/// +/// Pei Phase +/// +VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr); +VOID FchInitResetHwAcpi (IN VOID *FchDataPtr); +VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr); +VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr); +VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr); +VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr); +VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr); +VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr); +VOID FchInitMidHwAcpi (IN VOID *FchDataPtr); +VOID FchInitLateHwAcpi (IN VOID *FchDataPtr); + +/// +/// Other Public Routines +/// +VOID HpetInit (IN VOID *FchDataPtr); +VOID MtC1eEnable (IN VOID *FchDataPtr); +VOID GcpuRelatedSetting (IN VOID *FchDataPtr); +VOID StressResetModeLate (IN VOID *FchDataPtr); + +/// +/// Fch Hwm Routines +/// +/// Pei Phase +/// +VOID FchInitResetHwm (IN VOID* FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvHwm (IN VOID* FchDataPtr); +VOID FchInitMidHwm (IN VOID* FchDataPtr); +VOID FchInitLateHwm (IN VOID* FchDataPtr); +/// +/// Other Public Routines +/// +VOID HwmInitRegister (IN VOID* FchDataPtr); +VOID FchECfancontrolservice (IN VOID* FchDataPtr); + + +/// +/// Fch Imc Routines +/// +/// Pei Phase +/// +VOID FchInitResetImc (IN VOID *FchDataPtr); +VOID FchInitResetEc (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvImc (IN VOID *FchDataPtr); +VOID FchInitMidImc (IN VOID *FchDataPtr); +VOID FchInitLateImc (IN VOID *FchDataPtr); +VOID FchInitEnvEc (IN VOID *FchDataPtr); +VOID FchInitMidEc (IN VOID *FchDataPtr); +VOID FchInitLateEc (IN VOID *FchDataPtr); +/// +/// Other Public Routines +/// +VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader); +VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader); + +VOID ImcSleep (IN VOID *FchDataPtr); +VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr); +VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr); +VOID ImcWakeup (IN VOID *FchDataPtr); +VOID ImcIdle (IN VOID *FchDataPtr); +BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr); +VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr); +VOID ImcCrashReset (IN VOID *FchDataPtr); +VOID SoftwareDisableImc (IN VOID *FchDataPtr); + + +/// +/// Fch Ir Routines +/// +/// Dxe Phase +/// +VOID FchInitEnvIr (IN VOID* FchDataPtr); +VOID FchInitMidIr (IN VOID* FchDataPtr); +VOID FchInitLateIr (IN VOID* FchDataPtr); + +/// +/// Fch SATA Routines +/// +/// Pei Phase +/// +VOID FchInitResetSata (IN VOID *FchDataPtr); +VOID FchInitResetSataProgram (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitMidSata (IN VOID *FchDataPtr); +VOID FchInitEnvSata (IN VOID *FchDataPtr); +VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr); +VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr); +VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr); + +VOID FchInitLateSata (IN VOID *FchDataPtr); +VOID FchInitEnvSataIde (IN VOID *FchDataPtr); +VOID FchInitMidSataIde (IN VOID *FchDataPtr); +VOID FchInitLateSataIde (IN VOID *FchDataPtr); +VOID FchInitEnvSataAhci (IN VOID *FchDataPtr); +VOID FchInitMidSataAhci (IN VOID *FchDataPtr); +VOID FchInitLateSataAhci (IN VOID *FchDataPtr); +VOID FchInitEnvSataRaid (IN VOID *FchDataPtr); +VOID FchInitMidSataRaid (IN VOID *FchDataPtr); +VOID FchInitLateSataRaid (IN VOID *FchDataPtr); +VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr); +VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr); +VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr); + +VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader); +VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr); +VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader); +VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader); +VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr); +VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5); +VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5); +VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr); +VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr); +VOID SataBar5RegSet (IN VOID *FchDataPtr); +VOID SataSetPortGenMode (IN VOID *FchDataPtr); +VOID FchSataSetPortGenMode (IN VOID *FchDataPtr); +VOID FchProgramSataPhy (IN VOID *FchDataPtr); +VOID FchInitEnvSataRaidProgram (IN VOID *FchDataPtr); + +/// +/// FCH USB Controller Public Function +/// +/// Pei Phase +/// +VOID FchInitResetUsb (IN VOID *FchDataPtr); +VOID FchInitResetEhci (IN VOID *FchDataPtr); +VOID FchInitResetXhci (IN VOID *FchDataPtr); +VOID FchInitResetXhciProgram (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvUsb (IN VOID *FchDataPtr); +VOID FchInitMidUsb (IN VOID *FchDataPtr); +VOID FchInitLateUsb (IN VOID *FchDataPtr); +VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr); +VOID FchInitMidUsbEhci (IN VOID *FchDataPtr); +VOID FchInitLateUsbEhci (IN VOID *FchDataPtr); +VOID FchEhciDebugPortService (IN VOID *FchDataPtr); +VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr); +VOID FchInitMidUsbXhci (IN VOID *FchDataPtr); +VOID FchInitLateUsbXhci (IN VOID *FchDataPtr); +VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr); +/// +/// Other Public Routines +/// +VOID FchSetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr); +VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr); +VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr); +VOID FchXhciInitIndirectReg (IN FCH_DATA_BLOCK* FchDataPtr); +VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr); +VOID FchXhciPowerSavingProgram (IN FCH_DATA_BLOCK* FchDataPtr); +VOID FchXhciUsbPhyCalibrated (IN FCH_DATA_BLOCK* FchDataPtr); +UINT8 FchUsbCommonPhyCalibration (IN FCH_DATA_BLOCK* FchDataPtr); + +/// +/// Fch Sd Routines +/// +VOID FchInitEnvSd (IN VOID *FchDataPtr); +VOID FchInitMidSd (IN VOID *FchDataPtr); +VOID FchInitLateSd (IN VOID *FchDataPtr); + +/// +/// Other Public Routines +/// + +VOID FchInitEnvSdProgram (IN VOID *FchDataPtr); + +/// +/// Fch Spi Routines +/// +/// Pei Phase +/// +VOID FchInitResetSpi (IN VOID *FchDataPtr); +VOID FchInitResetLpc (IN VOID *FchDataPtr); +VOID FchInitResetLpcProgram (IN VOID *FchDataPtr); +/// +/// Dxe Phase +/// +VOID FchInitEnvSpi (IN VOID *FchDataPtr); +VOID FchInitMidSpi (IN VOID *FchDataPtr); +VOID FchInitLateSpi (IN VOID *FchDataPtr); +VOID FchInitEnvLpc (IN VOID *FchDataPtr); +VOID FchInitMidLpc (IN VOID *FchDataPtr); +VOID FchInitLateLpc (IN VOID *FchDataPtr); +VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr); +/// +/// Other Public Routines +/// +VOID FchSpiUnlock (IN VOID *FchDataPtr); +VOID FchSpiLock (IN VOID *FchDataPtr); + +/*--------------------------- Documentation Pages ---------------------------*/ +VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader); +VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader); +VOID FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader); +VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader); +VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader); +VOID GetEfuseStatus (IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID TurnOffCG2 (OUT VOID); +VOID BackUpCG2 (OUT VOID); +VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length); +VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwXhci0IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID RwXhci1IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadXhci0Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID ReadXhci1Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID AcLossControl (IN UINT8 AcLossControlValue); +VOID FchVgaInit (OUT VOID); +VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr); +VOID ValidateFchVariant (IN VOID *FchDataPtr); +VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader); +VOID ClearAllSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader); +BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr); +VOID SbSleepTrapControl (IN BOOLEAN SleepTrap); + +AGESA_STATUS +FchSpiTransfer ( + IN UINT8 PrefixCode, + IN UINT8 Opcode, + IN OUT UINT8 *DataPtr, + IN UINT8 *AddressPtr, + IN UINT8 Length, + IN BOOLEAN WriteFlag, + IN BOOLEAN AddressFlag, + IN BOOLEAN DataFlag, + IN BOOLEAN FinishedFlag + ); + +BOOLEAN +FchConfigureSpiDeviceDummyCycle ( + IN UINT32 DeviceID, + IN UINT8 SpiMode + ); + +UINT32 +FchReadSpiId ( + IN BOOLEAN Flag + ); + +BOOLEAN +FchPlatformSpiQe ( + IN VOID *FchDataPtr + ); + +FCH_DATA_BLOCK* +FchInitLoadDataBlock ( + IN FCH_INTERFACE *FchInterface, + IN AMD_CONFIG_PARAMS *StdHeader + ); + +FCH_DATA_BLOCK* +FchInitEnvCreatePrivateData ( + IN AMD_ENV_PARAMS *EnvParams + ); + +FCH_RESET_DATA_BLOCK* +FchInitResetLoadPrivateDefault ( + IN AMD_RESET_PARAMS *ResetParams + ); + +VOID +RetrieveDataBlockFromInitReset ( + IN FCH_DATA_BLOCK *FchParams + ); + + +#endif + diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchLib.c new file mode 100644 index 0000000000..dfdab59f08 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchLib.c @@ -0,0 +1,672 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH IO access common routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_COMMON_FCHLIB_FILECODE + +/**< FchStall - Reserved */ +VOID +FchStall ( + IN UINT32 uSec, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 timerAddr; + UINT32 startTime; + UINT32 elapsedTime; + + LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader); + if ( timerAddr == 0 ) { + uSec = uSec / 2; + while ( uSec != 0 ) { + LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8 *) (&startTime), StdHeader); + uSec--; + } + } else { + LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader); + for ( ;; ) { + LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader); + if ( elapsedTime < startTime ) { + elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime; + } else { + elapsedTime = elapsedTime - startTime; + } + if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) { + break; + } + } + } +} + +/**< cimFchStall - Reserved */ +VOID +CimFchStall ( + IN UINT32 uSec, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT16 timerAddr; + UINT32 startTime; + UINT32 elapsedTime; + + LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader); + if ( timerAddr == 0 ) { + uSec = uSec / 2; + while ( uSec != 0 ) { + LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8*)&elapsedTime, StdHeader); + uSec--; + } + } else { + LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader); + for ( ;; ) { + LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader); + if ( elapsedTime < startTime ) { + elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime; + } else { + elapsedTime = elapsedTime - startTime; + } + if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) { + break; + } + } + } +} + +/**< FchReset - Reserved */ +VOID +FchPciReset ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 PciRstValue; + + PciRstValue = 0x06; + LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &PciRstValue, StdHeader); +} + +/**< outPort80 - Reserved */ +VOID +OutPort80 ( + IN UINT32 pcode, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdIoWrite (AccessWidth8, FCHOEM_OUTPUT_DEBUG_PORT, &pcode, StdHeader); + return; +} + +/**< outPort1080 - Reserved */ +VOID +OutPort1080 ( + IN UINT32 pcode, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdIoWrite (AccessWidth32, 0x1080, &pcode, StdHeader); + return; +} + +/**< FchCopyMem - Reserved */ +VOID +FchCopyMem ( + IN VOID* pDest, + IN VOID* pSource, + IN UINTN Length + ) +{ + UINTN i; + UINT8 *Ptr; + UINT8 *Source; + Ptr = (UINT8*)pDest; + Source = (UINT8*)pSource; + for (i = 0; i < Length; i++) { + *Ptr = *Source; + Source++; + Ptr++; + } +} + +/** GetRomSigPtr - Reserved **/ +VOID* +GetRomSigPtr ( + IN UINTN *RomSigPtr, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RomPtr; + UINT32 RomSig; + UINT16 MswAddr; + + *RomSigPtr = 0; + MswAddr = 0xFF00; + do { + RomPtr = (MswAddr << 16) + FCH_ROMSIG_BASE_IO; + LibAmdMemRead (AccessWidth32, (UINT64) RomPtr, &RomSig, StdHeader); + if (RomSig == FCH_ROMSIG_SIGNATURE) { + *RomSigPtr = RomPtr; + break; + } + MswAddr >>= 1; + MswAddr |= BIT15; + } while (MswAddr != 0xFFF8); + return RomSigPtr; +} + +/** RwXhciIndReg - Reserved **/ +VOID +RwXhciIndReg ( + IN UINT32 Index, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RevReg; + PCI_ADDR PciAddress; + + PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48; + LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); + PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C; + RevReg = ~AndMask; + LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); + + PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48; + LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); + PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C; + RevReg = ~AndMask; + LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); +} + +/** RwXhci0IndReg - Reserved **/ +VOID +RwXhci0IndReg ( + IN UINT32 Index, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RevReg; + PCI_ADDR PciAddress; + + PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48; + LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); + PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C; + RevReg = ~AndMask; + LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); +} + +/** RwXhci1IndReg - Reserved **/ +VOID +RwXhci1IndReg ( + IN UINT32 Index, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RevReg; + PCI_ADDR PciAddress; + + PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48; + LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader); + PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C; + RevReg = ~AndMask; + LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader); +} + +/** ReadXhci0Phy - Reserved **/ +VOID +ReadXhci0Phy ( + IN UINT32 Port, + IN UINT32 Address, + IN UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RegIndex; + UINT32 RegValue; + PCI_ADDR PciAddress; + + RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + Address, StdHeader); + + RegIndex = FCH_XHCI_IND60_REG04; + PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48; + LibAmdPciWrite (AccessWidth32, PciAddress, &RegIndex, StdHeader); + PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C; + LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); + + (*Value) = ( RegValue >> (Port * 8)) & 0x000000FF; +} + +/** ReadXhci1Phy - Reserved **/ +VOID +ReadXhci1Phy ( + IN UINT32 Port, + IN UINT32 Address, + IN UINT32 *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 RegIndex; + UINT32 RegValue; + PCI_ADDR PciAddress; + + RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + Address, StdHeader); + + RegIndex = FCH_XHCI_IND60_REG04; + PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48; + LibAmdPciWrite (AccessWidth32, PciAddress, &RegIndex, StdHeader); + PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C; + LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader); + + (*Value) = ( RegValue >> (Port * 8)) & 0x000000FF; +} + +/** AcLossControl - Reserved **/ +VOID +AcLossControl ( + IN UINT8 AcLossControlValue + ) +{ + AcLossControlValue &= 0x03; + AcLossControlValue |= BIT2; + RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5B, AccessWidth8, 0xF0, AcLossControlValue); +} + +/** RecordFchConfigPtr - Reserved **/ +VOID +RecordFchConfigPtr ( + IN UINT32 FchConfigPtr + ) +{ + RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x08, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 0) & 0xFF) ); + RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x09, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 8) & 0xFF) ); + RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0A, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 16) & 0xFF) ); + RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0B, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 24) & 0xFF) ); +} + +/** ReadAlink - Reserved **/ +UINT32 +ReadAlink ( + IN UINT32 Index, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Data; + LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); + LibAmdIoRead (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader); + //Clear Index + Index = 0; + LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); + return Data; +} + +/** WriteAlink - Reserved **/ +VOID +WriteAlink ( + IN UINT32 Index, + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); + LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader); + //Clear Index + Index = 0; + LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader); +} + +/** RwAlink - Reserved **/ +VOID +RwAlink ( + IN UINT32 Index, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 AccessType; + + AccessType = Index & 0xE0000000; + if (AccessType == (AXINDC << 29)) { + WriteAlink ((FCH_AX_INDXC_REG30 | AccessType), Index & 0x1FFFFFFF, StdHeader); + Index = FCH_AX_DATAC_REG34 | AccessType; + } else if (AccessType == (AXINDP << 29)) { + WriteAlink ((FCH_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF, StdHeader); + Index = FCH_AX_DATAP_REG3C | AccessType; + } + WriteAlink (Index, (ReadAlink (Index, StdHeader) & AndMask) | OrMask, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * @param[in] StdHeader + * + */ +VOID +ReadPmio ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + OpFlag = 1 << (OpFlag - 1); + for (i = 0; i < OpFlag; i++) { + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader); + Address++; + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * @param[in] StdHeader + * + */ +VOID +WritePmio ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + OpFlag = 1 << (OpFlag - 1); + for (i = 0; i < OpFlag; i++) { + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader); + Address++; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * RwPmio - Read/Write PMIO + * + * + * + * @param[in] Address - PMIO Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * @param[in] StdHeader + * + */ +VOID +RwPmio ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Result; + + ReadPmio (Address, OpFlag, &Result, StdHeader); + Result = (Result & AndMask) | OrMask; + WritePmio (Address, OpFlag, &Result, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * @param[in] StdHeader + * + */ +VOID +ReadPmio2 ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + OpFlag = 1 << (OpFlag - 1); + for ( i = 0; i < OpFlag; i++ ) { + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader); + Address++; + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Write PMIO 2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * @param[in] StdHeader + * + */ +VOID +WritePmio2 ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + OpFlag = 1 << (OpFlag - 1); + + for ( i = 0; i < OpFlag; i++ ) { + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader); + Address++; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * RwPmio2 - Read/Write PMIO2 + * + * + * + * @param[in] Address - PMIO2 Offset value + * @param[in] OpFlag - Access sizes + * @param[in] AndMask - Data And Mask 32 bits + * @param[in] OrMask - Data OR Mask 32 bits + * @param[in] StdHeader + * + */ +VOID +RwPmio2 ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN UINT32 AndMask, + IN UINT32 OrMask, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT32 Result; + + ReadPmio2 (Address, OpFlag, &Result, StdHeader); + Result = (Result & AndMask) | OrMask; + WritePmio2 (Address, OpFlag, &Result, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Read BIOSRAM + * + * + * + * @param[in] Address - BIOSRAM Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Read Data Buffer + * @param[in] StdHeader + * + */ +VOID +ReadBiosram ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + OpFlag = 1 << (OpFlag - 1); + for (i = 0; i < OpFlag; i++) { + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader); + Address++; + LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write BIOSRAM + * + * + * + * @param[in] Address - BIOSRAM Offset value + * @param[in] OpFlag - Access sizes + * @param[in] Value - Write Data Buffer + * @param[in] StdHeader + * + */ +VOID +WriteBiosram ( + IN UINT8 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + + OpFlag = OpFlag & 0x7f; + OpFlag = 1 << (OpFlag - 1); + for (i = 0; i < OpFlag; i++) { + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader); + Address++; + LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Record SMI Status + * + * + * @param[in] StdHeader + * + */ +VOID +RecordSmiStatus ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN Index; + UINT8 SwSmiValue; + + ACPIMMIO8 (0xfed80320) |= 0x01; + for ( Index = 0; Index < 20; Index++ ) { + ACPIMMIO8 (0xfed10020 + Index) = ACPIMMIO8 (0xfed80280 + Index); + } + LibAmdIoRead (AccessWidth8, 0xB0, &SwSmiValue, StdHeader); + ACPIMMIO8 (0xfed10040) = SwSmiValue; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Clear All SMI Status + * + * + * @param[in] StdHeader + * + */ +VOID +ClearAllSmiStatus ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINTN Index; + + for ( Index = 0; Index < 20; Index++ ) { + ACPIMMIO8 (0xfed80280 + Index) |= 0; + } +} diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchPeLib.c new file mode 100644 index 0000000000..171ea0f3d0 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchPeLib.c @@ -0,0 +1,310 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH IO access common routine + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE + +/*----------------------------------------------------------------------------------------*/ +/** + * ProgramPciByteTable - Program PCI register by table (8 bits data) + * + * + * + * @param[in] pPciByteTable - Table data pointer + * @param[in] dwTableSize - Table length + * @param[in] StdHeader + * + */ +VOID +ProgramPciByteTable ( + IN REG8_MASK *pPciByteTable, + IN UINT16 dwTableSize, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 dbBusNo; + UINT8 dbDevFnNo; + UINT8 Or8; + UINT8 Mask8; + PCI_ADDR PciAddress; + + dbBusNo = pPciByteTable->RegIndex; + dbDevFnNo = pPciByteTable->AndMask; + pPciByteTable++; + + for ( i = 1; i < dwTableSize; i++ ) { + if ( (pPciByteTable->RegIndex == 0xFF) && (pPciByteTable->AndMask == 0xFF) && (pPciByteTable->OrMask == 0xFF) ) { + pPciByteTable++; + dbBusNo = pPciByteTable->RegIndex; + dbDevFnNo = pPciByteTable->AndMask; + pPciByteTable++; + i++; + } else { + PciAddress.AddressValue = (dbBusNo << 20) + (dbDevFnNo << 12) + pPciByteTable->RegIndex; + Or8 = pPciByteTable->OrMask; + Mask8 = ~pPciByteTable->AndMask; + LibAmdPciRMW (AccessWidth8, PciAddress, &Or8, &Mask8, StdHeader); + pPciByteTable++; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data) + * + * + * + * @param[in] pAcpiTbl - Table data pointer + * @param[in] StdHeader + * + */ +VOID +ProgramFchAcpiMmioTbl ( + IN ACPI_REG_WRITE *pAcpiTbl, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 i; + UINT8 Or8; + UINT8 Mask8; + UINT32 ddtempVar; + + if (pAcpiTbl != NULL) { + if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataAndMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) { + // Signature Checking + pAcpiTbl++; + for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) { + ddtempVar = ACPI_MMIO_BASE | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg; + Or8 = pAcpiTbl->DataOrMask; + Mask8 = ~pAcpiTbl->DataAndMask; + LibAmdMemRMW (AccessWidth8, (UINT64) ddtempVar, &Or8, &Mask8, StdHeader); + pAcpiTbl++; + } + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data) + * + * + * + * @param[in] pSciMapTbl - Table data pointer + * @param[in] FchResetDataBlock + * + */ +VOID +ProgramFchSciMapTbl ( + IN SCI_MAP_CONTROL *pSciMapTbl, + IN FCH_RESET_DATA_BLOCK *FchResetDataBlock + ) +{ + AMD_CONFIG_PARAMS *StdHeader; + + UINT32 ddtempVar; + StdHeader = FchResetDataBlock->StdHeader; + + if (pSciMapTbl != NULL) { + while (pSciMapTbl->InputPin != 0xFF) { + if ((pSciMapTbl->InputPin >= 0x40) && (pSciMapTbl->InputPin < 0x80) && (pSciMapTbl->GpeMap < 0x20)) { + ddtempVar = ACPI_MMIO_BASE | SMI_BASE | pSciMapTbl->InputPin; + if (((pSciMapTbl->InputPin == FCH_SMI_xHC0Pme) && (FchResetDataBlock->FchReset.Xhci0Enable == 0)) || \ + ((pSciMapTbl->InputPin == FCH_SMI_xHC1Pme) && (FchResetDataBlock->FchReset.Xhci1Enable == 0))) { + } else { + LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pSciMapTbl->GpeMap, StdHeader); + } + } else { + //Assert Warning "SCI map is invalid" + } + pSciMapTbl++; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ProgramFchGpioTbl - Program FCH Gpio table (8 bits data) + * + * + * + * @param[in] pGpioTbl - Table data pointer + * + */ +VOID +ProgramFchGpioTbl ( + IN GPIO_CONTROL *pGpioTbl + ) +{ + if (pGpioTbl != NULL) { + while (pGpioTbl->GpioPin != 0xFF) { + ACPIMMIO8 (ACPI_MMIO_BASE | IOMUX_BASE | pGpioTbl->GpioPin) = (UINT8) (pGpioTbl->PinFunction); + ACPIMMIO8 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + ((UINT32)pGpioTbl->GpioPin << 2) + 2) = (UINT8) (pGpioTbl->CfgByte); + pGpioTbl++; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * ProgramSataPhyTbl - Program FCH Sata Phy table (8 bits data) + * + * + * + * @param[in] pSataPhyTbl - Table data pointer + * @param[in] FchResetDataBlock + * + */ +VOID +ProgramFchSataPhyTbl ( + IN SATA_PHY_CONTROL *pSataPhyTbl, + IN FCH_RESET_DATA_BLOCK *FchResetDataBlock + ) +{ + if (pSataPhyTbl != NULL) { + while (pSataPhyTbl->PhyData != 0xFFFFFFFF) { + //to be implemented + pSataPhyTbl++; + } + } +} + +/** + * GetChipSysMode - Get Chip status + * + * + * @param[in] Value - Return Chip strap status + * StrapStatus [15.0] - Hudson-2 chip Strap Status + * @li <b>0001</b> - Not USED FWH + * @li <b>0002</b> - Not USED LPC ROM + * @li <b>0004</b> - EC enabled + * @li <b>0008</b> - Reserved + * @li <b>0010</b> - Internal Clock mode + * @param[in] StdHeader + * + */ +VOID +GetChipSysMode ( + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), Value, StdHeader); +} + +/** + * IsImcEnabled - Is IMC Enabled + * @retval TRUE for IMC Enabled; FALSE for IMC Disabled + */ +BOOLEAN +IsImcEnabled ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 dbSysConfig; + GetChipSysMode (&dbSysConfig, StdHeader); + if (dbSysConfig & ChipSysEcEnable) { + return TRUE; + } else { + return FALSE; + } +} + + +/** + * GetEfuseStatue - Get Efuse status + * + * + * @param[in] Value - Return Chip strap status + * @param[in] StdHeader + * + */ +VOID +GetEfuseStatus ( + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + UINT8 Or8; + UINT8 Mask8; + + Or8 = BIT5; + Mask8 = BIT5; + LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader); + LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8), Value, StdHeader); + LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8 + 1), Value, StdHeader); + Or8 = 0; + Mask8 = BIT5; + LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * SbSleepTrapControl - SB Sleep Trap Control + * + * + * + * @param[in] SleepTrap - Whether sleep trap is enabled + * + */ +VOID +SbSleepTrapControl ( + IN BOOLEAN SleepTrap + ) +{ + if (SleepTrap) { + ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3); + ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) |= BIT2; + + ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE) &= ~ (BIT5); + ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1); + ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT1; + } else { + ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE) |= BIT5; + ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1); + ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT0; + + ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3); + } +} diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/MemLib.c b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/MemLib.c new file mode 100644 index 0000000000..656f7689bb --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/MemLib.c @@ -0,0 +1,144 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH memory access lib + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#include "FchPlatform.h" +#include "Ids.h" +#define FILECODE PROC_FCH_COMMON_MEMLIB_FILECODE + + +/** + * ReadMem - Read FCH BAR Memory + * + * @param[in] Address - Memory BAR address + * @param[in] OpFlag - Access width + * @param[in] *ValuePtr - In/Out value pointer + * + */ +VOID +ReadMem ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID *ValuePtr + ) +{ + OpFlag = OpFlag & 0x7f; + + switch ( OpFlag ) { + case AccessWidth8: + *((UINT8*)ValuePtr) = *((volatile UINT8*) ((UINTN)Address)); + break; + + case AccessWidth16: + *((UINT16*)ValuePtr) = *((volatile UINT16*) ((UINTN)Address)); + break; + + case AccessWidth32: + *((UINT32*)ValuePtr) = *((volatile UINT32*) ((UINTN)Address)); + break; + + default: + ASSERT (FALSE); + break; + } +} + +/** + * WriteMem - Write FCH BAR Memory + * + * @param[in] Address - Memory BAR address + * @param[in] OpFlag - Access width + * @param[in] *ValuePtr - In/Out Value pointer + * + */ +VOID +WriteMem ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID *ValuePtr + ) +{ + OpFlag = OpFlag & 0x7f; + + switch ( OpFlag ) { + case AccessWidth8 : + *((volatile UINT8*) ((UINTN)Address)) = *((UINT8*)ValuePtr); + break; + + case AccessWidth16: + *((volatile UINT16*) ((UINTN)Address)) = *((UINT16*)ValuePtr); + break; + + case AccessWidth32: + *((volatile UINT32*) ((UINTN)Address)) = *((UINT32*)ValuePtr); + break; + + default: + ASSERT (FALSE); + break; + } +} + +/** + * RwMem - Read & Write FCH BAR Memory + * + * @param[in] Address - Memory BAR address + * @param[in] OpFlag - Access width + * @param[in] Mask - Mask Value of data + * @param[in] Data - Write data + * + */ +VOID +RwMem ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data + ) +{ + UINT32 Result; + + ReadMem (Address, OpFlag, &Result); + Result = (Result & Mask) | Data; + WriteMem (Address, OpFlag, &Result); + ReadMem (Address, OpFlag, &Result); +} + diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/PciLib.c new file mode 100644 index 0000000000..ed8bb81869 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/PciLib.c @@ -0,0 +1,93 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH PCI access lib + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#include "FchPlatform.h" +#define FILECODE PROC_FCH_COMMON_PCILIB_FILECODE + +VOID +ReadPci ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID* Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + + PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF); + LibAmdPciRead ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader); +} + + +VOID +WritePci ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN VOID *Value, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + + PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF); + LibAmdPciWrite ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader); +} + + +VOID +RwPci ( + IN UINT32 Address, + IN UINT8 OpFlag, + IN UINT32 Mask, + IN UINT32 Data, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCI_ADDR PciAddress; + UINT32 rMask; + + PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF); + rMask = ~Mask; + LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader); +} + + diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h new file mode 100644 index 0000000000..7576cad4dd --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h @@ -0,0 +1,2603 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH registers definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 314274 $ @e \$Date: 2015-03-08 03:53:49 -0500 (Sun, 08 Mar 2015) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#define FCH_REVISION "0.0.5.0" +#define FCH_ID "FCH_A05" +#define FCH_VERSION 0x0000 + +/** + * @page fchinitguide FCH implement phase in AGESA + * + * FCH provides below access to supported FCH service functions + * and data. + * - @subpage fchreset "FCH_INIT_RESET" + * - @subpage fchenv "FCH_INIT_ENV" + * - @subpage fchmid "FCH_INIT_MID" + * - @subpage fchlate "FCH_INIT_LATE" + * - @subpage fchs3early "FCH_INIT_S3_EARLY_RESTORE" + * - @subpage fchs3late "FCH_INIT_S3_LATE_RESTORE" + * - @subpage fchsmm "FCH_SMM_SERVICE" + * - @subpage fchsmmacpion "FCH_SMM_ACPION" + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchreset FCH_INIT_RESET + * @section FCH_INIT_RESET Interface Call + * @par + * Initialize structure referenced by FCH_RESET_DATA_BLOCK to default recommended value. + * @subsection FCH_INIT_RESET_CallIn Call Prototype + * @par + * AGESA_STATUS FchInitReset (IN AMD_RESET_PARAMS *ResetParams); + * @subsection FCH_INIT_RESET_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_INIT_RESET_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus0BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus1BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSioPmeBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgWatchDogTimerBase </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgGecShadowRomBase </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1EvtBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1CntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmTmrBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgCpuControlBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiGpe0BlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmiCmdPortAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmaCntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * </TABLE> + * + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchenv FCH_INIT_ENV + * @section FCH_INIT_ENV Interface Call + * @par + * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value. + * @subsection FCH_INIT_ENV_CallIn Call Prototype + * @par + * AGESA_STATUS FchInitEnv (IN AMD_ENV_PARAMS *EnvParams); + * @subsection FCH_INIT_ENV_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_INIT_ENV_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * </TABLE> + * + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchmid FCH_INIT_MID + * @section FCH_INIT_MID Interface Call + * @par + * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value. + * @subsection FCH_INIT_MID_CallIn Call Prototype + * @par + * AGESA_STATUS FchInitMid (IN AMD_MID_PARAMS *MidParams); + * @subsection FCH_INIT_MID_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_INIT_MID_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * </TABLE> + * + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchlate FCH_INIT_LATE + * @section FCH_INIT_LATE Interface Call + * @par + * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value. + * @subsection FCH_INIT_LATE_CallIn Call Prototype + * @par + * AGESA_STATUS FchInitLate (IN FCH_DATA_BLOCK *LateParams); + * @subsection FCH_INIT_LATE_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_INIT_LATE_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * </TABLE> + * + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchs3early FCH_INIT_S3_EARLY_RESTORE + * @section FCH_INIT_S3_EARLY_RESTORE Interface Call + * @par + * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value. + * @subsection FCH_INIT_S3_EARLY_RESTORE_CallIn Call Prototype + * @par + * VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); + * @subsection FCH_INIT_S3_EARLY_RESTORE_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_INIT_S3_EARLY_RESTORE_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * </TABLE> + * + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchs3late FCH_INIT_S3_LATE_RESTORE + * @section FCH_INIT_S3_LATE_RESTORE Interface Call + * @par + * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value. + * @subsection FCH_INIT_S3_LATE_RESTORE_CallIn Call Prototype + * @par + * VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); + * @subsection FCH_INIT_S3_LATE_RESTORE_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_INIT_S3_LATE_RESTORE_Config Prepare for Configuration Data. + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR> + * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR> + * </TABLE> + * + */ + +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchsmm FCH_SMM_SERVICE + * @section FCH_SMM_SERVICE Interface Call + * Initialize structure referenced by FCHCFG to default recommended value. + * @subsection FCH_SMM_SERVICE_CallIn Call Prototype + * @par + * FchSmmService ((FCHCFG*)pConfig) (Followed PH Interface) + * @subsection FCH_SMM_SERVICE_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_SMM_SERVICE --> 0x00010060 </TD></TR> + * </TABLE> + * @subsection FCH_SMM_SERVICE_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_SMM_SERVICE_Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define FCH_SMM_SERVICE 0x00010060ul +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page fchsmmacpion FCH_SMM_ACPION + * @section FCH_SMM_ACPION Interface Call + * Initialize structure referenced by FCHCFG to default recommended value. + * @subsection FCH_SMM_ACPION_CallIn Call Prototype + * @par + * FchSmmAcpiOn ((FCHCFG*)pConfig) (Followed PH Interface) + * @subsection FCH_SMM_ACPION_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> FCH_SMM_ACPION --> 0x00010061 </TD></TR> + * </TABLE> + * @subsection FCH_SMM_ACPION_CallOut Prepare for Callout + * @par + * Not Applicable (Not necessary for the current implementation) + * @subsection FCH_SMM_ACPION_Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define FCH_SMM_ACPION 0x00010061ul + +#ifndef OEM_CALLBACK_BASE + #define OEM_CALLBACK_BASE 0x00010100ul +#endif + +//0x00 - 0x0F callback functions are reserved for bootblock +#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10 +#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT + * @section CB_SBGPP_RESET_ASSERT Interface Call + * Initialize structure referenced by FCHCFG to default recommended value. + * @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT --> 0x00010130 </TD></TR> + * </TABLE> + * @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define CB_SBGPP_RESET_ASSERT OEM_CALLBACK_BASE + 0x30 +/*--------------------------- Documentation Pages ---------------------------*/ +/** + * @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT + * @section CB_SBGPP_RESET_DEASSERT Interface Call + * Initialize structure referenced by FCHCFG to default recommended value. + * @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID + * @par + * <TABLE border="0"> + * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT --> 0x00010131 </TD></TR> + * </TABLE> + * @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data. + * @par + * Not necessary on current implementation + * + */ +#define CB_SBGPP_RESET_DEASSERT OEM_CALLBACK_BASE + 0x31 + +#define CFG_ADDR_PORT 0xCF8 +#define CFG_DATA_PORT 0xCFC + +#define ALINK_ACCESS_INDEX 0x0CD8 +#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4 + +/*------------------------------------------------------------------ +; I/O Base Address - Should be set by host BIOS +;------------------------------------------------------------------ */ +#define DELAY_PORT 0x0E0 + +#define FCH_8259_CONTROL_REG_MASTER 0x20 +#define FCH_8259_MASK_REG_MASTER 0x21 + +/*------------------------------------------------------------------ +; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display +;------------------------------------------------------------------ */ +// ASIC VendorID and DeviceIDs +#define ATI_VID 0x1002 +#define AMD_FCH_VID 0x1022 +#define FCH_DEVICE_ID 0x780B +#define FCH_SATA_VID AMD_FCH_VID // Dev 17 Func 0 +#define FCH_SATA_DID 0x7800 +#define FCH_SATA_AHCI_DID 0x7801 +#define FCH_SATA_RAID_DID 0x7802 +#define FCH_SATA_RAID5_DID 0x7803 +#define FCH_SATA_AMDAHCI_DID 0x7804 +#define FCH_SATA_RAID_DOTHILL_DID 0x7805 +#define FCH_SATA_RAID5_DOTHILL_DID 0x780A +#define FCH_USB_OHCI_VID AMD_FCH_VID // Dev 18 Func 0, Dev 19 Func 0 +#define FCH_USB_OHCI_DID 0x7807 +#define FCH_USB_EHCI_VID AMD_FCH_VID // Dev 18 Func 2, Dev 19 Func 2 +#define FCH_USB_EHCI_DID 0x7808 +#define FCH_USB_XHCI_VID AMD_FCH_VID // Dev 10 Func 0, Dev 10 Func 1 +#define FCH_USB_XHCI_DID 0x7812 +#define FCH_USB_XHCI_DID_BOLTON 0x7814 +#define FCH_USB_XHCI_DID_KABINI 0x7814 +#define FCH_SMBUS_VID AMD_FCH_VID // Dev 20 Func 0 +#define FCH_SMBUS_DID 0x780B +#define FCH_IDE_VID AMD_FCH_VID // Dev 20 Func 1 +#define FCH_IDE_DID 0x780C +#define FCH_AZALIA_VID AMD_FCH_VID // Dev 20 Func 2 +#define FCH_AZALIA_DID 0x157a +#define FCH_LPC_VID AMD_FCH_VID // Dev 20 Func 3 +#define FCH_LPC_DID 0x780E +#define FCH_PCIB_VID AMD_FCH_VID // Dev 20 Func 4 +#define FCH_PCIB_DID 0x780F +#define FCH_USB_OHCIF_VID AMD_FCH_VID // dev 20 Func 5 +#define FCH_USB_OHCIF_DID 0x7809 +#define FCH_NIC_VID 0x14E4 // Dev 20 Func 6 +#define FCH_NIC_DID 0x1699 +#define FCH_SD_VID AMD_FCH_VID // Dev 20 Func 7 +#define FCH_SD_DID 0x7806 + +//FCH Variant +#define FCH_Variant_EFUSE_LOCATION 0x1E // EFUSE bit 240-247 + +#define FCH_M2 0x01 +#define FCH_M3 0x03 +#define FCH_M3T 0x07 +#define FCH_D2 0x0F +#define FCH_D3 0x1F +#define FCH_D4 0x3F +#define FCH_BOLTON 0x15 +#define FCH_YANGTZE 0x39 +#define FCH_YANGTZEA1 0x3A +#define FCH_AVALONA0 0x41 +#define FCH_AVALONA1 0x42 +//Misc +#define R_FCH_ACPI_PM1_STATUS 0x00 +#define R_FCH_ACPI_PM1_ENABLE 0x02 +#define R_FCH_ACPI_PM_CONTROL 0x04 +#define R_FCH_ACPI_EVENT_STATUS 0x20 +#define R_FCH_ACPI_EVENT_ENABLE 0x24 +#define R_FCH_PM_ACPI_PMA_CNT_BLK_LO 0x2C + +// ACPI Sleep Type +#define ACPI_SLPTYP_S0 0 +#define ACPI_SLPTYP_S1 1 +#define ACPI_SLPTYP_S3 3 +#define ACPI_SLPTYP_S4 4 +#define ACPI_SLPTYP_S5 5 + +//#define SATA_BUS_DEV_FUN_FPGA 0x228 +#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0) +#define FCH_SATA1_BUS 0 +#define FCH_SATA1_DEV 17 +#define FCH_SATA1_FUNC 0 + +#define FC_BUS_DEV_FUN ((0x11 << 3) + 1) +#define FCH_XHCI_BUS 0 +#define FCH_XHCI_DEV 16 +#define FCH_XHCI_FUNC 0 +#define USB_XHCI_BUS_DEV_FUN ((FCH_XHCI_DEV << 3) + FCH_XHCI_FUNC) +#define FCH_XHCI1_BUS 0 +#define FCH_XHCI1_DEV 16 +#define FCH_XHCI1_FUNC 1 +#define USB_XHCI1_BUS_DEV_FUN ((FCH_XHCI1_DEV << 3) + FCH_XHCI1_FUNC) +#define USB1_OHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-4 +#define FCH_OHCI1_BUS 0 +#define FCH_OHCI1_DEV 18 +#define FCH_OHCI1_FUNC 0 +#define USB2_OHCI_BUS_DEV_FUN ((0x13 << 3) + 0) // PORT 5-9 +#define FCH_OHCI2_BUS 0 +#define FCH_OHCI2_DEV 19 +#define FCH_OHCI2_FUNC 0 +#define USB3_OHCI_BUS_DEV_FUN ((0x16 << 3) + 0) // PORT 10-13 +#define FCH_OHCI3_BUS 0 +#define FCH_OHCI3_DEV 22 +#define FCH_OHCI3_FUNC 0 +#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) // PORT 0-4 +#define FCH_EHCI1_BUS 0 +#define FCH_EHCI1_DEV 18 +#define FCH_EHCI1_FUNC 2 +#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) // PORT 5-9 +#define FCH_EHCI2_BUS 0 +#define FCH_EHCI2_DEV 19 +#define FCH_EHCI2_FUNC 2 +#define USB3_EHCI_BUS_DEV_FUN ((0x16 << 3) + 2) // PORT 10-13 +#define FCH_EHCI3_BUS 0 +#define FCH_EHCI3_DEV 22 +#define FCH_EHCI3_FUNC 2 +#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0) +#define FCH_ISA_BUS 0 +#define FCH_ISA_DEV 20 +#define FCH_ISA_FUNC 0 +#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1) +#define FCH_IDE_BUS 0 +#define FCH_IDE_DEV 20 +#define FCH_IDE_FUNC 1 +#define AZALIA_BUS_DEV_FUN ((0x9 << 3) + 2) +#define FCH_AZALIA_BUS 0 +#define FCH_AZALIA_DEV 9 +#define FCH_AZALIA_FUNC 2 +#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3) +#define FCH_LPC_BUS 0 +#define FCH_LPC_DEV 20 +#define FCH_LPC_FUNC 3 +#define PCIB_BUS_DEV_FUN ((0x14 << 3) + 4) // P2P in SB700 +#define FCH_PCI_BUS 0 +#define FCH_PCI_DEV 20 +#define FCH_PCI_FUNC 4 +#define USB4_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) // PORT FL0 - FL1 +#define FCH_OHCI4_BUS 0 +#define FCH_OHCI4_DEV 20 +#define FCH_OHCI4_FUNC 5 +//Gigabyte Ethernet Controller +#define GEC_BUS_DEV_FUN ((0x14 << 3) + 6) +#define FCH_GBEC_BUS 0 +#define FCH_GBEC_DEV 20 +#define FCH_GBEC_FUNC 6 + +#define SD_BUS_DEV_FUN ((0x14 << 3) + 7) // SD Controller +#define SD_PCI_BUS 0 +#define SD_PCI_DEV 20 +#define SD_PCI_FUNC 7 + + +#define FCH_GPP_BUS 0 +#define FCH_GPP_DEV 21 +#define FCH_GPP_FUNC 0 +#define GPP0_BUS_DEV_FUN ((0x15 << 3) + 0) // GPP P2P bridge PORT0 +#define GPP1_BUS_DEV_FUN ((0x15 << 3) + 1) // GPP P2P bridge PORT1 +#define GPP2_BUS_DEV_FUN ((0x15 << 3) + 2) // GPP P2P bridge PORT2 +#define GPP3_BUS_DEV_FUN ((0x15 << 3) + 3) // GPP P2P bridge PORT3 + +#define ACPI_MMIO_BASE 0xFED80000ul +#define FCH_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 +#define SERIAL_DEBUG_BASE 0x1000 +#define GFX_DAC_BASE 0x1400 +#define GPIO_BANK0_BASE 0x1500 // DWORD +//#define GPIO_BANK1_BASE 0x1600 // DWORD +//#define GPIO_BANK2_BASE 0x1700 // DWORD +#define CEC_BASE 0x1800 +#define XHCI_BASE 0x1C00 +#define ACDC_BASE 0x1D00 +#define AOAC_BASE 0x1E00 + + +// Chip type definition +#define CHIPTYPE_HUDSON2 (1 << 0) +#define CHIPTYPE_YUBA (1 << 1) + +// +// ROM SIG type definition +// +#define NUM_OF_ROMSIG_FILED 0x04 +#define XHCI_FILED_NUM 0x03 +#define ROMSIG_CFG_MASK 0x07 +#define XHCI_BOOT_RAM_OFFSET 0x8000 +#define INSTRUCTION_RAM_SIG 0x55AA +#define ROMSIG_SIG 0x55AA55AAul + +// RegSpace field (AB_INDEX[31:29] +#define AXINDC 0 // AXINDC +#define AXINDP 2 // AXINDP +#define ABCFG 6 // ABCFG +#define AXCFG 4 // AXCFG +#define RCINDXC 1 // PCIEIND +#define RCINDXP 3 // PCIEIND_P + +#define GPP_DEV_NUM 21 // +#define MAX_GPP_PORTS 4 + +#define PCIE_FORCE_GEN1_EFUSE_LOCATION 0x14 // EFUSE bit 160 +// +// ABCFG Registers +// +#define FCH_ABCFG_REG00 0x00 // VENDOR ID +#define FCH_ABCFG_REG08 0x08 // REVISION ID +#define FCH_ABCFG_REG40 0x40 // BL_EVENTCNT0LO +#define FCH_ABCFG_REG44 0x44 // BL_EVENTCNT1LO +#define FCH_ABCFG_REG48 0x48 // BL_EVENTCNTSEL +#define FCH_ABCFG_REG4A 0x4A // BL_EVENTCNT0HI +#define FCH_ABCFG_REG4B 0x4B // BL_EVENTCNT1HI +#define FCH_ABCFG_REG4C 0x4C // BL_EVENTCNTCTL +#define FCH_ABCFG_REG50 0x50 // MISCCTL_50 +#define FCH_ABCFG_REG54 0x54 // MISCCTL_54 +#define FCH_ABCFG_REG58 0x58 // BL RAB CONTROL + +#define FCH_ABCFG_REG60 0x60 // LINKWIDTH_CTL +#define FCH_ABCFG_REG64 0x64 // LINKWIDTH_UP_INTERVAL +#define FCH_ABCFG_REG68 0x68 // LINKWIDTH_DN_INVERVAL +#define FCH_ABCFG_REG6C 0x6C // LINKWIDTH_UPSTREAM_DWORDS +#define FCH_ABCFG_REG70 0x70 // LINKWIDTH_DOWNSTREAM_DWORDS +#define FCH_ABCFG_REG74 0x74 // LINKWIDTH_THRESHOLD_INCREASE +#define FCH_ABCFG_REG78 0x78 // LINKWIDTH_THRESHOLD_DECREASE + +#define FCH_ABCFG_REG80 0x80 // BL DMA PREFETCH CONTROL +#define FCH_ABCFG_REG88 0x88 // +#define FCH_ABCFG_REG8C 0x8C // +#define FCH_ABCFG_REG90 0x90 // BIF CONTROL 0 +#define FCH_ABCFG_REG94 0x94 // MSI CONTROL +#define FCH_ABCFG_REG98 0x98 // BIF CONTROL 1 +#define FCH_ABCFG_REG9C 0x9C // MISCCTL_9C +#define FCH_ABCFG_REGA0 0xA0 // BIF PHY CONTROL ENABLE +#define FCH_ABCFG_REGA4 0xA4 // BIF PHY CONTROL A4 +#define FCH_ABCFG_REGA8 0xA8 // BIF PHY CONTROL A8 +#define FCH_ABCFG_REGB0 0xB0 // HYPERFLASH-PCIE PORT MAPPING +#define FCH_ABCFG_REGB8 0xB8 // +#define FCH_ABCFG_REGB4 0xB4 // +#define FCH_ABCFG_REGBC 0xBC // +#define FCH_ABCFG_REGC0 0xC0 // PCIE_GPP_ENABLE +#define FCH_ABCFG_REGC4 0xC4 // PCIE_P2P_INT_MAP +#define FCH_ABCFG_REGD0 0xD0 // MCTP_VDM_TX_FIFO_DATA +#define FCH_ABCFG_REGD4 0xD4 // MCTP_VMD_TX_CONTROL +#define FCH_ABCFG_REGE0 0xE0 // MCTP_VDM_RX_FIFO_DATA +#define FCH_ABCFG_REGE4 0xE4 // MCTP_VDM_RX_FIFO_STATUS +#define FCH_ABCFG_REGEC 0xEC // MCTP_VDM_CONTROL +#define FCH_ABCFG_REGF0 0xF0 // GPP_UPSTREAM_CONTROL +#define FCH_ABCFG_REGF4 0xF4 // GPP_SYSTEM_ERROR_CONTROL +#define FCH_ABCFG_REGFC 0xFC // FCH_TRAP_CONTROL +#define FCH_ABCFG_REG100 0x100 // FCH_TRAP0_ADDRL +#define FCH_ABCFG_REG104 0x104 // FCH_TRAP0_ADDRH +#define FCH_ABCFG_REG108 0x108 // FCH_TRAP0_CMD +#define FCH_ABCFG_REG10C 0x10C // FCH_TRAP1_DATA +#define FCH_ABCFG_REG110 0x110 // FCH_TRAP1_ADDRL +#define FCH_ABCFG_REG114 0x114 // FCH_TRAP1_ADDRH +#define FCH_ABCFG_REG118 0x118 // FCH_TRAP1_CMD +#define FCH_ABCFG_REG11C 0x11C // FCH_TRAP1_DATA +#define FCH_ABCFG_REG120 0x120 // FCH_TRAP2_ADDRL +#define FCH_ABCFG_REG124 0x124 // FCH_TRAP2_ADDRH +#define FCH_ABCFG_REG128 0x128 // FCH_TRAP2_CMD +#define FCH_ABCFG_REG12C 0x12C // FCH_TRAP2_DATA +#define FCH_ABCFG_REG130 0x130 // FCH_TRAP3_ADDRL +#define FCH_ABCFG_REG134 0x134 // FCH_TRAP3_ADDRH +#define FCH_ABCFG_REG138 0x138 // FCH_TRAP3_CMD +#define FCH_ABCFG_REG13C 0x13C // FCH_TRAP3_DATA +#define FCH_ABCFG_REG180 0x180 // FCH_DMA_TRAFFIC_CONTROL +#define FCH_ABCFG_REG184 0x184 // FCH_AXI_DMA_MEMORY_POWER_SAVING +#define FCH_ABCFG_REG208 0x208 // SBG_MISC +#define FCH_ABCFG_REG300 0x300 // MCTP_VDM_RX_SMI_CONTROL +#define FCH_ABCFG_REG310 0x310 // BIF_GPP_STRAP_SYSTEM_0 +#define FCH_ABCFG_REG314 0x314 // BIF_GPP_STRAP_SYSTEM_1 +#define FCH_ABCFG_REG31C 0x31C // BIF_GPP_STRAP_LINK_CONTROL_0 +#define FCH_ABCFG_REG320 0x320 // BIF_GPP_STRAP_LINK_CONTROL_LANE_A +#define FCH_ABCFG_REG324 0x324 // BIF_GPP_STRAP_LINK_CONTROL_LANE_B +#define FCH_ABCFG_REG328 0x328 // BIF_GPP_STRAP_LINK_CONTROL_LANE_C +#define FCH_ABCFG_REG32C 0x32C // BIF_GPP_STRAP_LINK_CONTROL_LANE_D +#define FCH_ABCFG_REG330 0x330 // BIF_GPP_STRAP_BIF_0 +#define FCH_ABCFG_REG334 0x334 // BIF_GPP_STRAP_BIF_1 +#define FCH_ABCFG_REG338 0x338 // BIF_GPP_STRAP_BIF_2 +#define FCH_ABCFG_REG340 0x340 // BIF_GPP_STRAP_BIF_LANE_A +#define FCH_ABCFG_REG344 0x344 // BIF_GPP_STRAP_BIF_LANE_B +#define FCH_ABCFG_REG348 0x348 // BIF_GPP_STRAP_BIF_LANE_C +#define FCH_ABCFG_REG34C 0x34C // BIF_GPP_STRAP_BIF_LANE_D +#define FCH_ABCFG_REG350 0x350 // BIF_GPP_STRAP_PHY_LOGICAL _0 +#define FCH_ABCFG_REG354 0x354 // BIF_GPP_STRAP_PHY_LOGICAL _1 +#define FCH_ABCFG_REG404 0x404 // GPP0_SHADOW_COMMAND +#define FCH_ABCFG_REG418 0x418 // GPP0_SHADOW_BUS_NUMBER +#define FCH_ABCFG_REG41C 0x41C // GPP0_SHADOW_IO_LIMIT_BASE +#define FCH_ABCFG_REG420 0x420 // GPP0_SHADOW_MEM_LIMIT_BASE +#define FCH_ABCFG_REG424 0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE +#define FCH_ABCFG_REG428 0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER +#define FCH_ABCFG_REG42C 0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER +#define FCH_ABCFG_REG430 0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER +#define FCH_ABCFG_REG43C 0x43C // GPP0_SHADOW_BRIDGE_CONTROL +#define FCH_ABCFG_REG444 0x444 // GPP1_SHADOW_COMMAND +#define FCH_ABCFG_REG458 0x458 // GPP1_SHADOW_BUS_NUMBER +#define FCH_ABCFG_REG45C 0x45C // GPP1_SHADOW_IO_LIMIT_BASE +#define FCH_ABCFG_REG460 0x460 // GPP1_SHADOW_MEM_LIMIT_BASE +#define FCH_ABCFG_REG464 0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE +#define FCH_ABCFG_REG468 0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER +#define FCH_ABCFG_REG46C 0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER +#define FCH_ABCFG_REG470 0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER +#define FCH_ABCFG_REG47C 0x47C // GPP1_SHADOW_BRIDGE_CONTROL +#define FCH_ABCFG_REG484 0x484 // GPP2_SHADOW_COMMAND +#define FCH_ABCFG_REG498 0x498 // GPP2_SHADOW_BUS_NUMBER +#define FCH_ABCFG_REG49C 0x49C // GPP2_SHADOW_IO_LIMIT_BASE +#define FCH_ABCFG_REG4A0 0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE +#define FCH_ABCFG_REG4A4 0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE +#define FCH_ABCFG_REG4A8 0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER +#define FCH_ABCFG_REG4AC 0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER +#define FCH_ABCFG_REG4B0 0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER +#define FCH_ABCFG_REG4BC 0x4BC // GPP2_SHADOW_BRIDGE_CONTROL +#define FCH_ABCFG_REG4C4 0x4C4 // GPP3_SHADOW_COMMAND +#define FCH_ABCFG_REG4D8 0x4D8 // GPP3_SHADOW_BUS_NUMBER +#define FCH_ABCFG_REG4DC 0x4DC // GPP3_SHADOW_IO_LIMIT_BASE +#define FCH_ABCFG_REG4E0 0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE +#define FCH_ABCFG_REG4E4 0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE +#define FCH_ABCFG_REG4E8 0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER +#define FCH_ABCFG_REG4EC 0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER +#define FCH_ABCFG_REG4F0 0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER +#define FCH_ABCFG_REG4FC 0x4FC // GPP3_SHADOW_BRIDGE_CONTROL +#define FCH_ABCFG_REG10040 0x10040ul // AL_EVENTCNT0LO +#define FCH_ABCFG_REG10044 0x10044ul // AL_EVENTCNT1LO +#define FCH_ABCFG_REG10048 0x10048ul // AL_EVENTCNTSEL +#define FCH_ABCFG_REG1004A 0x1004Aul // AL_EVENTCNT0HI +#define FCH_ABCFG_REG1004B 0x1004Bul // AL_EVENTCNT1HI +#define FCH_ABCFG_REG1004C 0x1004Cul // AL_EVENTCNTCTL +#define FCH_ABCFG_REG10050 0x10050ul // MISCCTL_10050 +#define FCH_ABCFG_REG10054 0x10054ul // AL_ARB_CTL +#define FCH_ABCFG_REG10056 0x10056ul // AL_CLK_CTL +#define FCH_ABCFG_REG10058 0x10058ul // AL RAB CONTROL +#define FCH_ABCFG_REG1005C 0x1005Cul // AL MLT CONTROL +#define FCH_ABCFG_REG10060 0x10060ul // AL DMA PREFETCH ENABLE +#define FCH_ABCFG_REG10064 0x10064ul // AL DMA PREFETCH FLUSH CONTROL +#define FCH_ABCFG_REG10068 0x10068ul // AL PREFETCH LIMIT +#define FCH_ABCFG_REG1006C 0x1006Cul // AL DMA PREFETCH CONTROL +#define FCH_ABCFG_REG10070 0x10070ul // MISCCTL_10070 +#define FCH_ABCFG_REG10080 0x10080ul // CLKMUXSTATUS +#define FCH_ABCFG_REG10090 0x10090ul // BIF CONTROL 0 +#define FCH_ABCFG_REG1009C 0x1009Cul // MISCCTL_1009C + +// +// RCINDX_P Registers +// +#define FCH_RCINDXP_REG01 0x01 | RCINDXP << 29 // PCIEP_SCRATCH +#define FCH_RCINDXP_REG02 0x02 | RCINDXP << 29 // +#define FCH_RCINDXP_REG10 0x10 | RCINDXP << 29 // +#define FCH_RCINDXP_REG20 0x20 | RCINDXP << 29 // PCIE_TX_CNTL +#define FCH_RCINDXP_REG21 0x21 | RCINDXP << 29 // PCIE_TX_REQUESTER_ID +#define FCH_RCINDXP_REG50 0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS +#define FCH_RCINDXP_REG6A 0x6A | RCINDXP << 29 // +#define FCH_RCINDXP_REG70 0x70 | RCINDXP << 29 // PCIE_RX_CNTL +#define FCH_RCINDXP_REGA0 0xA0 | RCINDXP << 29 // PCIE_LC_CNTL +#define FCH_RCINDXP_REGA1 0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL +#define FCH_RCINDXP_REGA2 0xA2 | RCINDXP << 29 // +#define FCH_RCINDXP_REGA4 0xA4 | RCINDXP << 29 // +#define FCH_RCINDXP_REGA5 0xA5 | RCINDXP << 29 // PCIE_LC_STATE0 +#define FCH_RCINDXP_REGC0 0xC0 | RCINDXP << 29 // + +// +// RCINDX_C Registers +// +#define FCH_RCINDXC_REG02 0x02 | RCINDXC << 29 // PCIE_HW_DEBUG +#define FCH_RCINDXC_REG10 0x10 | RCINDXC << 29 // PCIE_CNTL +#define FCH_RCINDXC_REG40 0x40 | RCINDXC << 29 // PCIE_P_CNTL +#define FCH_RCINDXC_REG65 0x65 | RCINDXC << 29 // PCIE_P_PAD_FORCE_DIS +#define FCH_RCINDXC_REGC0 0xC0 | RCINDXC << 29 // PCIE_STRAP_MISC +#define FCH_RCINDXC_REGC1 0xC1 | RCINDXC << 29 // PCIE_STRAP_MISC2 + + +// +// AXINDC Registers +// +#define FCH_AX_INDXC_REG02 0x02 // PCIEP_HW_DEBUG +#define FCH_AX_INDXC_REG10 0x10 +#define FCH_AX_INDXC_REG30 0x30 +#define FCH_AX_DATAC_REG34 0x34 +#define FCH_AX_INDXP_REG38 0x38 +#define FCH_AX_DATAP_REG3C 0x3C +#define FCH_AX_INDXC_REG40 0x40 | AXINDC << 29 +#define FCH_AX_INDXC_REGA4 0xA4 | AXINDC << 29 + +#define FCH_AX_INDXP_REG02 0x02 | AXINDP << 29 +#define FCH_AX_INDXP_REGA0 0xA0 | AXINDP << 29 +#define FCH_AX_INDXP_REGA4 0xA4 | AXINDP << 29 +#define FCH_AX_INDXP_REGB1 0xB1 | AXINDP << 29 + +#define FCH_AX_CFG_REG68 0x68 | AXCFG << 29 +#define FCH_AX_CFG_REG88 0x88 | AXCFG << 29 + +#define FCH_AB_REG04 0x04 +#define FCH_AB_REG40 0x40 + +//Sata Port Configuration +#define SIX_PORTS 0 +#define FOUR_PORTS 1 + +#define SATA_EFUSE_LOCATION 0x10 // EFUSE bit 133 +#define SATA_DH_EFUSE_LOCATION 0x11 // EFUSE bit 138 +#define SATA_FIS_BASE_EFUSE_LOC 0x15 // EFUSE bit 169 +#define SATA_EFUSE_BIT 0x20 // +#define SATA_DH_EFUSE_BIT 0x04 // +#define FCH_SATA_REG00 0x000 // Vendor ID - R- 16 bits +#define FCH_SATA_REG02 0x002 // Device ID - RW -16 bits +#define FCH_SATA_REG04 0x004 // PCI Command - RW - 16 bits +#define FCH_SATA_REG06 0x006 // PCI Status - RW - 16 bits +#define FCH_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08 +#define FCH_SATA_REG0C 0x00C // Cache Line Size - R/W - 8bits +#define FCH_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits +#define FCH_SATA_REG0E 0x00E // Header Type - R - 8 bits +#define FCH_SATA_REG0F 0x00F // BIST - R - 8 bits +#define FCH_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits +#define FCH_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits +#define FCH_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits +#define FCH_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits +#define FCH_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits +#define FCH_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits +#define FCH_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits +#define FCH_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits +#define FCH_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits +#define FCH_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits +#define FCH_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits +#define FCH_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits +#define FCH_SATA_REG3E 0x03E // Min Grant - R - 8 bits +#define FCH_SATA_REG3F 0x03F // Max Latency - R - 8 bits +#define FCH_SATA_REG40 0x040 // Configuration - RW - 32 bits +#define FCH_SATA_REG44 0x044 // Software Data Register - RW - 32 bits +#define FCH_SATA_REG48 0x048 +#define FCH_SATA_REG4C 0x04C +#define FCH_SATA_REG50 0x050 // Message Capability - R - 16 bits +#define FCH_SATA_REG52 0x052 // Message Control - R/W - 16 bits +#define FCH_SATA_REG54 0x054 // Message Address - R/W - 32 bits +#define FCH_SATA_REG58 0x058 // Message Data - R/W - 16 bits +#define FCH_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits +#define FCH_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits +#define FCH_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits +#define FCH_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits +#define FCH_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits +#define FCH_SATA_REG68 0x068 // MSI Program - R/W - 8 bits +#define FCH_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits +#define FCH_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits +#define FCH_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits +#define FCH_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits +#define FCH_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits +#define FCH_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits +#define FCH_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits +#define FCH_SATA_REG86 0x086 // PY Global Control +#define FCH_SATA_REG87 0x087 +#define FCH_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune (0:23) +#define FCH_SATA_REG8A 0x08A +#define FCH_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune (0:23) +#define FCH_SATA_REG8E 0x08E +#define FCH_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune (0:23) +#define FCH_SATA_REG92 0x092 +#define FCH_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune (0:23) +#define FCH_SATA_REG96 0x096 +#define FCH_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits +#define FCH_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits +#define FCH_SATA_REGA0 0x0A0 // +#define FCH_SATA_REGA4 0x0A4 // +#define FCH_SATA_REGA5 0x0A5 //; +#define FCH_SATA_REGA8 0x0A8 // +#define FCH_SATA_REGAD 0x0AD //; +#define FCH_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits +#define FCH_SATA_REGB5 0x0B5 //; +#define FCH_SATA_REGBD 0x0BD //; +#define FCH_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits +#define FCH_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits + +#define FCH_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits +#define FCH_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits +#define FCH_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits +#define FCH_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits +#define FCH_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits +#define FCH_SATA_BAR5_REG1C 0x01C +#define FCH_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits +#define FCH_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits +#define FCH_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits +#define FCH_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits +#define FCH_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits +#define FCH_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits +#define FCH_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits +#define FCH_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits +#define FCH_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits +#define FCH_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits +#define FCH_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits +#define FCH_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits +#define FCH_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits +#define FCH_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits +#define FCH_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits +#define FCH_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits +#define FCH_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits +#define FCH_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits +#define FCH_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits +#define FCH_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits +#define FCH_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits +#define FCH_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits +#define FCH_SATA_BAR5_REG8C 0x08C // IDE0 Read Data - RW - 32 bits +#define FCH_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits +#define FCH_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits +#define FCH_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Byte Count - RW - 32 bits +#define FCH_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits +#define FCH_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits +#define FCH_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits +#define FCH_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits +#define FCH_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits +#define FCH_SATA_BAR5_REGCC 0x0CC // Read/Write Data - RW - 32 bits +#define FCH_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits +#define FCH_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits +#define FCH_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Byte Count - RW - 32 bits +#define FCH_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits +#define FCH_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits +#define FCH_SATA_BAR5_REGF8 0x0F8 // PORT Configuration +#define FCH_SATA_BAR5_REGFC 0x0FC +#define FCH_SATA_BAR5_REG100 0x0100 // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180 +#define FCH_SATA_BAR5_REG104 0x0104 // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel +#define FCH_SATA_BAR5_REG108 0x0108 // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel +#define FCH_SATA_BAR5_REG10C 0x010C // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel +#define FCH_SATA_BAR5_REG144 0x0144 // Serial ATA PY Configuration - RW - 32 bits +#define FCH_SATA_BAR5_REG148 0x0148 // SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)] +#define FCH_SATA_BAR5_REG14C 0x014C // SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)] +#define FCH_SATA_BAR5_REG120 0x0120 // +#define FCH_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status +#define FCH_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control +#define FCH_SATA_BAR5_REG130 0x0130 +#define FCH_SATA_BAR5_REG1B0 0x01B0 +#define FCH_SATA_BAR5_REG230 0x0230 +#define FCH_SATA_BAR5_REG2B0 0x02B0 +#define FCH_SATA_BAR5_REG330 0x0330 +#define FCH_SATA_BAR5_REG3B0 0x03B0 +#define FCH_SATA_BAR5_REG430 0x0430 +#define FCH_SATA_BAR5_REG4B0 0x04B0 + + +// USB ports +#define NUM_USB1_PORTS 5 +#define NUM_USB2_PORTS 5 +#define NUM_USB3_PORTS 4 +#define NUM_USB4_PORTS 2 +#define NUM_XHC0_PORTS 2 +#define NUM_XHC1_PORTS 2 + + +// +// USB OHCI Device 0x7807 +// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0 +// Device 20 (0x14) Func 5 (FL) 0x7809 +// +#define FCH_OHCI_REG00 0x00 // Device/Vendor ID - R (0x43971002ul) +#define FCH_OHCI_REG04 0x04 // Command - RW +#define FCH_OHCI_REG06 0x06 // Status - R +#define FCH_OHCI_REG08 0x08 // Revision ID/Class Code - R +#define FCH_OHCI_REG0C 0x0C // Miscellaneous - RW +#define FCH_OHCI_REG10 0x10 // Bar_OCI - RW +#define FCH_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW +#define FCH_OHCI_REG34 0x34 // Capability Pointer - R +#define FCH_OHCI_REG3C 0x3C // Interrupt Line - RW +#define FCH_OHCI_REG3D 0x3D // Interrupt Line - RW +#define FCH_OHCI_REG40 0x40 // Config Timers - RW +#define FCH_OHCI_REG42 0x42 // Port Disable Control - RW (800) +#define FCH_OHCI_REG46 0x46 // USB PHY Battery Charger - RW (800) +#define FCH_OHCI_REG48 0x48 // Port Force Reset - RW (800) +#define FCH_OHCI_REG4C 0x4C // MSI - RW (800) +#define FCH_OHCI_REG50 0x50 // Misc Control - RW +#define FCH_OHCI_REG51 0x51 +#define FCH_OHCI_REG52 0x52 +#define FCH_OHCI_REG58 0x58 // Over Current Control - RW +#define FCH_OHCI_REG5C 0x5C // Over Current Control - RW +#define FCH_OHCI_REG60 0x60 // Serial Bus Release Number - RW +#define FCH_OHCI_REG68 0x68 // Over Current PME Enable - RW +#define FCH_OHCI_REG74 0x74 // Target Timeout Control - RW +#define FCH_OHCI_REG80 0x80 // +#define FCH_OHCI_REGD0 0x0D0 // MSI Control - RW +#define FCH_OHCI_REGD4 0x0D4 // MSI Address - RW +#define FCH_OHCI_REGD8 0x0D8 // MSI Data - RW +#define FCH_OHCI_REGE4 0x0E4 // HT MSI Support +#define FCH_OHCI_REGF0 0x0F0 // Function Level Reset Capability +#define FCH_OHCI_REGF4 0x0F4 // Function Level Reset Control + +#define FCH_OHCI_BAR_REG00 0x00 // cRevision - R +#define FCH_OHCI_BAR_REG04 0x04 // cControl +#define FCH_OHCI_BAR_REG08 0x08 // cCommandStatus +#define FCH_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW +#define FCH_OHCI_BAR_REG10 0x10 // cInterruptEnable +#define FCH_OHCI_BAR_REG14 0x14 // cInterruptDisable +#define FCH_OHCI_BAR_REG18 0x18 // HcCCA +#define FCH_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED +#define FCH_OHCI_BAR_REG20 0x20 // HcControleadED +#define FCH_OHCI_BAR_REG24 0x24 // cControlCurrentED RW +#define FCH_OHCI_BAR_REG28 0x28 // HcBulkeadED +#define FCH_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW +#define FCH_OHCI_BAR_REG30 0x30 // HcDoneead +#define FCH_OHCI_BAR_REG34 0x34 // cFmInterval +#define FCH_OHCI_BAR_REG38 0x38 // cFmRemaining +#define FCH_OHCI_BAR_REG3C 0x3C // cFmNumber +#define FCH_OHCI_BAR_REG40 0x40 // cPeriodicStart +#define FCH_OHCI_BAR_REG44 0x44 // HcLSThresold +#define FCH_OHCI_BAR_REG48 0x48 // HcRDescriptorA +#define FCH_OHCI_BAR_REG4C 0x4C // HcRDescriptorB +#define FCH_OHCI_BAR_REG50 0x50 // HcRStatus +#define FCH_OHCI_BAR_REG54 0x54 // HcRhPortStatus (800) +#define FCH_OHCI_BAR_REG58 0x58 // HcRhPortStatus NPD (800) +#define FCH_OHCI_BAR_REGF0 0xF0 // OHCI Loop Back feature Support (800) + +#define FCH_OHCI_PORTSC_CCS 0x1 // HcRhPortStatus +#define FCH_OHCI_PORTSC_PES 0x2 // HcRhPortStatus +#define FCH_OHCI_PORTSC_PSS 0x4 // HcRhPortStatus +#define FCH_OHCI_PORTSC_PPS 0x100 // HcRhPortStatus +#define FCH_OHCI_PORTSC_LSDA 0x200 // HcRhPortStatus +#define FCH_OHCI_PORTSC_PRS 0x10 // HcRhPortStatus + +// +// USB EHCI Device 0x7808 +// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2 +// +#define FCH_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R +#define FCH_EHCI_REG04 0x04 // Command - RW +#define FCH_EHCI_REG06 0x06 // Status - R +#define FCH_EHCI_REG08 0x08 // Revision ID/Class Code - R +#define FCH_EHCI_REG0C 0x0C // Miscellaneous - RW +#define FCH_EHCI_REG10 0x10 // BAR - RW +#define FCH_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW +#define FCH_EHCI_REG34 0x34 // Capability Pointer - R +#define FCH_EHCI_REG3C 0x3C // Interrupt Line - RW +#define FCH_EHCI_REG3D 0x3D // Interrupt Line - RW +#define FCH_EHCI_REG40 0x40 // Config Timers - RW +#define FCH_EHCI_REG4C 0x4C // MSI - RW +#define FCH_EHCI_REG50 0x50 // EHCI Misc Control - RW +#define FCH_EHCI_REG54 0x54 // EHCI Misc Control - RW +#define FCH_EHCI_REG60 0x60 // SBRN - R +#define FCH_EHCI_REG61 0x61 // FLADJ - RW +#define FCH_EHCI_REG62 0x62 // PORTWAKECAP - RW +#define FCH_EHCI_REG64 0x64 // Misc Control 2 - RW +#define FCH_EHCI_REG70 0x70 // Over Current Control - RW +#define FCH_EHCI_REG74 0x74 // EHCI Misc Control2 - RW +#define FCH_EHCI_REG84 0x84 // HUB Configure 1 - RW +#define FCH_EHCI_REG88 0x88 // - RW +#define FCH_EHCI_REG90 0x90 // HUB Configure 4 - RW +#define FCH_EHCI_REGA0 0xA0 // +#define FCH_EHCI_REGA4 0xA4 // +#define FCH_EHCI_REGC0 0x0C0 // PME control - RW (800) +#define FCH_EHCI_REGC4 0x0C4 // PME Data /Status - RW (800) +#define FCH_EHCI_REGD0 0x0D0 // MSI Control - RW +#define FCH_EHCI_REGD4 0x0D4 // MSI Address - RW +#define FCH_EHCI_REGD8 0x0D8 // MSI Data - RW +#define FCH_EHCI_REGE4 0x0E4 // EHCI Debug Port Support - RW (800) +#define FCH_EHCI_REGF0 0x0F0 // Function Level Reset Capability - R (800) +#define FCH_EHCI_REGF4 0x0F4 // Function Level Reset Capability - R (800) + +#define FCH_EHCI_BAR_REG00 0x00 // CAPLENGT - R +#define FCH_EHCI_BAR_REG02 0x002 // CIVERSION- R +#define FCH_EHCI_BAR_REG04 0x004 // CSPARAMS - R +#define FCH_EHCI_BAR_REG08 0x008 // CCPARAMS - R +#define FCH_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R + +#define FCH_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits +#define FCH_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits +#define FCH_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits +#define FCH_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits +#define FCH_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits +#define FCH_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits +#define FCH_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits +#define FCH_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits +#define FCH_EHCI_BAR_REG64 0x064 // PORTSC (1-N_PORTS) -RW - 32 bits +#define FCH_EHCI_BAR_REGA0 0x0A0 // DebugPort MISC Control - RW - 32 bits (800) +#define FCH_EHCI_BAR_REGA4 0x0A4 // Packet Buffer Threshold Values - RW - 32 bits +#define FCH_EHCI_BAR_REGA8 0x0A8 // USB PHY Status 0 - R +#define FCH_EHCI_BAR_REGAC 0x0AC // USB PHY Status 1 - R +#define FCH_EHCI_BAR_REGB0 0x0B0 // USB PHY Status 2 - R +#define FCH_EHCI_BAR_REGB4 0x0B4 // UTMI Control - RW (800) +#define FCH_EHCI_BAR_REGB8 0x0B8 // Loopback Test +#define FCH_EHCI_BAR_REGBC 0x0BC // EHCI MISC Control +#define FCH_EHCI_BAR_REGC0 0x0C0 // USB PHY Calibration +#define FCH_EHCI_BAR_REGC4 0x0C4 // USB Common PHY Control +#define FCH_EHCI_BAR_REGC8 0x0C8 // EHCI Debug Purpose +#define FCH_EHCI_BAR_REGCC 0x0CC // Ehci Spare 1 (800) ** +#define FCH_EHCI_BAR_REGD0 0x0D0 +#define FCH_EHCI_BAR_REGD4 0x0D4 +#define FCH_EHCI_BAR_REGDC 0x0DC +#define FCH_EHCI_BAR_REG100 0x100 // USB debug port + +// +// USB XHCI Device 0x7812/0x7814 +// Device 16 (0x10) Func 0/1 +// +#define FCH_XHCI_REG00 0x00 // DEVICE/VENDOR ID - R +#define FCH_XHCI_REG04 0x04 // Command - RW +#define FCH_XHCI_REG10 0x10 // Bar0 +#define FCH_XHCI_REG2C 0x2C // Sub System ID +#define FCH_XHCI_REG40 0x40 // Index0 +#define FCH_XHCI_REG44 0x44 // Data0 +#define FCH_XHCI_REG48 0x48 // Index1 +#define FCH_XHCI_REG4C 0x4C // Data0 +#define FCH_XHCI_REG54 0x54 // PME Control/Status +#define XHCI_EFUSE_LOCATION 0x18 // EFUSE bit 192, 193 + +#define FCH_XHCI_BAR_REG420 0x420 // Port Status and Control +#define FCH_XHCI_PORTSC_CCS 0x1 // Port Status and Control +#define FCH_XHCI_PORTSC_PED 0x2 // Port Status and Control +#define FCH_XHCI_PORTSC_PLS 0x1E0 // Port Status and Control +#define FCH_XHCI_PORTSC_SPEED 0x3C00 // Port Status and Control +#define FCH_XHCI_PORTSC_PR 0x10 // Port Status and Control + +// +// FCH CFG device 0x780B +// Device 20 (0x14) Func 0 +// +#define FCH_CFG_REG00 0x000 // VendorID - R +#define FCH_CFG_REG02 0x002 // DeviceID - R +#define FCH_CFG_REG04 0x004 // Command- RW +#define FCH_CFG_REG05 0x005 // Command- RW +#define FCH_CFG_REG06 0x006 // STATUS- RW +#define FCH_CFG_REG08 0x008 // Revision ID/Class Code- R +#define FCH_CFG_REG0A 0x00A // +#define FCH_CFG_REG0B 0x00B // +#define FCH_CFG_REG0C 0x00C // Cache Line Size- R +#define FCH_CFG_REG0D 0x00D // Latency Timer- R +#define FCH_CFG_REG0E 0x00E // Header Type- R +#define FCH_CFG_REG0F 0x00F // BIST- R +#define FCH_CFG_REG10 0x010 // Base Address 0- R +#define FCH_CFG_REG11 0x011 //; +#define FCH_CFG_REG12 0x012 //; +#define FCH_CFG_REG13 0x013 //; +#define FCH_CFG_REG14 0x014 // Base Address 1- R +#define FCH_CFG_REG18 0x018 // Base Address 2- R +#define FCH_CFG_REG1C 0x01C // Base Address 3- R +#define FCH_CFG_REG20 0x020 // Base Address 4- R +#define FCH_CFG_REG24 0x024 // Base Address 5- R +#define FCH_CFG_REG28 0x028 // Cardbus CIS Pointer- R +#define FCH_CFG_REG2C 0x02C // Subsystem Vendor ID- W +#define FCH_CFG_REG2E 0x02E // Subsystem ID- W +#define FCH_CFG_REG30 0x030 // Expansion ROM Base Address - R +#define FCH_CFG_REG34 0x034 // Capability Pointer - R (800) default changed as 0x00 +#define FCH_CFG_REG3C 0x03C // Interrupt Line - R +#define FCH_CFG_REG3D 0x03D // Interrupt Pin - R +#define FCH_CFG_REG3E 0x03E // Min_Gnt - R +#define FCH_CFG_REG3F 0x03F // Max_Lat - R +#define FCH_CFG_REG90 0x090 // Smbus Base Address - R +#define FCH_CFG_REG9C 0x09C // SBResourceMMIO_BASE + +// +// FCH SATA IDE device +// Device 20 (0x14) Func 1 +// + +#define FCH_IDE_REG00 0x00 // Vendor ID +#define FCH_IDE_REG02 0x02 // Device ID +#define FCH_IDE_REG04 0x04 // Command +#define FCH_IDE_REG06 0x06 // Status +#define FCH_IDE_REG08 0x08 // Revision ID/Class Code +#define FCH_IDE_REG09 0x09 // Class Code +#define FCH_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID +#define FCH_IDE_REG40 0x40 // Configuration - RW - 32 bits +#define FCH_IDE_REG34 0x34 +#define FCH_IDE_REG62 0x62 // IDE Internal Control +#define FCH_IDE_REG63 0x63 // IDE Internal Control +// +// FCH AZALIA device 0x780D +// Device 20 (0x14) Func 2 +// +#define ATI_AZALIA_ExtBlk_Addr 0x0F8 +#define ATI_AZALIA_ExtBlk_DATA 0x0FC + +#define FCH_AZ_REG00 0x00 // Vendor ID - R +#define FCH_AZ_REG02 0x02 // Device ID - R/W +#define FCH_AZ_REG04 0x04 // PCI Command +#define FCH_AZ_REG06 0x06 // PCI Status - R/W +#define FCH_AZ_REG08 0x08 // Revision ID +#define FCH_AZ_REG09 0x09 // Programming Interface +#define FCH_AZ_REG0A 0x0A // Sub Class Code +#define FCH_AZ_REG0B 0x0B // Base Class Code +#define FCH_AZ_REG0C 0x0C // Cache Line Size - R/W +#define FCH_AZ_REG0D 0x0D // Latency Timer +#define FCH_AZ_REG0E 0x0E // Header Type +#define FCH_AZ_REG0F 0x0F // BIST +#define FCH_AZ_REG10 0x10 // Lower Base Address Register +#define FCH_AZ_REG14 0x14 // Upper Base Address Register +#define FCH_AZ_REG2C 0x2C // Subsystem Vendor ID +#define FCH_AZ_REG2D 0x2D // Subsystem ID +#define FCH_AZ_REG34 0x34 // Capabilities Pointer +#define FCH_AZ_REG3C 0x3C // Interrupt Line +#define FCH_AZ_REG3D 0x3D // Interrupt Pin +#define FCH_AZ_REG3E 0x3E // Minimum Grant +#define FCH_AZ_REG3F 0x3F // Maximum Latency +#define FCH_AZ_REG40 0x40 // Misc Control 1 +#define FCH_AZ_REG42 0x42 // Misc Control 2 Register +#define FCH_AZ_REG43 0x43 // Misc Control 3 Register +#define FCH_AZ_REG44 0x44 // Interrupt Pin Control Register +#define FCH_AZ_REG46 0x46 // Debug Control Register +#define FCH_AZ_REG4C 0x4C +#define FCH_AZ_REG50 0x50 // Power Management Capability ID +#define FCH_AZ_REG52 0x52 // Power Management Capabilities +#define FCH_AZ_REG54 0x54 // Power Management Control/Status +#define FCH_AZ_REG60 0x60 // MSI Capability ID +#define FCH_AZ_REG62 0x62 // MSI Message Control +#define FCH_AZ_REG64 0x64 // MSI Message Lower Address +#define FCH_AZ_REG68 0x68 // MSI Message Upper Address +#define FCH_AZ_REG6C 0x6C // MSI Message Data + +#define FCH_AZ_BAR_REG00 0x00 // Global Capabilities - R +#define FCH_AZ_BAR_REG02 0x02 // Minor Version - R +#define FCH_AZ_BAR_REG03 0x03 // Major Version - R +#define FCH_AZ_BAR_REG04 0x04 // Output Payload Capability - R +#define FCH_AZ_BAR_REG06 0x06 // Input Payload Capability - R +#define FCH_AZ_BAR_REG08 0x08 // Global Control - R/W +#define FCH_AZ_BAR_REG0C 0x0C // Wake Enable - R/W +#define FCH_AZ_BAR_REG0E 0x0E // State Change Status - R/W +#define FCH_AZ_BAR_REG10 0x10 // Global Status - R/W +#define FCH_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R +#define FCH_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R +#define FCH_AZ_BAR_REG20 0x20 // Interrupt Control - R/W +#define FCH_AZ_BAR_REG24 0x24 // Interrupt Status - R/W +#define FCH_AZ_BAR_REG30 0x30 // Wall Clock Counter - R +#define FCH_AZ_BAR_REG38 0x38 // Stream Synchronization - R/W +#define FCH_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W +#define FCH_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW +#define FCH_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W +#define FCH_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W +#define FCH_AZ_BAR_REG4C 0x4C // CORB Control - R/W +#define FCH_AZ_BAR_REG4D 0x4D // CORB Status - R/W +#define FCH_AZ_BAR_REG4E 0x4E // CORB Size - R/W +#define FCH_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW +#define FCH_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW +#define FCH_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW +#define FCH_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W +#define FCH_AZ_BAR_REG5C 0x5C // RIRB Control - R/W +#define FCH_AZ_BAR_REG5D 0x5D // RIRB Status - R/W +#define FCH_AZ_BAR_REG5E 0x5E // RIRB Size - R/W +#define FCH_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W +#define FCH_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W +#define FCH_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W +#define FCH_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W +#define FCH_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W +#define FCH_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R + +// +// FCH LPC Device 0x780E +// Device 20 (0x14) Func 3 +// +#define FCH_LPC_REG00 0x00 // VID- R +#define FCH_LPC_REG02 0x02 // DID- R +#define FCH_LPC_REG04 0x04 // CMD- RW +#define FCH_LPC_REG06 0x06 // STATUS- RW +#define FCH_LPC_REG08 0x08 // Revision ID/Class Code - R +#define FCH_LPC_REG0C 0x0C // Cache Line Size - R +#define FCH_LPC_REG0D 0x0D // Latency Timer - R +#define FCH_LPC_REG0E 0x0E // Header Type - R +#define FCH_LPC_REG0F 0x0F // BIST- R +#define FCH_LPC_REG10 0x10 // Base Address Reg 0- RW* +#define FCH_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro +#define FCH_LPC_REG34 0x34 // Capabilities Pointer - Ro +#define FCH_LPC_REG40 0x40 // PCI Control - RW +#define FCH_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW +#define FCH_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW +#define FCH_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW +#define FCH_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW +#define FCH_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW +#define FCH_LPC_REG49 0x49 // LPC Sync Timeout Count - RW +#define FCH_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW +#define FCH_LPC_REG4C 0x4C // Memory Range Register - RW +#define FCH_LPC_REG50 0x50 // Rom Protect 0 - RW +#define FCH_LPC_REG54 0x54 // Rom Protect 1 - RW +#define FCH_LPC_REG58 0x58 // Rom Protect 2 - RW +#define FCH_LPC_REG5C 0x5C // Rom Protect 3 - RW +#define FCH_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles - +#define FCH_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles - +#define FCH_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW +#define FCH_LPC_REG65 0x65 +#define FCH_LPC_REG66 0x66 +#define FCH_LPC_REG67 0x67 +#define FCH_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW +#define FCH_LPC_REG69 0x69 +#define FCH_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW +#define FCH_LPC_REG6B 0x6B +#define FCH_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW +#define FCH_LPC_REG6D 0x6D +#define FCH_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW +#define FCH_LPC_REG6F 0x6F +#define FCH_LPC_REG70 0x70 // Firmware ub Select - RW* +#define FCH_LPC_REG71 0x71 +#define FCH_LPC_REG72 0x72 +#define FCH_LPC_REG73 0x73 +#define FCH_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R +#define FCH_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R +#define FCH_LPC_REG79 0x79 // Miscellaneous Control Bits- W/R +#define FCH_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R +#define FCH_LPC_REG9C 0x9C +#define FCH_LPC_REG80 0x80 // MSI Capability Register- R +#define FCH_LPC_REGA0 0x0A0 // SPI base address +#define FCH_LPC_REGA1 0x0A1 // SPI base address +#define FCH_LPC_REGA2 0x0A2 // SPI base address +#define FCH_LPC_REGA3 0x0A3 // SPI base address +#define FCH_LPC_REGA4 0x0A4 +#define FCH_LPC_REGB8 0x0B8 +#define FCH_LPC_REGBA 0x0BA // EcControl +#define FCH_LPC_REGBB 0x0BB // HostControl +#define FCH_LPC_REGC8 0x0C8 +#define FCH_LPC_REGCC 0x0CC // AutoRomCfg +#define FCH_LPC_REGD0 0x0D0 +#define FCH_LPC_REGD3 0x0D3 +#define FCH_LPC_REGD4 0x0D4 + +// +// FCH PCIB 0x780F +// Device 20 (0x14) Func 4 +// +#define FCH_PCIB_REG04 0x04 // Command +#define FCH_PCIB_REG0D 0x0D // Primary Master Latency Timer +#define FCH_PCIB_REG1B 0x1B // Secondary Latency Timer +#define FCH_PCIB_REG1C 0x1C // IO Base +#define FCH_PCIB_REG1D 0x1D // IO Limit +#define FCH_PCIB_REG40 0x40 // CPCTRL +#define FCH_PCIB_REG42 0x42 // CLKCTRL +#define FCH_PCIB_REG48 0x48 // +#define FCH_PCIB_REG4A 0x4A // PCICLK Enable Bits +#define FCH_PCIB_REG4B 0x4B // Misc Control +#define FCH_PCIB_REG4C 0x4C // AutoClockRun Control +#define FCH_PCIB_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop Override +#define FCH_PCIB_REG65 0x65 // Misc Control +#define FCH_PCIB_REG66 0x66 // Misc Control +// +// FCH GEC 0x14E4 0x1699 +// Device 20 (0x14) Func 6 +// +#define FCH_GEC_REG10 0x10 // GEC BAR + +// +// FCH SD +// Device 20 (0x14) Func 7 +// +#define SD_PCI_REG10 0x10 +#define SD_PCI_REG2C 0x2C +#define SD_PCI_REGA4 0xA4 +#define SD_PCI_REGA8 0xA8 +#define SD_PCI_REGAC 0xAC +#define SD_PCI_REGB0 0xB0 +#define SD_PCI_REGB8 0xB8 +#define SD_PCI_REGBC 0xBC +#define SD_PCI_REGD0 0xD0 +#define SD_PCI_REGF0 0xF0 +#define SD_PCI_REGF4 0xF4 +#define SD_PCI_REGF8 0xF8 +#define SD_PCI_REGFC 0xFC +#define FCH_SD_BAR_REG28 0x28 // SDHC_CTRL1 +#define SD_CARD_PRESENT BIT0 +#define FCH_SD_BAR_REG2C 0x2C // SDHC_CTRL2 +#define FCH_SD_FREQUENCY_SLT BIT2 +#define FCH_SD_BAR_REG3C 0x3C // SDHC_HOST_CTRL2 +#define FCH_SD_1_8V BIT3 + +// +// FCH MMIO Base (SMI) +// offset : 0x200 +// +#define FCH_SMI_REG00 0x00 // EventStatus +#define FCH_SMI_REG04 0x04 // EventEnable +#define FCH_SMI_REG08 0x08 // SciTrig +#define FCH_SMI_REG0C 0x0C // SciLevl +#define FCH_SMI_REG10 0x10 // SmiSciStatus +#define FCH_SMI_REG14 0x14 // SmiSciEn +#define FCH_SMI_REG18 0x18 // ForceSciEn +#define FCH_SMI_REG1C 0x1C // SciRwData +#define FCH_SMI_REG3C 0x3C // DataErrorStatus +#define FCH_SMI_REG20 0x20 // SciS0En +#define FCH_SMI_Gevent0 0x40 // SciMap0 +#define FCH_SMI_Gevent1 0x41 // SciMap1 +#define FCH_SMI_Gevent2 0x42 // SciMap2 +#define FCH_SMI_Gevent3 0x43 // SciMap3 +#define FCH_SMI_Gevent4 0x44 // SciMap4 +#define FCH_SMI_Gevent5 0x45 // SciMap5 +#define FCH_SMI_Gevent6 0x46 // SciMap6 +#define FCH_SMI_Gevent7 0x47 // SciMap7 +#define FCH_SMI_Gevent8 0x48 // SciMap8 +#define FCH_SMI_Gevent9 0x49 // SciMap9 +#define FCH_SMI_Gevent10 0x4A // SciMap10 +#define FCH_SMI_Gevent11 0x4B // SciMap11 +#define FCH_SMI_Gevent12 0x4C // SciMap12 +#define FCH_SMI_Gevent13 0x4D // SciMap13 +#define FCH_SMI_Gevent14 0x4E // SciMap14 +#define FCH_SMI_Gevent15 0x4F // SciMap15 +#define FCH_SMI_Gevent16 0x50 // SciMap16 +#define FCH_SMI_Gevent17 0x51 // SciMap17 +#define FCH_SMI_Gevent18 0x52 // SciMap18 +#define FCH_SMI_Gevent19 0x53 // SciMap19 +#define FCH_SMI_Gevent20 0x54 // SciMap20 +#define FCH_SMI_Gevent21 0x55 // SciMap21 +#define FCH_SMI_Gevent22 0x56 // SciMap22 +#define FCH_SMI_Gevent23 0x57 // SciMap23 +#define FCH_SMI_Usbwakup0 0x58 // SciMap24 +#define FCH_SMI_Usbwakup1 0x59 // SciMap25 +#define FCH_SMI_Usbwakup2 0x5A // SciMap26 +#define FCH_SMI_Usbwakup3 0x5B // SciMap27 +#define FCH_SMI_SBGppPme0 0x5C // SciMap28 +#define FCH_SMI_SBGppPme1 0x5D // SciMap29 +#define FCH_SMI_SBGppPme2 0x5E // SciMap30 +#define FCH_SMI_SBGppPme3 0x5F // SciMap31 +#define FCH_SMI_SBGppHp0 0x60 // SciMap32 +#define FCH_SMI_SBGppHp1 0x61 // SciMap33 +#define FCH_SMI_SBGppHp2 0x62 // SciMap34 +#define FCH_SMI_SBGppHp3 0x63 // SciMap35 +#define FCH_SMI_AzaliaPme 0x64 // SciMap36 +#define FCH_SMI_SataGevent0 0x65 // SciMap37 +#define FCH_SMI_SataGevent1 0x66 // SciMap38 +#define FCH_SMI_GecPme 0x67 // SciMap39 +#define FCH_SMI_IMCGevent0 0x68 // SciMap40 +#define FCH_SMI_IMCGevent1 0x69 // SciMap41 +#define FCH_SMI_CIRPme 0x6A // SciMap42 +#define FCH_SMI_WakePinGevent 0x6B // SciMap43 +#define FCH_SMI_FanThGevent 0x6C // SciMap44 //FanThermalGevent +#define FCH_SMI_ASFMasterIntr 0x6D // SciMap45 +#define FCH_SMI_ASFSlaveIntr 0x6E // SciMap46 +#define FCH_SMI_SMBUS0 0x6F // SciMap47 +#define FCH_SMI_TWARN 0x70 // SciMap48 +#define FCH_SMI_TMI 0x71 // SciMap49 // TrafficMonitorIntr +#define FCH_SMI_iLLB 0x72 // SciMap50 +#define FCH_SMI_PowerButton 0x73 // SciMap51 +#define FCH_SMI_ProcHot 0x74 // SciMap52 +#define FCH_SMI_APUHwAssertion 0x75 // SciMap53 +#define FCH_SMI_APUSciAssertion 0x76 // SciMap54 +#define FCH_SMI_RAS 0x77 // SciMap55 +#define FCH_SMI_xHC0Pme 0x78 // SciMap56 +#define FCH_SMI_xHC1Pme 0x79 // SciMap57 +#define FCH_SMI_AcDcWake 0x7A // SciMap58 + +// Empty from 0x72-0x7F +//#Define FCH_SMI_REG7C 0x7F // SciMap63 *** + +#define FCH_SMI_REG80 0x80 // SmiStatus0 +#define FCH_SMI_REG84 0x84 // SmiStatus1 +#define FCH_SMI_REG88 0x88 // SmiStatus2 +#define FCH_SMI_REG8C 0x8C // SmiStatus3 +#define FCH_SMI_REG90 0x90 // SmiStatus4 +#define FCH_SMI_REG94 0x94 // SmiPointer +#define FCH_SMI_REG96 0x96 // SmiTimer +#define FCH_SMI_REG98 0x98 // SmiTrig +#define FCH_SMI_REG9C 0x9C // SmiTrig +#define FCH_SMI_REGA0 0xA0 +#define FCH_SMI_REGA1 0xA1 +#define FCH_SMI_REGA2 0xA2 +#define FCH_SMI_REGA3 0xA3 +#define FCH_SMI_REGA4 0xA4 +#define FCH_SMI_REGA5 0xA5 +#define FCH_SMI_REGA6 0xA6 +#define FCH_SMI_REGA7 0xA7 +#define FCH_SMI_REGA8 0xA8 +#define FCH_SMI_REGA9 0xA9 +#define FCH_SMI_REGAA 0xAA +#define FCH_SMI_REGAB 0xAB +#define FCH_SMI_REGAC 0xAC +#define FCH_SMI_REGAD 0xAD +#define FCH_SMI_REGAE 0xAE +#define FCH_SMI_REGAF 0xAF +#define FCH_SMI_REGB0 0xB0 +#define FCH_SMI_REGB1 0xB1 +#define FCH_SMI_REGB2 0xB2 +#define FCH_SMI_REGB3 0xB3 +#define FCH_SMI_REGB4 0xB4 +#define FCH_SMI_REGB5 0xB5 +#define FCH_SMI_REGB6 0xB6 +#define FCH_SMI_REGB7 0xB7 +#define FCH_SMI_REGB8 0xB8 +#define FCH_SMI_REGB9 0xB9 +#define FCH_SMI_REGBA 0xBA +#define FCH_SMI_REGBB 0xBB +#define FCH_SMI_REGBC 0xBC +#define FCH_SMI_REGBD 0xBD +#define FCH_SMI_REGBE 0xBE +#define FCH_SMI_REGBF 0xBF +#define FCH_SMI_REGC0 0xC0 +#define FCH_SMI_REGC1 0xC1 +#define FCH_SMI_REGC2 0xC2 +#define FCH_SMI_REGC3 0xC3 +#define FCH_SMI_REGC4 0xC4 +#define FCH_SMI_REGC5 0xC5 +#define FCH_SMI_REGC6 0xC6 +#define FCH_SMI_REGC7 0xC7 +#define FCH_SMI_REGC8 0xC8 +#define FCH_SMI_REGCA 0xCA // IoTrapping1 +#define FCH_SMI_REGCC 0xCC // IoTrapping2 +#define FCH_SMI_REGCE 0xCE // IoTrapping3 +#define FCH_SMI_TRAPPING_WRITE 0x01 +#define FCH_SMI_REGD0 0xD0 // MemTrapping0 +#define FCH_SMI_REGD4 0xD4 // MemRdOvrData0 +#define FCH_SMI_REGD8 0xD8 // MemTrapping1 +#define FCH_SMI_REGDC 0xDC // MemRdOvrData1 +#define FCH_SMI_REGE0 0xE0 // MemTrapping2 +#define FCH_SMI_REGE4 0xE4 // MemRdOvrData2 +#define FCH_SMI_REGE8 0xE8 // MemTrapping3 +#define FCH_SMI_REGEC 0xEC // MemRdOvrData3 +#define FCH_SMI_REGF0 0xF0 // CfgTrapping0 +#define FCH_SMI_REGF4 0xF4 // CfgTrapping1 +#define FCH_SMI_REGF8 0xF8 // CfgTrapping2 +#define FCH_SMI_REGFC 0xFC // CfgTrapping3 + +// +// FCH MMIO Base (PMIO) +// offset : 0x300 +// +#define FCH_PMIOA_REG00 0x00 // ISA Decode +#define FCH_PMIOA_REG04 0x04 // ISA Control +#define FCH_PMIOA_REG08 0x08 // PCI Control +#define FCH_PMIOA_REG0C 0x0C // StpClkSmaf +#define FCH_PMIOA_REG10 0x10 // RetryDetect +#define FCH_PMIOA_REG14 0x14 // StuckDetect +#define FCH_PMIOA_REG20 0x20 // BiosRamEn +#define FCH_PMIOA_REG24 0x24 // AcpiMmioEn +#define FCH_PMIOA_REG28 0x28 // AsfEn +#define FCH_PMIOA_REG2C 0x2C // Smbus0En +#define FCH_PMIOA_REG2E 0x2E // Smbus0Sel +#define FCH_PMIOA_REG34 0x34 // IoApicEn +#define FCH_PMIOA_REG3C 0x3C // SmartVoltEn +#define FCH_PMIOA_REG40 0x40 // SmartVolt2En +#define FCH_PMIOA_REG44 0x44 // BootTimerEn +#define FCH_PMIOA_REG48 0x48 // WatchDogTimerEn +#define FCH_PMIOA_REG4C 0x4C // WatchDogTimerConfig +#define FCH_PMIOA_REG50 0x50 // HPETEn +#define FCH_PMIOA_REG54 0x54 // SerialIrqConfig +#define FCH_PMIOA_REG56 0x56 // RtcControl +#define FCH_PMIOA_REG58 0x58 // VRT_T1 +#define FCH_PMIOA_REG59 0x59 // VRT_T2 +#define FCH_PMIOA_REG5A 0x5A // IntruderControl +#define FCH_PMIOA_REG5B 0x5B // RtcShadow +#define FCH_PMIOA_REG5C 0x5C +#define FCH_PMIOA_REG5D 0x5D +#define FCH_PMIOA_REG5E 0x5E // RtcExtIndex +#define FCH_PMIOA_REG5F 0x5F // RtcExtData +#define FCH_PMIOA_REG60 0x60 // AcpiPm1EvtBlk +#define FCH_PMIOA_REG62 0x62 // AcpiPm1CntBlk +#define FCH_PMIOA_REG64 0x64 // AcpiPmTmrBlk +#define FCH_PMIOA_REG66 0x66 // P_CNTBlk +#define FCH_PMIOA_REG68 0x68 // AcpiGpe0Blk +#define FCH_PMIOA_REG6A 0x6A // AcpiSmiCmd +#define FCH_PMIOA_REG6C 0x6C // AcpiPm2CntBlk +#define FCH_PMIOA_REG6E 0x6E // AcpiPmaCntBlk +#define FCH_PMIOA_REG74 0x74 // AcpiConfig +#define FCH_PMIOA_REG78 0x78 // WakeIoAddr +#define FCH_PMIOA_REG7A 0x7A // HaltCountEn +#define FCH_PMIOA_REG7C 0x7C // C1eWrPortAdr +#define FCH_PMIOA_REG7E 0x7E // CStateEn +#define FCH_PMIOA_REG7F 0x7F // CStateEn +#define FCH_PMIOA_REG80 0x80 // BreakEvent +#define FCH_PMIOA_REG84 0x84 // AutoArbEn +#define FCH_PMIOA_REG88 0x88 // CStateControl +#define FCH_PMIOA_REG89 0x89 // +#define FCH_PMIOA_REG8C 0x8C // StpClkHoldTime +#define FCH_PMIOA_REG8E 0x8E // PopUpEndTime +#define FCH_PMIOA_REG90 0x90 // C4Control +#define FCH_PMIOA_REG94 0x94 // CStateTiming0 +#define FCH_PMIOA_REG96 0x96 // +#define FCH_PMIOA_REG97 0x97 // +#define FCH_PMIOA_REG98 0x98 // CStateTiming1 +#define FCH_PMIOA_REG99 0x99 // +#define FCH_PMIOA_REG9B 0x9B // +#define FCH_PMIOA_REG9C 0x9C // C2Count +#define FCH_PMIOA_REG9D 0x9D // C3Count +#define FCH_PMIOA_REG9E 0x9E // C4Count +#define FCH_PMIOA_REGA0 0xA0 // MessageCState +#define FCH_PMIOA_REGA4 0xA4 // +#define FCH_PMIOA_REGA8 0xA8 // TrafficMonitorIdleTime +#define FCH_PMIOA_REGAA 0xAA // TrafficMonitorIntTime +#define FCH_PMIOA_REGAC 0xAC // TrafficMonitorTrafficCount +#define FCH_PMIOA_REGAE 0xAE // TrafficMonitorIntrCount +#define FCH_PMIOA_REGB0 0xB0 // TrafficMonitorTimeTick +#define FCH_PMIOA_REGB4 0xB4 // FidVidControl +#define FCH_PMIOA_REGB6 0xB6 // TPRESET1 +#define FCH_PMIOA_REGB7 0xB7 // Tpreset1b +#define FCH_PMIOA_REGB8 0xB8 // TPRESET2 +#define FCH_PMIOA_REGB9 0xB9 // Test0 +#define FCH_PMIOA_REGBA 0xBA // S_StateControl +#define FCH_PMIOA_REGBB 0xBB // +#define FCH_PMIOA_REGBC 0xBC // ThrottlingControl +#define FCH_PMIOA_REGBE 0xBE // ResetControl +#define FCH_PMIOA_REGBF 0xBF // ResetControl +#define FCH_PMIOA_REGC0 0xC0 // S5Status +#define FCH_PMIOA_REGC2 0xC2 // ResetStatus +#define FCH_PMIOA_REGC4 0xC4 // ResetCommand +#define FCH_PMIOA_REGC5 0xC5 // CF9Shadow +#define FCH_PMIOA_REGC6 0xC6 // HTControl +#define FCH_PMIOA_REGC8 0xC8 // Misc +#define FCH_PMIOA_REGCC 0xCC // IoDrvSth +#define FCH_PMIOA_REGD0 0xD0 // CLKRunEn +#define FCH_PMIOA_REGD2 0xD2 // PmioDebug +#define FCH_PMIOA_REGD3 0xD3 // SD +#define FCH_PMIOA_REGD6 0xD6 // IMCGating +#define FCH_PMIOA_REGD7 0xD7 // +#define FCH_PMIOA_REGD8 0xD8 // MiscIndex +#define FCH_PMIOA_REGD9 0xD9 // MiscData +#define FCH_PMIOA_REGDA 0xDA // SataConfig +#define FCH_PMIOA_REGDC 0xDC // HyperFlashConfig +#define FCH_PMIOA_REGDE 0xDE // ABConfig +#define FCH_PMIOA_REGE0 0xE0 // ABRegBar +#define FCH_PMIOA_REGE4 0xE4 +#define FCH_PMIOA_REGE6 0xE6 // FcEn +#define FCH_PMIOA_REGE7 0xE7 +#define FCH_PMIOA_REGE8 0xE8 +#define FCH_PMIOA_REGEA 0xEA // PcibConfig +#define FCH_PMIOA_REGEB 0xEB // AzEn +#define FCH_PMIOA_REGEC 0xEC // LpcGating +#define FCH_PMIOA_REGED 0xED // UsbGating +#define FCH_PMIOA_REGEE 0xEE // UsbCntrl +#define FCH_PMIOA_REGEF 0xEF // UsbEnable +#define FCH_PMIOA_REGF0 0xF0 // UsbControl +#define FCH_PMIOA_REGF2 0xF2 // UsbControl2 +#define FCH_PMIOA_REGF3 0xF3 // UsbDebug +#define FCH_PMIOA_REGF4 0xF4 // UsbDebug +#define FCH_PMIOA_REGF6 0xF6 // GecEn +#define FCH_PMIOA_REGF8 0xF8 // GecConfig +#define FCH_PMIOA_REGFC 0xFC // TraceMemoryEn + +#define FCH_PMx00_DecodeEn 0xFED80300ul // +#define FCH_PMxC0_ResetStatus 0xFED803C0ul // +#define FCH_PMxC0_ResetStatus_Mask 0x3fff0000ul // +#define FCH_PMxC4_ResetCommand 0xFED803C4ul // +#define FCH_PMxDC_SataConfig2 0xFED803DCul // + +// +// FCH MMIO Base (PMIO2) +// offset : 0x400 +// +#define FCH_PMIO2_REG00 0x00 // Fan0InputControl +#define FCH_PMIO2_REG01 0x01 // Fan0Control +#define FCH_PMIO2_REG02 0x02 // Fan0Freq +#define FCH_PMIO2_REG03 0x03 // LowDuty0 +#define FCH_PMIO2_REG04 0x04 // MidDuty0 + +#define FCH_PMIO2_REG10 0x00 // Fan1InputControl +#define FCH_PMIO2_REG11 0x01 // Fan1Control +#define FCH_PMIO2_REG12 0x02 // Fan1Freq +#define FCH_PMIO2_REG13 0x03 // LowDuty1 +#define FCH_PMIO2_REG14 0x04 // MidDuty1 + +#define FCH_PMIO2_REG63 0x63 // SampleFreqDiv +#define FCH_PMIO2_REG69 0x69 // Fan0 Speed +#define FCH_PMIO2_REG95 0x95 // Temperature +#define FCH_PMIO2_REGB8 0xB8 // Voltage +#define FCH_PMIO2_REGEA 0xEA // Hwm_Calibration + +#define FCH_PMIO2_REG92 0x92 // +#define FCH_PMIO2_REGF8 0xF8 // VoltageSamleSel +#define FCH_PMIO2_REGF9 0xF9 // TempSampleSel + +#define FCH_PMIO2_REG 0xFC // TraceMemoryEn + + +// +// FCH MMIO Base (GPIO/IoMux) +// offset : 0x100/0xD00 +// +/* +GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226. +*/ +#define FCH_GPIO_REG00 0x00 +#define FCH_GPIO_REG06 0x06 +#define FCH_GPIO_REG09 0x09 +#define FCH_GPIO_REG10 0x0A +#define FCH_GPIO_REG17 0x11 +#define FCH_GPIO_REG21 0x15 +#define FCH_GPIO_REG28 0x1C +#define FCH_GPIO_REG32 0x20 +#define FCH_GPIO_REG33 0x21 +#define FCH_GPIO_REG34 0x22 +#define FCH_GPIO_REG35 0x23 +#define FCH_GPIO_REG36 0x24 +#define FCH_GPIO_REG37 0x25 +#define FCH_GPIO_REG38 0x26 +#define FCH_GPIO_REG39 0x27 +#define FCH_GPIO_REG40 0x28 +#define FCH_GPIO_REG41 0x29 +#define FCH_GPIO_REG42 0x2A +#define FCH_GPIO_REG43 0x2B +#define FCH_GPIO_REG44 0x2C +#define FCH_GPIO_REG45 0x2D +#define FCH_GPIO_REG46 0x2E +#define FCH_GPIO_REG47 0x2F +#define FCH_GPIO_REG48 0x30 +#define FCH_GPIO_REG49 0x31 +#define FCH_GPIO_REG50 0x32 +#define FCH_GPIO_REG51 0x33 +#define FCH_GPIO_REG52 0x34 +#define FCH_GPIO_REG53 0x35 +#define FCH_GPIO_REG54 0x36 +#define FCH_GPIO_REG55 0x37 +#define FCH_GPIO_REG56 0x38 +#define FCH_GPIO_REG57 0x39 +#define FCH_GPIO_REG58 0x3A +#define FCH_GPIO_REG59 0x3B +#define FCH_GPIO_REG60 0x3C +#define FCH_GPIO_REG61 0x3D +#define FCH_GPIO_REG62 0x3E +#define FCH_GPIO_REG63 0x3F +#define FCH_GPIO_REG64 0x40 +#define FCH_GPIO_REG65 0x41 +#define FCH_GPIO_REG66 0x42 +#define FCH_GPIO_REG67 0x43 +#define FCH_GPIO_REG68 0x44 +#define FCH_GPIO_REG69 0x45 +#define FCH_GPIO_REG70 0x46 +#define FCH_GPIO_REG71 0x47 +#define FCH_GPIO_REG72 0x48 +#define FCH_GPIO_REG73 0x49 +#define FCH_GPIO_REG74 0x4A +#define FCH_GPIO_REG75 0x4B +#define FCH_GPIO_REG76 0x4C +#define FCH_GPIO_REG77 0x4D +#define FCH_GPIO_REG78 0x4E +#define FCH_GPIO_REG79 0x4F +#define FCH_GPIO_REG80 0x50 + +#define FCH_GEVENT_REG00 0x60 +#define FCH_GEVENT_REG01 0x61 +#define FCH_GEVENT_REG02 0x62 +#define FCH_GEVENT_REG03 0x63 +#define FCH_GEVENT_REG04 0x64 +#define FCH_GEVENT_REG05 0x65 +#define FCH_GEVENT_REG06 0x66 +#define FCH_GEVENT_REG07 0x67 +#define FCH_GEVENT_REG08 0x68 +#define FCH_GEVENT_REG09 0x69 +#define FCH_GEVENT_REG10 0x6A +#define FCH_GEVENT_REG11 0x6B +#define FCH_GEVENT_REG12 0x6C +#define FCH_GEVENT_REG13 0x6D +#define FCH_GEVENT_REG14 0x6E +#define FCH_GEVENT_REG15 0x6F +#define FCH_GEVENT_REG16 0x70 +#define FCH_GEVENT_REG17 0x71 +#define FCH_GEVENT_REG18 0x72 +#define FCH_GEVENT_REG19 0x73 +#define FCH_GEVENT_REG20 0x74 +#define FCH_GEVENT_REG21 0x75 +#define FCH_GEVENT_REG22 0x76 +#define FCH_GEVENT_REG23 0x77 +// S5-DOMAIN GPIO +#define FCH_GPIO_REG160 0xA0 +#define FCH_GPIO_REG161 0xA1 +#define FCH_GPIO_REG162 0xA2 +#define FCH_GPIO_REG163 0xA3 +#define FCH_GPIO_REG164 0xA4 +#define FCH_GPIO_REG165 0xA5 +#define FCH_GPIO_REG166 0xA6 +#define FCH_GPIO_REG167 0xA7 +#define FCH_GPIO_REG168 0xA8 +#define FCH_GPIO_REG169 0xA9 +#define FCH_GPIO_REG170 0xAA +#define FCH_GPIO_REG171 0xAB +#define FCH_GPIO_REG172 0xAC +#define FCH_GPIO_REG173 0xAD +#define FCH_GPIO_REG174 0xAE +#define FCH_GPIO_REG175 0xAF +#define FCH_GPIO_REG176 0xB0 +#define FCH_GPIO_REG177 0xB1 +#define FCH_GPIO_REG178 0xB2 +#define FCH_GPIO_REG179 0xB3 +#define FCH_GPIO_REG180 0xB4 +#define FCH_GPIO_REG181 0xB5 +#define FCH_GPIO_REG182 0xB6 +#define FCH_GPIO_REG183 0xB7 +#define FCH_GPIO_REG184 0xB8 +#define FCH_GPIO_REG185 0xB9 +#define FCH_GPIO_REG186 0xBA +#define FCH_GPIO_REG187 0xBB +#define FCH_GPIO_REG188 0xBC +#define FCH_GPIO_REG189 0xBD +#define FCH_GPIO_REG190 0xBE +#define FCH_GPIO_REG191 0xBF +#define FCH_GPIO_REG192 0xC0 +#define FCH_GPIO_REG193 0xC1 +#define FCH_GPIO_REG194 0xC2 +#define FCH_GPIO_REG195 0xC3 +#define FCH_GPIO_REG196 0xC4 +#define FCH_GPIO_REG197 0xC5 +#define FCH_GPIO_REG198 0xC6 +#define FCH_GPIO_REG199 0xC7 +#define FCH_GPIO_REG200 0xC8 +#define FCH_GPIO_REG201 0xC9 +#define FCH_GPIO_REG202 0xCA +#define FCH_GPIO_REG203 0xCB +#define FCH_GPIO_REG204 0xCC +#define FCH_GPIO_REG205 0xCD +#define FCH_GPIO_REG206 0xCE +#define FCH_GPIO_REG207 0xCF +#define FCH_GPIO_REG208 0xD0 +#define FCH_GPIO_REG209 0xD1 +#define FCH_GPIO_REG210 0xD2 +#define FCH_GPIO_REG211 0xD3 +#define FCH_GPIO_REG212 0xD4 +#define FCH_GPIO_REG213 0xD5 +#define FCH_GPIO_REG214 0xD6 +#define FCH_GPIO_REG215 0xD7 +#define FCH_GPIO_REG216 0xD8 +#define FCH_GPIO_REG217 0xD9 +#define FCH_GPIO_REG218 0xDA +#define FCH_GPIO_REG219 0xDB +#define FCH_GPIO_REG220 0xDC +#define FCH_GPIO_REG221 0xDD +#define FCH_GPIO_REG222 0xDE +#define FCH_GPIO_REG223 0xDF +#define FCH_GPIO_REG224 0xF0 +#define FCH_GPIO_REG225 0xF1 +#define FCH_GPIO_REG226 0xF2 +#define FCH_GPIO_REG227 0xF3 +#define FCH_GPIO_REG228 0xF4 + +#define FCH_IOMUXx0D_IR_TX0_USB_OC5_L_AGPIO13 0xFED80D0Dul // +#define FCH_IOMUXx0E_IR_TX1_USB_OC6_L_AGPIO14 0xFED80D0Eul // +#define FCH_IOMUXx13_SCL1_I2C3_SCL_EGPIO19 0xFED80D13ul // +#define FCH_IOMUXx14_SDA1_I2C3_SDA_EGPIO20 0xFED80D14ul // +#define FCH_IOMUX_55_FANOUT0_AGPIO85 0xFED80D55ul // FANOUT0_AGPIO85 +#define FCH_IOMUXx66_SD0_PWR_CTRL_AGPIO102 0xFED80D66ul // +#define FCH_IOMUXx71_SCL0_I2C2_SCL_EGPIO113 0xFED80D71ul // +#define FCH_IOMUXx72_SDA0_I2C2_SDA_EGPIO114 0xFED80D72ul // +#define FCH_IOMUXx89_UART0_RTS_L_EGPIO137 0xFED80D89ul // +#define FCH_IOMUXx8A_UART0_TXD_EGPIO138 0xFED80D8Aul // +#define FCH_IOMUXx8E_UART1_RTS_L_EGPIO142 0xFED80D8Eul // +#define FCH_IOMUXx8F_UART1_TXD_EGPIO143 0xFED80D8Ful // + +// +// FCH MMIO Base (GPIO BANK0) +// offset : 0x1500 +// +#define FCH_GPIO_PULL_UP_ENABLE BIT4 +#define FCH_GPIO_PULL_DOWN_ENABLE BIT5 +#define FCH_GPIO_OUTPUT_VALUE BIT6 +#define FCH_GPIO_OUTPUT_ENABLE (1 << 7) + +#define FCH_GPIO_068_AZ_SDIN0_GPIO26 0x68 +#define FCH_GPIO_06C_AZ_SDIN1_GPIO27 0x6C +#define FCH_GPIO_070_AZ_SDIN2_GPIO28 0x70 +#define FCH_GPIO_074_AZ_SDIN3_GPIO29 0x74 + +#define FCH_GPIO_10C_GPIO55_AGPI067 0x10C +#define FCH_GPIO_118_GPIO59_AGPI070 0x118 + +// +// FCH MMIO Base (IoMux) +// offset : 0xD00 +// +#define FCH_IOMUX_1A_AZ_SDIN0_EGPIO26 0x1A +#define FCH_IOMUX_1B_AZ_SDIN1_EGPIO27 0x1B +#define FCH_IOMUX_1C_AZ_SDIN2_EGPIO28 0x1C +#define FCH_IOMUX_1D_AZ_SDIN3_EGPIO29 0x1D + +// +// FCH MMIO Base (SMBUS) +// offset : 0xA00 +// +#define FCH_SMBUS_REG12 0x12 // I2CbusConfig + +// +// FCH MMIO Base (MISC) +// offset : 0xE00 +// +#define FCH_MISC_REG00 0x00 // ClkCntrl0 +/* +FCH_MISC_REG00 EQU 000h + ClkCntrl0 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG04 0x04 // ClkCntrl1 +/* +FCH_MISC_REG04 EQU 004h + ClkCntrl1 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG08 0x08 // ClkCntrl2 +/* +FCH_MISC_REG08 EQU 008h + ClkCntrl2 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG0C 0x0C // ClkCntrl3 +/* +FCH_MISC_REG0C EQU 00Ch + ClkCntrl3 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG10 0x10 // ClkCntrl4 +/* +FCH_MISC_REG10 EQU 010h + ClkCntrl4 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG14 0x14 // ClkCntrl5 +/* +FCH_MISC_REG14 EQU 014h + ClkCntrl5 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG18 0x18 // ClkCntrl6 +/* +FCH_MISC_REG18 EQU 018h + ClkCntrl6 EQU 0FFFFFFFFh +*/ +#define FCH_MISC_REG1C 0x1C +#define FCH_MISC_REG20 0x20 +#define FCH_MISC_REG30 0x30 // OscFreqCounter +/* +FCH_MISC_REG30 EQU 030h + OscCounter EQU 0FFFFFFFFh ; The 32bit register shows the number of OSC clock per second. +*/ +#define FCH_MISC_REG34 0x34 // HpetClkPeriod +/* +FCH_MISC_REG34 EQU 034h + HpetClkPeriod EQU 0FFFFFFFFh ; default - 0x429B17Eh (14.31818M). +*/ +#define FCH_MISC_REG28 0x28 // ClkDrvSth2 +#define FCH_MISC_REG2C 0x2C +#define FCH_MISC_REG40 0x40 // MiscCntrl for clock only +#define FCH_MISC_REG41 0x41 // MiscCntr2 +#define FCH_MISC_REG42 0x42 // MiscCntr3 +#define FCH_MISC_REG44 0x44 // ValueOnPort80 +#define FCH_MISC_REG50 0x50 // +#define FCH_MISCx50_JTAG_CONTROL_ECO 0xFED80E50ul // +#define FCH_MISCx68_MEMORY_POWER_SAVING_CONTROL 0xFED80E68ul // + +#define FCH_MISC_REG6C 0x6C // EcoBit2 +/* +FCH_MISC_REG40 EQU 040h +*/ + +#define FCH_MISC_REG80 0x80 /**< FCH_MISC_REG80 + * @par + * StrapStatus [15.0] - FCH chip Strap Status + * @li <b>0001</b> - Not USED FWH + * @li <b>0002</b> - Not USED LPC ROM + * @li <b>0004</b> - EC enabled + * @li <b>0008</b> - Reserved + * @li <b>0010</b> - Internal Clock mode + */ +#define FCH_MISC_REGB6 0xB6 // + +#define ChipSysNotUseFWHRom 0x0001 // EcPwm3 pad +#define ChipSysNotUseLpcRom 0x0002 // Inverted version from EcPwm2 pad (default - 1) + // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type. +#define ChipSysEcEnable 0x0004 // Enable Embedded Controller (EC) +#define ChipSysBootFailTmrEn 0x0008 // Enable Watchdog function +#define ChipSysIntClkGen 0x0010 // Select 25Mhz crystal clock or 100Mhz PCI-E clock ** + +#define FCH_MISC_REG84 0x84 // StrapOverride +/* +FCH_MISC_REG84 EQU 084h + Override FWHDisableStrap EQU BIT0 ; Override FWHDiableStrap value from external pin. + Override UseLpcRomStrap EQU BIT1 ; Override UseLpcRomStrap value from external pin. + Override EcEnableStrap EQU BIT2 ; Override EcEnableStrap value from external pin. + Override BootFailTmrEnStrap EQU BIT3 ; Override BootFailTmrEnStrap value from external pin. + Override DefaultModeStrap EQU BIT5 ; Override DefaultModeStrap value from external pin. + Override I2CRomStrap EQU BIT7 ; Override I2CRomStrap value from external pin. + Override ILAAutorunEnBStrap EQU BIT8 ; Override ILAAutorunEnBStrap value from external pin. + Override FcPllBypStrap EQU BIT9 ; Override FcPllBypStrap value from external pin. + Override PciPllBypStrap EQU BIT10 ; Override PciPllBypStrap value from external pin. + Override ShortResetStrap EQU BIT11 ; Override ShortResetStrap value from external pin. + Override FastBif2ClkStrap EQU BIT13 ; Override FastBif2ClkStrap value from external pin + PciRomBootStrap EQU BIT15 ; Override PCI Rom Boot Strap value from external pin + BlinkSlowModestrap EQU BIT16 ; Override Blink Slow mode (100Mhz) from external pin + ClkGenStrap EQU BIT17 ; Override CLKGEN from external pin. + BIF_GEN2_COMPL_Strap EQU BIT18 ; Override BIF_ GEN2_COMPLIANCE strap from external pin. + StrapOverrideEn EQU BIT31 ; Enable override strapping feature. +*/ +#define FCH_MISC_REGC0 0xC0 // CPU_Pstate0 +/* +FCH_MISC_REGC0 EQU 0C0h + Core0_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7 + Core1_PState EQU BIT4+BIT5+BIT6 + Core2_PState EQU BIT8+BIT9+BIT10 + Core3_PState EQU BIT12+BIT13+BIT14 + Core4_PState EQU BIT16++BIT17+BIT18 + Core5_PState EQU BIT20+BIT21+BIT22 + Core6_PState EQU BIT24+BIT25+BIT26 + Core7_PState EQU BIT28+BIT29+BIT30 +*/ +#define FCH_MISC_REGC4 0xC4 // CPU_Pstate1 +/* +FCH_MISC_REGC4 EQU 0C4h + Core8_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7 + Core9_PState EQU BIT4+BIT5+BIT6 + Core10_PState EQU BIT8+BIT9+BIT10 + Core11_PState EQU BIT12+BIT13+BIT14 + Core12_PState EQU BIT16++BIT17+BIT18 + Core13_PState EQU BIT20+BIT21+BIT22 + Core14_PState EQU BIT24+BIT25+BIT26 + Core15_PState EQU BIT28+BIT29+BIT30 +*/ +#define FCH_MISC_REGD0 0xD0 // CPU_Cstate0 +/* +FCH_MISC_REGD0 EQU 0D0h + Core0_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7 + Core1_CState EQU BIT4+BIT5+BIT6 + Core2_CState EQU BIT8+BIT9+BIT10 + Core3_CState EQU BIT12+BIT13+BIT14 + Core4_CState EQU BIT16++BIT17+BIT18 + Core5_CState EQU BIT20+BIT21+BIT22 + Core6_CState EQU BIT24+BIT25+BIT26 + Core7_CState EQU BIT28+BIT29+BIT30 +*/ +#define FCH_MISC_REGD4 0xD4 // CPU_Cstate1 +/* +FCH_MISC_REGD4 EQU 0D4h + Core8_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7 + Core9_CState EQU BIT4+BIT5+BIT6 + Core10_CState EQU BIT8+BIT9+BIT10 + Core11_CState EQU BIT12+BIT13+BIT14 + Core12_CState EQU BIT16++BIT17+BIT18 + Core13_CState EQU BIT20+BIT21+BIT22 + Core14_CState EQU BIT24+BIT25+BIT26 + Core15_CState EQU BIT28+BIT29+BIT30 +*/ +#define FCH_MISC_REGF0 0xF0 // SataPortSts +/* +FCH_MISC_REGF0 EQU 0F0h + Port0Sts EQU BIT0 ; The selected status of Port 0. + Port1Sts EQU BIT1 ; The selected status of Port 1 + Port2Sts EQU BIT2 ; The selected status of Port 2. + Port3Sts EQU BIT3 ; The selected status of Port 3 + Port4Sts EQU BIT4 ; The selected status of Port 4. + Port5Sts EQU BIT5 ; The selected status of Port 5 + SataPortSel EQU BIT24+BIT25 ; 00 - Select "led" for Port 0 to 5 + ; 01 - Select "delete" for Port 0 to 5 + ; 10 - Select "err" for Port 0 to 5 + ; 11 - Select "led" for Port 0 to 5 +*/ + +// +// FCH MMIO Base (SERIAL_DEBUG_BASE) +// offset : 0x1000 +// +#define FCH_SDB_REG00 0x00 // +#define FCH_SDB_REG74 0x74 + +#define FCH_RTC_REG00 0x00 // Seconds - RW +#define FCH_RTC_REG01 0x01 // Seconds Alarm - RW +#define FCH_RTC_REG02 0x02 // Minutes - RW +#define FCH_RTC_REG03 0x03 // Minutes Alarm - RW +#define FCH_RTC_REG04 0x04 // ours - RW +#define FCH_RTC_REG05 0x05 // ours Alarm- RW +#define FCH_RTC_REG06 0x06 // Day of Week - RW +#define FCH_RTC_REG07 0x07 // Date of Mont - RW +#define FCH_RTC_REG08 0x08 // Mont - RW +#define FCH_RTC_REG09 0x09 // Year - RW +#define FCH_RTC_REG0A 0x0A // Register A - RW +#define FCH_RTC_REG0B 0x0B // Register B - RW +#define FCH_RTC_REG0C 0x0C // Register C - R +#define FCH_RTC_REG0D 0x0D // DateAlarm - RW +#define FCH_RTC_REG32 0x32 // AltCentury - RW +#define FCH_RTC_REG48 0x48 // Century - RW +#define FCH_RTC_REG50 0x50 // Extended RAM Address Port - RW +#define FCH_RTC_REG53 0x53 // Extended RAM Data Port - RW +#define FCH_RTC_REG7E 0x7E // RTC Time Clear - RW +#define FCH_RTC_REG7F 0x7F // RTC RAM Enable - RW + +#define FCH_ECMOS_REG00 0x00 // scratch - reg +//;BIT0=0 AsicDebug is enabled +//;BIT1=0 SLT S3 runs +#define FCH_ECMOS_REG01 0x01 +#define FCH_ECMOS_REG02 0x02 +#define FCH_ECMOS_REG03 0x03 +#define FCH_ECMOS_REG04 0x04 +#define FCH_ECMOS_REG05 0x05 +#define FCH_ECMOS_REG06 0x06 +#define FCH_ECMOS_REG07 0x07 +#define FCH_ECMOS_REG08 0x08 // save 32BIT Physical address of Config structure +#define FCH_ECMOS_REG09 0x09 +#define FCH_ECMOS_REG0A 0x0A +#define FCH_ECMOS_REG0B 0x0B + +#define FCH_ECMOS_REG0C 0x0C //;save MODULE_ID +#define FCH_ECMOS_REG0D 0x0D //;Reserve for NB + +// +// FCH SMI Base (FCH_SMI_BASE) +// offset : 0x0200 +// +#define FCH_SMIx0C_Level 0xFED8020Cul // Level +#define FCH_SMIx58_EHCI_WAKE 0xFED80258ul // EHCI WAKE +#define FCH_SMIx78_XHCI_WAKE 0xFED80278ul // XHCI WAKE + +#define FCH_SMIx88_SmiStatus2 0xFED80288ul // SmiStatus2 +#define FCH_SMIx88_SmiStatus2_UsbSmiEvent76 ( 1 << 12 ) + +// +// FCH PMIO Base (FCH_PMIO_BASE) +// offset : 0x0300 +// +#define FCH_PMIOx10_Power_Reset_Config 0xFED80310ul //Power Reset Config +#define FCH_PMIOx10_Power_Reset_Config_ToggleAllPwrGoodOnCf9 (1 << 1) + +#define FCH_PMIOx74_AcpiConfig 0xFED80374ul // AcpiConfig +#define FCH_PMIOx74_AcpiConfig_PwnBtnEn (1 << 8) +#define FCH_PMIOx74_AcpiConfig_AcpiReducedHwEn (1 << 9) + +#define FCH_PMIOxC0_S5ResetStatus 0xFED803C0ul // S5ResetStatus +#define FCH_PMIOxC0_S5ResetStatus_ThermalTrip (1 << 0) +#define FCH_PMIOxC0_S5ResetStatus_FourSecondPwrBtn (1 << 1) +#define FCH_PMIOxC0_S5ResetStatus_S_Status (0x3ff | (1 << 20)) +#define FCH_PMIOxC0_S5ResetStatus_All_Status 0x3FFF03FFul + +#define FCH_PMxC8_Misc 0xFED803C8ul // Misc +#define FCH_PMxC8_Misc_UseAcpiStraps (1 << 4) + +#define FCH_PMxE8_SDFlashCntrl 0xFED803E8ul // SDFlashCntrl +#define FCH_PMxE8_SDFlashCntrl_SdCd2Acpi (1 << 5) +// +// FCH MISC Base (FCH_MISC_BASE) +// offset : 0x0E00 +// +#define FCH_MISCx28_ClkDrvStr2 0xFED80E28ul // ClkDrvStr2 + +#define FCH_MISCx40_MiscClkCntl1 0xFED80E40ul // MiscClkCntl1 +#define FCH_MISCx40_MiscClkCntl1_CG1PLL_FBDIV_Test (1 << 26) + +#define FCH_MISCx50_JTAG_Control_ECO_bits 0xFED80E50ul // JTAG_Control_ECO_bits +#define FCH_MISCx50_JTAG_Control_ECO_bits_BIT12 (1 << 12) +#define FCH_MISCx50_JTAG_Control_ECO_bits_BIT16 (1 << 16) + +// FCH GPIO +// offset : 0x1500 +// +#define FCH_GPIOx018_AGPIO6_LDT_RST_L 0xFED81518ul // +#define FCH_GPIOx10C_DEVSLP0_EGPIO67 0xFED8160Cul // + +// FCH XHC PM (FCH_XHC_PM) +// offset : 0x1C00 +// +#define FCH_XHC_PMx00_Configure0 0xFED81C00ul // +#define FCH_XHC_PMx00_Configure0_XHC_SMIB_EN BIT21 +#define FCH_XHC_PMx10_Xhc_Memory_Configure 0xFED81C10ul // +#define FCH_XHC_PMx18_Usb20_Link_Status 0xFED81C18ul // +#define FCH_XHC_PMx20_Usb20_Wake_Control 0xFED81C20ul // +#define FCH_XHC_PMx24_Misc0 0xFED81C24ul // +#define FCH_XHC_PMx28_Misc1 0xFED81C28ul // +#define FCH_XHC_PMx2C_Misc2 0xFED81C2Cul // +#define FCH_XHC_PMx30_Xhci10_Enable 0xFED81C30ul // +#define FCH_XHC_PMx60_xHC_Battery_Charger_Enable 0xFED81C60ul // + + + + +// FCH AOAC Base (FCH_AOAC_BASE) +// offset : 0x1E00 +// +#define FCH_AOACx40_D3_CONTROL 0xFED81E40ul // +#define FCH_AOACx41_D3_STATUS 0xFED81E40ul // +#define FCH_AOACx5E_SATA_D3_CONTROL 0xFED81E5Eul // +#define FCH_AOACx6E_USB3_D3_CONTROL 0xFED81E6Eul // +#define FCH_AOACx70_SD_D3_CONTROL 0xFED81E70ul // +#define FCH_AOACx7A_IMC_D3_CONTROL 0xFED81E7Aul // +#define FCH_AOACx88Shadow_Register_SRAM_Addr 0xFED81E88ul // +#define FCH_AOACx8CShadow_Register_SRAM_Data 0xFED81E8Cul // +#define FCH_AOACx94S013_CONTROL 0xFED81E94ul // +#define FCH_AOACx94S013_CONTROL_ARBITER_DIS (1 << 14) +#define FCH_AOACx94S013_CONTROL_INTERRUPT_DIS (1 << 15) +#define FCH_AOACx9C_Shadow_Timer_Control 0xFED81E9Cul // +#define FCH_AOACx9C_Shadow_Timer_Control_ShadowHpetEn (1 << 0) // +#define FCH_AOACx9C_Shadow_Timer_Control_ShadowAcpiTimerEn (1 << 1) // + +#define FCH_AOACxA0_PwrGood_Control 0xFED81EA0ul // + +#define FCH_AOAC_REG00 0x00 // PerfMonControl +#define FCH_AOAC_REG04 0x04 // PerfMonTimeLimit +#define FCH_AOAC_REG08 0x08 // PerfMonWeight[3:0] +#define FCH_AOAC_REG0C 0x0C // PerfMonWeight[7:4] +#define FCH_AOAC_REG10 0x10 // PerfMonTrafficCnt[1:0] +#define FCH_AOAC_REG14 0x14 // PerfMonTrafficCnt[3:2] +#define FCH_AOAC_REG18 0x18 // PerfMonTrafficCnt[5:4] +#define FCH_AOAC_REG1C 0x1C // PerfMonTrafficCnt[7:6] +#define FCH_AOAC_REG20 0x20 // PerfMonTrafficCntAll +#define FCH_AOAC_REG24 0x24 // PerfMonIntrCnt +#define FCH_AOAC_REG28 0x28 // +#define FCH_AOAC_REG2C 0x2C // +#define FCH_AOAC_REG30 0x30 // Alternative HPET Timer +#define FCH_AOAC_REG34 0x34 // Alternative HPET Timer (HIGH 32BITS) +#define FCH_AOAC_REG38 0x38 // Alternative HPET Alarm +#define FCH_AOAC_REG3C 0x3C // Alternative HPET Alarm (HIGH 32BITS) +/* +FCH_AOAC_REG4X-7x Control field +*/ +#define AOAC_TARGET_DEVICE_STATE (BIT0 + BIT1) // TargetedDeviceState - + // 00 - D0 un-initialized + // 01 - D0 initialized + // 10 - D1/D2/D3hot + // 11 - D3cold + // +#define AOAC_DEVICE_STATE BIT2 // DeviceState + // 0 - Device power is removed + // 1 - Device power is applied +#define AOAC_PWR_ON_DEV BIT3 // PwrOnDev - + // If IsSwControl==0, software can write this bit to trigger a HW + // controlled power-down or reset sequence to the device. + // 0 - Power down the device. + // 1 - Power up the device. + // +#define AOAC_SW_PWR_ON_RSTB BIT4 // SwPwrOnRstB - + // + // 0 - PwrRstB is asserted to the device if IsSwControl==1. + // 1 - 1=PwrRstB is de-asserted to the device if IsSwControl==1. + // +#define AOAC_SW_REF_CLK_OK BIT5 // SwRefClkOk - + // + // 0 - 0=RefClkOk is de-asserted to the device if IsSwControl==1. + // 1 - RefClkOk is asserted to the device if IsSwControl==1. + // +#define AOAC_SW_RST_B BIT6 // SwRstB - + // 0 - RstB is asserted to the device if IsSwControl==1. + // 1 - RstB is deasserted to the device if IsSwControl==1. + // +#define AOAC_IS_SW_CONTROL BIT7 // IsSwControl + // To avoid glitch on the reset signals, software must set bit IsSwControl first before programming bit + // SwPwrOnRstB, SwRefClkOk and SwRstB. + // 0 - Hardware controls control signals (PwrRstB, RefClkOk, RstB) to the device. + // 1 - Software controls control signals (PwrRstB, RefClkOk, RstB) to the device. + // +/* +FCH_AOAC_REG4X-7x State field +*/ +#define A0AC_PWR_RST_STATE BIT0 +#define AOAC_RST_CLK_OK_STATE BIT1 +#define AOAC_RST_B_STATE BIT2 +#define AOAC_DEV_OFF_GATING_STATE BIT3 +#define AOAC_D3COLD BIT4 +#define AOAC_CLK_OK_STATE BIT5 +#define AOAC_STAT0 BIT6 +#define AOAC_STAT1 BIT7 +#define FCH_AOAC_REG40 0x40 // ClkGen Control +#define FCH_AOAC_REG41 0x41 // ClkGen State +#define FCH_AOAC_REG42 0x42 // AB Control +#define FCH_AOAC_REG43 0x43 // AB State +#define FCH_AOAC_REG44 0x44 // ACPI S0 Control +#define FCH_AOAC_REG45 0x45 // ACPI S0 State +#define FCH_AOAC_REG46 0x46 // ACPI S5 Control +#define FCH_AOAC_REG47 0x47 // ACPI S5 State +#define FCH_AOAC_REG48 0x48 // LPC Control +#define FCH_AOAC_REG49 0x49 // LPC State +#define FCH_AOAC_REG4A 0x4A // I_2_C 0 Control +#define FCH_AOAC_REG4B 0x4B // I_2_C 0 State +#define FCH_AOAC_REG4C 0x4C // I_2_C 1 Control +#define FCH_AOAC_REG4D 0x4D // I_2_C 1 State +#define FCH_AOAC_REG4E 0x4E // I_2_C 2 Control +#define FCH_AOAC_REG4F 0x4F // I_2_C 2 State +#define FCH_AOAC_REG50 0x50 // I_2_C 3 Control +#define FCH_AOAC_REG51 0x51 // I_2_C 3 State + +#define FCH_AOAC_REG56 0x56 // UART0 Control +#define FCH_AOAC_REG57 0x57 // UART0 State +#define FCH_AOAC_REG58 0x58 // UART1 Control +#define FCH_AOAC_REG59 0x59 // UART1 State + +#define FCH_AOAC_REG5E 0x5E // SATA Control +#define FCH_AOAC_REG5F 0x5F // SATA State + +#define FCH_AOAC_REG62 0x62 // AMBA Control +#define FCH_AOAC_REG63 0x63 // AMBA State +#define FCH_AOAC_REG64 0x64 // USB2 Control +#define FCH_AOAC_REG65 0x65 // USB2 State + +#define FCH_AOAC_REG6E 0x6E // USB3 Control +#define FCH_AOAC_REG6F 0x6F // USB3 State +#define FCH_AOAC_REG70 0x70 // SD Control +#define FCH_AOAC_REG71 0x71 // SD State + +#define FCH_AOAC_REG76 0x76 // eSPI Control +#define FCH_AOAC_REG77 0x77 // eSPI State + +#define FCH_AOAC_REG7A 0x7A // IMC Control +#define FCH_AOAC_REG7B 0x7B // IMC State +#define FCH_AOAC_REG7C 0x7C // NB Control +#define FCH_AOAC_REG7D 0x7D // NB State +#define FCH_AOAC_REG7E 0x7E // APU Control +#define FCH_AOAC_REG7F 0x7F // APU State +#define FCH_AOAC_REG80 0x80 // +#define FCH_AOAC_REG84 0x84 // +#define FCH_AOAC_REG88 0x88 // +#define FCH_AOAC_REG8C 0x8C // +#define FCH_AOAC_REG90 0x90 // +#define FCH_AOAC_REG94 0x94 // +#define FCH_AOAC_REG98 0x98 // +#define FCH_AOAC_REG9C 0x9C // +#define FCH_AOAC_REGA0 0xA0 // +#define FCH_AOAC_REGA4 0xA4 // +#define FCH_AOAC_REGA8 0xA8 // +#define FCH_AOAC_REGAC 0xAC // +#define FCH_AOAC_REGB0 0xB0 // +#define FCH_AOAC_REGB4 0xB4 // +#define FCH_AOAC_REGB8 0xB8 // +#define FCH_AOAC_REGBC 0xBC // +#define FCH_AOAC_REGC0 0xC0 // +#define FCH_AOAC_REGC4 0xC4 // +#define FCH_AOAC_REGC8 0xC8 // +#define FCH_AOAC_REGCC 0xCC // +#define FCH_AOAC_REGD0 0xD0 // +#define FCH_AOAC_REGD4 0xD4 // +#define FCH_AOAC_REGD8 0xD8 // +#define FCH_AOAC_REGDC 0xDC // +#define FCH_AOAC_REGE0 0xE0 // +#define FCH_AOAC_REGE4 0xE4 // +#define FCH_AOAC_REGE8 0xE8 // +#define FCH_AOAC_REGEC 0xEC // +#define FCH_AOAC_REGF0 0xF0 // +#define FCH_AOAC_REGF4 0xF4 // +#define FCH_AOAC_REGF8 0xF8 // +#define FCH_AOAC_REGFC 0xFC // +#define FCH_AOACx98S013_DEBUG 0xFED81E98ul // +#define FCH_AOACx98S013_DEBUG_BYPASS_SHDW_TMR (1 << 8) +#define FCH_AOACx98S013_DEBUG_BYPASS_SHDW_REG (1 << 9) +//Set S0I3_BypassShdwTmr in AOAC offset 0x98 bit 8 to 0 +//Set S0I3_BypassShdwReg in AOAC offset 0x98 bit 9 to 1 + +#define FCH_AOACx9CS013_TIMER_CONTROL 0xFED81E9Cul // +#define FCH_AOACx9CS013_TIMER_CONTROL_SHADOW_HPET_EN (1 << 0) +#define FCH_AOACx9CS013_TIMER_CONTROL_EARLY_COUNT_UNIT (1 << 2) +#define FCH_AOACx9CS013_TIMER_CONTROL_EARLY_COUNT_MASK (0xff << 8) +#define FCH_AOACx9CS013_TIMER_CONTROL_EARLY_COUNT_VALUE (0x23 << 8) +//Set ShadowHPETEn in AOAC offset 0x9C bit 0 to 1 +//Set EarlyCountUnit in AOAC offset 0x9C bit 2 to 1 +//Program EarlyCount in AOAC offset 0x9C bit[15:8]. (please set 0x23 for now) + + +#define FCH_AL2AHBx10_CONTROL 0xFEDC0010ul // +#define FCH_AL2AHBx10_CONTROL_CLOCK_GATE_EN (1 << 1) + +#define FCH_AL2AHBx30_HCLK_CONTROL 0xFEDC0030ul // +#define FCH_AL2AHBx30_HCLK_CONTROL_CLOCK_GATE_EN (1 << 1) + +#define FCH_IOMAP_REG00 0x000 // Dma_C 0 +#define FCH_IOMAP_REG02 0x002 // Dma_C 1 +#define FCH_IOMAP_REG04 0x004 // Dma_C 2 +#define FCH_IOMAP_REG06 0x006 // Dma_C 3 +#define FCH_IOMAP_REG08 0x008 // Dma_Status +#define FCH_IOMAP_REG09 0x009 // Dma_WriteRest +#define FCH_IOMAP_REG0A 0x00A // Dma_WriteMask +#define FCH_IOMAP_REG0B 0x00B // Dma_WriteMode +#define FCH_IOMAP_REG0C 0x00C // Dma_Clear +#define FCH_IOMAP_REG0D 0x00D // Dma_MasterClr +#define FCH_IOMAP_REG0E 0x00E // Dma_ClrMask +#define FCH_IOMAP_REG0F 0x00F // Dma_AllMask +#define FCH_IOMAP_REG20 0x020 // IntrCntrlReg1 +#define FCH_IOMAP_REG21 0x021 // IntrCntrlReg2 +#define FCH_IOMAP_REG40 0x040 // TimerC0 +#define FCH_IOMAP_REG41 0x041 // TimerC1 +#define FCH_IOMAP_REG42 0x042 // TimerC2 +#define FCH_IOMAP_REG43 0x043 // Tmr1CntrlWord +#define FCH_IOMAP_REG61 0x061 // Nmi_Status +#define FCH_IOMAP_REG70 0x070 // Nmi_Enable +#define FCH_IOMAP_REG71 0x071 // RtcDataPort +#define FCH_IOMAP_REG72 0x072 // AlternatRtcAddrPort +#define FCH_IOMAP_REG73 0x073 // AlternatRtcDataPort +#define FCH_IOMAP_REG80 0x080 // Dma_Page_Reserved0 +#define FCH_IOMAP_REG81 0x081 // Dma_PageC2 +#define FCH_IOMAP_REG82 0x082 // Dma_PageC3 +#define FCH_IOMAP_REG83 0x083 // Dma_PageC1 +#define FCH_IOMAP_REG84 0x084 // Dma_Page_Reserved1 +#define FCH_IOMAP_REG85 0x085 // Dma_Page_Reserved2 +#define FCH_IOMAP_REG86 0x086 // Dma_Page_Reserved3 +#define FCH_IOMAP_REG87 0x087 // Dma_PageC0 +#define FCH_IOMAP_REG88 0x088 // Dma_Page_Reserved4 +#define FCH_IOMAP_REG89 0x089 // Dma_PageC6 +#define FCH_IOMAP_REG8A 0x08A // Dma_PageC7 +#define FCH_IOMAP_REG8B 0x08B // Dma_PageC5 +#define FCH_IOMAP_REG8C 0x08C // Dma_Page_Reserved5 +#define FCH_IOMAP_REG8D 0x08D // Dma_Page_Reserved6 +#define FCH_IOMAP_REG8E 0x08E // Dma_Page_Reserved7 +#define FCH_IOMAP_REG8F 0x08F // Dma_Refres +#define FCH_IOMAP_REG92 0x092 // FastInit +#define FCH_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1 +#define FCH_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2 +#define FCH_IOMAP_REGC0 0x0C0 // Dma2_C4Addr +#define FCH_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt +#define FCH_IOMAP_REGC4 0x0C4 // Dma2_C5Addr +#define FCH_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt +#define FCH_IOMAP_REGC8 0x0C8 // Dma2_C6Addr +#define FCH_IOMAP_REGCA 0x0CA // Dma2_C6Cnt +#define FCH_IOMAP_REGCC 0x0CC // Dma2_C7Addr +#define FCH_IOMAP_REGCE 0x0CE // Dma2_C7Cnt +#define FCH_IOMAP_REGD0 0x0D0 // Dma_Status +#define FCH_IOMAP_REGD2 0x0D2 // Dma_WriteRest +#define FCH_IOMAP_REGD4 0x0D4 // Dma_WriteMask +#define FCH_IOMAP_REGD6 0x0D6 // Dma_WriteMode +#define FCH_IOMAP_REGD8 0x0D8 // Dma_Clear +#define FCH_IOMAP_REGDA 0x0DA // Dma_Clear +#define FCH_IOMAP_REGDC 0x0DC // Dma_ClrMask +#define FCH_IOMAP_REGDE 0x0DE // Dma_ClrMask +#define FCH_IOMAP_REGED 0x0ED // DUMMY IO PORT +#define FCH_IOMAP_REGF0 0x0F0 // NCP_Error +#define FCH_IOMAP_REG40B 0x040B // DMA1_Extend +#define FCH_IOMAP_REG4D0 0x04D0 // IntrEdgeControl +#define FCH_IOMAP_REG4D6 0x04D6 // DMA2_Extend +#define FCH_IOMAP_REGC00 0x0C00 // Pci_Intr_Index +#define FCH_IOMAP_REGC01 0x0C01 // Pci_Intr_Data +#define FCH_IOMAP_REGC14 0x0C14 // Pci_Error +#define FCH_IOMAP_REGC50 0x0C50 // CMIndex +#define FCH_IOMAP_REGC51 0x0C51 // CMData +#define FCH_IOMAP_REGC52 0x0C52 // GpmPort +#define FCH_IOMAP_REGC6F 0x0C6F // Isa_Misc +#define FCH_IOMAP_REGCD0 0x0CD0 // PMio2_Index +#define FCH_IOMAP_REGCD1 0x0CD1 // PMio2_Data +#define FCH_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index +#define FCH_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data +#define FCH_IOMAP_REGCD6 0x0CD6 // PM_Index +#define FCH_IOMAP_REGCD7 0x0CD7 // PM_Data +#define FCH_IOMAP_REGCF9 0x0CF9 // CF9Rst reg + +#define FCH_IRQ_INTA 0x00 // INTA# +#define FCH_IRQ_INTB 0x01 // INTB# +#define FCH_IRQ_INTC 0x02 // INTC# +#define FCH_IRQ_INTD 0x03 // INTD# +#define FCH_IRQ_INTE 0x04 // INTE# +#define FCH_IRQ_INTF 0x05 // INTF# +#define FCH_IRQ_INTG 0x06 // INTG# +#define FCH_IRQ_INTH 0x07 // INTH# +#define FCH_IRQ_SCI 0x10 // SCI +#define FCH_IRQ_SMBUS0 0x11 // SMBUS0 +#define FCH_IRQ_ASF 0x12 // ASF +#define FCH_IRQ_HDAUDIO 0x13 // HD Audio +#define FCH_IRQ_FC 0x14 // FC +#define FCH_IRQ_GEC 0x15 // GEC +#define FCH_IRQ_SD 0x17 // SD +#define FCH_IRQ_IMCINT0 0x20 // IMC INT0 +#define FCH_IRQ_IMCINT1 0x21 // IMC INT1 +#define FCH_IRQ_IMCINT2 0x22 // IMC INT2 +#define FCH_IRQ_IMCINT3 0x23 // IMC INT3 +#define FCH_IRQ_IMCINT4 0x24 // IMC INT4 +#define FCH_IRQ_IMCINT5 0x25 // IMC INT5 +#define FCH_IRQ_USB18INTA 0x30 // Dev 18 (USB) INTA# +#define FCH_IRQ_USB18INTB 0x31 // Dev 18 (USB) INTB# +#define FCH_IRQ_USB19INTA 0x32 // Dev 19 (USB) INTA# +#define FCH_IRQ_USB19INTB 0x33 // Dev 19 (USB) INTB# +#define FCH_IRQ_USB22INTA 0x34 // Dev 22 (USB) INTA# +#define FCH_IRQ_USB22INTB 0x35 // Dev 22 (USB) INTB# +#define FCH_IRQ_USB20INTC 0x36 // Dev 20 (USB) INTC# +#define FCH_IRQ_IDE 0x40 // IDE pci interrupt +#define FCH_IRQ_SATA 0x41 // SATA pci interrupt +#define FCH_IRQ_GPPINT0 0x50 // Gpp Int0 +#define FCH_IRQ_GPPINT1 0x51 // Gpp Int1 +#define FCH_IRQ_GPPINT2 0x52 // Gpp Int2 +#define FCH_IRQ_GPPINT3 0x53 // Gpp Int3 +#define FCH_IRQ_GPIO 0x62 // GPIO Controller +#define FCH_IRQ_I2C0 0x70 // I2C0 Controller +#define FCH_IRQ_I2C1 0x71 // I2C1 Controller +#define FCH_IRQ_I2C2 0x72 // I2C2 Controller +#define FCH_IRQ_I2C3 0x73 // I2C3 Controller +#define FCH_IRQ_UART0 0x74 // UART0 Controller +#define FCH_IRQ_UART1 0x75 // UART1 Controller +#define FCH_IRQ_IOAPIC 0x80 // Select IRQ routing to IoApic mode +#define FCH_IRQ_PIC 0x00 // Select IRQ routing to PIC mode + +#define FCH_IRQ_INTERNAL_SHARE 0x07 // Fch Internal Shared IRQ +#define FCH_IRQ_GPIO_IRQ FCH_IRQ_INTERNAL_SHARE +#define FCH_IRQ_I2C0_IRQ 3 +#define FCH_IRQ_I2C1_IRQ 15 +#define FCH_IRQ_I2C2_IRQ 6 +#define FCH_IRQ_I2C3_IRQ 14 +#define FCH_IRQ_UART0_IRQ 10 +#define FCH_IRQ_UART1_IRQ 11 + + +#define FCH_SPI_MMIO_REG00 0x00 //SPI_ +#define FCH_SPI_OPCODE 0x000000FFl // +#define FCH_SPI_TX_COUNT 0x00000F00l // +#define FCH_SPI_RX_COUNT 0x0000F000l // +#define FCH_SPI_EXEC_OPCODE 0x00010000l // +#define FCH_SPI_FIFO_PTR_CRL 0x00100000l // +#define FCH_SPI_FIFO_PTR_INC 0x00200000l // +#define FCH_SPI_BUSY 0x80000000l // +#define FCH_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register +#define FCH_SPI_PARAMETER 0x000000FFl // +#define FCH_SPI_FIFO_PTR 0x00000700l // +#define FCH_SPI_BYTE_PROGRAM 0xFF000000l // +#define FCH_SPI_MMIO_REG1C 0x1C // +#define FCH_SPI_RETRY_TIMES 0x3 // + +#define FCH_SPI_MMIO_REG1D 0x1D // +#define FCH_SPI_MMIO_REG1E 0x1E // +#define FCH_SPI_MMIO_REG1F 0x1F // +#define FCH_SPI_MMIO_REG4E 0x4E // + +#define FCH_SPI_MMIO_REG1F_X05_TX_BYTE_COUNT 0x05 // +#define FCH_SPI_MMIO_REG1F_X06_RX_BYTE_COUNT 0x06 // + +#define FCH_SPI_MMIO_REG20 0x20 // +#define FCH_SPI_MMIO_REG22 0x22 // +#define FCH_SPI_MMIO_REG2C 0x2C // +#define FCH_SPI_MMIO_REG38 0x38 // +#define FCH_SPI_MMIO_REG3C 0x3C // + +#define FCH_SPI_MMIO_REG45_CMDCODE 0x45 // +#define FCH_SPI_MMIO_REG47_CMDTRIGGER 0x47 // +#define FCH_SPI_MMIO_REG48_TXBYTECOUNT 0x48 // +#define FCH_SPI_MMIO_REG4B_RXBYTECOUNT 0x4B // +#define FCH_SPI_MMIO_REG4C_SPISTATUS 0x4C // +#define FCH_SPI_MMIO_REG80_FIFO 0x80 // + +#define FCH_SPI_MODE_FAST 0x7 // +#define FCH_SPI_MODE_NORMAL 0x6 // +#define FCH_SPI_MODE_QUAL_144 0x5 // +#define FCH_SPI_MODE_QUAL_122 0x4 // +#define FCH_SPI_MODE_QUAL_114 0x3 // +#define FCH_SPI_MODE_QUAL_112 0x2 // + +#define FCH_SPI_DEVICE_MODE_DIS 0x7 // +#define FCH_SPI_DEVICE_MODE_144 0x4 // +#define FCH_SPI_DEVICE_MODE_114 0x3 // +#define FCH_SPI_DEVICE_MODE_122 0x2 // +#define FCH_SPI_DEVICE_MODE_112 0x1 // +#define FCH_SPI_DEVICE_MODE_FAST 0x0 // + +#define FCH_SPI_SPEED_16M 0x4 // +#define FCH_SPI_SPEED_22M 0x3 // +#define FCH_SPI_SPEED_33M 0x2 // +#define FCH_SPI_SPEED_66M 0x1 // +#define FCH_SPI_SPEED_100M 0x5 // + +#define AMD_NB_REG78 0x78 +#define AMD_NB_SCRATCH AMD_NB_REG78 +#define MailBoxPort 0x3E + +#define MAX_LT_POLLINGS 0x4000 +#define SMI_TIMER_ENABLE BIT15 + +#define ACPIMMIO32(x) (*(volatile UINT32*)(UINTN)(x)) +#define ACPIMMIO16(x) (*(volatile UINT16*)(UINTN)(x)) +#define ACPIMMIO8(x) (*(volatile UINT8*)(UINTN)(x)) + +#define U3PLL_LOCK BIT7 +#define U3PLL_RESET BIT8 +#define U3PHY_RESET BIT9 +#define U3CORE_RESET BIT10 +#define XHC0_FUNC_RESET BIT11 +#define XHC1_FUNC_RESET BIT12 + +#define XHCI_ACPI_MMIO_AMD_REG00 0x00 +#define XHCI_ACPI_MMIO_AMD_REG04 0x04 +#define XHCI_ACPI_MMIO_AMD_REG08 0x08 +#define XHCI_ACPI_MMIO_AMD_REG10 0x10 +#define XHCI_ACPI_MMIO_AMD_REG14 0x14 +#define XHCI_ACPI_MMIO_AMD_REG20 0x20 +#define XHCI_ACPI_MMIO_AMD_REG24 0x24 +#define XHCI_ACPI_MMIO_AMD_REG28 0x28 +#define XHCI_ACPI_MMIO_AMD_REG30 0x30 +#define XHCI_ACPI_MMIO_AMD_REG40 0x40 +#define XHCI_ACPI_MMIO_AMD_REG48 0x48 // USB3.0_Ind_REG Index +#define XHCI_ACPI_MMIO_AMD_REG4C 0x4C // USB2.0_Ind_REG Data +#define XHCI_ACPI_MMIO_AMD_REG8C 0x8C +#define XHCI_ACPI_MMIO_AMD_REG90 0x90 // adaptation timer settings +#define XHCI_ACPI_MMIO_AMD_REG98 0x98 +#define XHCI_ACPI_MMIO_AMD_REGA0 0xA0 // BAR 0 +#define XHCI_ACPI_MMIO_AMD_REGA4 0xA4 // BAR 1 +#define XHCI_ACPI_MMIO_AMD_REGA8 0xA8 // BAR 2 +#define XHCI_ACPI_MMIO_AMD_REGB0 0xB0 // SPI_Valid_Base. +#define XHCI_ACPI_MMIO_AMD_REGC0 0xC0 // Firmware starting offset for coping +#define XHCI_ACPI_MMIO_AMD_REGB4 0xB4 +#define XHCI_ACPI_MMIO_AMD_REGD0 0xD0 + +#define FCH_XHCI_REG48 0x48 // XHCI IND_REG Index registers +#define FCH_XHCI_REG4C 0x4C // XHCI IND_REG Data registers + +#define FCH_XHCI_IND60_BASE 0x40000000ul // + +#define FCH_XHCI_IND60_REG00 FCH_XHCI_IND60_BASE + 0x00 // +#define FCH_XHCI_IND60_REG04 FCH_XHCI_IND60_BASE + 0x04 // +#define FCH_XHCI_IND60_REG08 FCH_XHCI_IND60_BASE + 0x08 // +#define FCH_XHCI_IND60_REG0C FCH_XHCI_IND60_BASE + 0x0C // +#define FCH_XHCI_IND60_REG18 FCH_XHCI_IND60_BASE + 0x18 // +#define FCH_XHCI_IND60_REG48 FCH_XHCI_IND60_BASE + 0x48 // +#define FCH_XHCI_IND60_REG50 FCH_XHCI_IND60_BASE + 0x50 // +#define FCH_XHCI_IND60_REG54 FCH_XHCI_IND60_BASE + 0x54 // +#define FCH_XHCI_IND60_REG58 FCH_XHCI_IND60_BASE + 0x58 // +#define FCH_XHCI_IND60_REG5C FCH_XHCI_IND60_BASE + 0x5C // +#define FCH_XHCI_IND60_REG68 FCH_XHCI_IND60_BASE + 0x68 // +#define FCH_XHCI_IND60_REG6C FCH_XHCI_IND60_BASE + 0x6C // + +#define FCH_XHCI_IND_REG00 0x00 // +#define FCH_XHCI_IND_REG04 0x04 // +#define FCH_XHCI_IND_REG48 0x48 // +#define FCH_XHCI_IND_REG54 0x54 // +#define FCH_XHCI_IND_REG88 0x88 // +#define FCH_XHCI_IND_REG94 0x94 // adaptation mode settings +#define FCH_XHCI_IND_REG98 0x98 // CR phase and frequency filter settings +#define FCH_XHCI_IND_REGC8 0xC8 // +#define FCH_XHCI_IND_REGD4 0xD4 // adaptation mode settings +#define FCH_XHCI_IND_REGD8 0xD8 // CR phase and frequency filter settings +#define FCH_XHCI_IND_REG100 0x100 // +#define FCH_XHCI_IND_REG120 0x120 // +#define FCH_XHCI_IND_REG128 0x128 // +#define FCH_XHCI_IND_REG200 0x200 // +#define FCH_XHCI_IND_REG240 0x240 // +#define FCH_XHCI_IND_REG280 0x280 // +#define FCH_XHCI_IND_REG2C0 0x2C0 // +#define MAX_XHCI_PORTS 0x04 + +//SMBUS +#define FCH_SMB_IOREG00 0x00 // SMBusStatus +#define FCH_SMB_IOREG01 0x01 // SMBusSlaveStatus +#define FCH_SMB_IOREG02 0x02 // SMBusControl +#define FCH_SMB_IOREG03 0x03 // SMBusHostCmd +#define FCH_SMB_IOREG04 0x04 // SMBusAddress +#define FCH_SMB_IOREG05 0x05 // SMBusData0 +#define FCH_SMB_IOREG06 0x06 // SMBusData1 +#define FCH_SMB_IOREG07 0x07 // SMBusBlockData +#define FCH_SMB_IOREG08 0x08 // SMBusSlaveControl +#define FCH_SMB_IOREG14 0x14 // SMBusAutoPoll +#define FCH_SMB_IOREG16 0x16 // SMBusPausePoll +#define FCH_SMB_IOREG17 0x17 // SMBusHostCmd2 + +#define FCH_SMB_CMD_QUICK 0x00 << 2 // Quick Read or Write +#define FCH_SMB_CMD_BYTE 0x01 << 2 // Byte Read or Write +#define FCH_SMB_CMD_BYTE_DATA 0x02 << 2 // Byte Data Read or Write +#define FCH_SMB_CMD_WORD_DATA 0x03 << 2 // Word Data Read or Write +#define FCH_SMB_CMD_BLOCK 0x05 << 2 // Block Read or Write + +#define FCH_SMB_ALL_HOST_STATUS 0x1f // HostBusy+SMBInterrupt+DeviceErr+BusCollision+Failed +#define FCH_SMB_CMD_BYTE_DATA_START 0x48 // Byte Data Read or Write +#define FCH_SMB_CMD_START BIT6 +#define FCH_SMB_READ_ENABLE BIT0 +#define FCH_SMB_AUTO_POLL_EN BIT0 +#define FCH_SMB_POLL2BYTE BIT7 + +#define SBTSI_ADDR 0x98 +#define SBTSI_REG01 0x01 +#define SBTSI_REG09 0x09 +#define SBTSI_REG10 0x10 +#define SBTSI_READORDER BIT5 + +#define FCH_EC_ENTER_CONFIG 0X5A +#define FCH_EC_EXIT_CONFIG 0XA5 +#define FCH_EC_REG07 0X07 +#define FCH_EC_REG30 0X30 +#define FCH_EC_REG60 0X60 +#define FCH_EC_REG61 0X61 + +#define FCH_IMC_ROMSIG 0x55aa55aaul + +#define SPI_HEAD_LENGTH 0x0E +#define SPI_BAR0_VLD 0x01 +#define SPI_BASE0 (0x00 << 7) +#define SPI_BAR1_VLD (0x01 << 8) +#define SPI_BASE1 (SPI_HEAD_LENGTH << 10) +#define SPI_BAR2_VLD (0x01 << 16) +#define SPI_BASE2(x) ((SPI_HEAD_LENGTH + ACPIMMIO16(x)) << 18) + +#define FW_TO_SIGADDR_OFFSET 0x0C +#define BCD_ADDR_OFFSET 0x02 +#define BCD_SIZE_OFFSET 0x04 +#define FW_ADDR_OFFSET 0x06 +#define FW_SIZE_OFFSET 0x08 +#define ACD_ADDR_OFFSET 0x0A +#define ACD_SIZE_OFFSET 0x0C +#define XHC_BOOT_RAM_SIZE 0x8000 + +#define PKT_DATA_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x00 +#define PKT_LEN_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x14 +#define PKT_CTRL_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x15 +#define EFUS_DAC_ADJUSTMENT_CONTROL 0x850A8ul +#define BGADJ 0x1F +#define DACADJ 0x1B +#define EFUS_DAC_ADJUSTMENT_CONTROL_DATA (BGADJ + (DACADJ << 8) + BIT16 ) + +#define KABINI_OSC_OUT_CLOCK_SEL_48MHz 0x02 +#define KABINI_OSC_OUT_CLOCK_SEL_25MHz 0x01 + +#define KERN_OSC_OUT_CLOCK_SEL_48MHz 0x02 +#define KERN_OSC_OUT_CLOCK_SEL_25MHz 0x01 + +#define RTC_WORKAROUND_SECOND 0x00 +#define RTC_VALID_SECOND_VALUE 0x59 +#define RTC_SECOND_RESET_VALUE 0x30 +#define RTC_SECOND_LOWER_NIBBLE 0x0F +#define RTC_VALID_SECOND_VALUE_LN 0x09 + +#ifndef FCH_DEADLOOP + #define FCH_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); } +#endif + +#define OHCI_ARB_REGQ_VLD_EN BIT2 + +#define HCEx40_Control 0xFED80040ul +#define HCEx44_Input 0xFED80044ul +#define HCEx48_Output 0xFED80048ul +#define HCEx4C_Status 0xFED8004Cul +#define HCEx50_IntrEn 0xFED80050ul +#define EmulationSmiEn BIT4 + +#define FCH_PMx08_PciControl 0xFED80308ul // PCI Control +#define FCH_PMx08_PciControl_ShutDownOption BIT20 + +#define FCH_PMxD2_PmioDebug 0xFED803D2ul // Pmio Debug +#define FCH_PMxD6_Imc_Gating 0xFED803D6ul // IMC Gating +#define FCH_PMxEC_LpcGating 0xFED803ECul // LPC Gating + diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/FchPlatform.h new file mode 100644 index 0000000000..ca2a8d89a5 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/FchPlatform.h @@ -0,0 +1,117 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH platform definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ +#ifndef _FCH_PLATFORM_H_ +#define _FCH_PLATFORM_H_ + +#define MAX_SATA_PORTS 8 + +#include "AGESA.h" + +#ifndef FCHOEM_ACPI_RESTORE_SWSMI + #define FCHOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3 + #define FCHOEM_AFTER_PCI_RESTORE_SWSMI 0xD4 + #define FCHOEM_ENABLE_ACPI_SWSMI 0xA0 + #define FCHOEM_DISABLE_ACPI_SWSMI 0xA1 + #define FCHOEM_START_TIMER_SMI 0xBC + #define FCHOEM_STOP_TIMER_SMI 0xBD +#endif + +#ifndef FCHOEM_SPI_UNLOCK_SWSMI + #define FCHOEM_SPI_UNLOCK_SWSMI 0xAA +#endif +#ifndef FCHOEM_SPI_LOCK_SWSMI + #define FCHOEM_SPI_LOCK_SWSMI 0xAB +#endif + +#ifndef FCHOEM_ACPI_TABLE_RANGE_LOW + #define FCHOEM_ACPI_TABLE_RANGE_LOW 0xE0000ul +#endif + +#ifndef FCHOEM_ACPI_TABLE_RANGE_HIGH + #define FCHOEM_ACPI_TABLE_RANGE_HIGH 0xFFFF0ul +#endif + +#ifndef FCHOEM_ACPI_BYTE_CHECHSUM + #define FCHOEM_ACPI_BYTE_CHECHSUM 0x100 +#endif + +#ifndef FCHOEM_IO_DELAY_PORT + #define FCHOEM_IO_DELAY_PORT 0x80 +#endif + +#ifndef FCHOEM_OUTPUT_DEBUG_PORT + #define FCHOEM_OUTPUT_DEBUG_PORT 0x80 +#endif + +#define FCH_PCIRST_BASE_IO 0xCF9 +#define FCH_PCI_RESET_COMMAND06 0x06 +#define FCH_PCI_RESET_COMMAND0E 0x0E +#define FCH_KBDRST_BASE_IO 0x64 +#define FCH_KBC_RESET_COMMAND 0xFE +#define FCH_ROMSIG_BASE_IO 0x20000l +#define FCH_ROMSIG_SIGNATURE 0x55AA55AAul +#define FCH_MAX_TIMER 0xFFFFFFFFul +#define FCH_GEC_INTERNAL_REG 0x6804 +#define FCH_HPET_REG_MASK 0xFFFFF800ul +#define FCH_FAKE_USB_BAR_ADDRESS 0x58830000ul + + +#ifndef FCHOEM_ELAPSED_TIME_UNIT + #define FCHOEM_ELAPSED_TIME_UNIT 28 +#endif + +#ifndef FCHOEM_ELAPSED_TIME_DIVIDER + #define FCHOEM_ELAPSED_TIME_DIVIDER 100 +#endif + +#include "Fch.h" +#include "amdlib.h" +#include "FchCommonCfg.h" +#include "AcpiLib.h" +#include "FchDef.h" +#include "FchBiosRamUsage.h" +#include "AmdFch.h" + +extern BUILD_OPT_CFG UserOptions; + +#endif // _FCH_PLATFORM_H_ diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Kern/KernFch.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Kern/KernFch.h new file mode 100644 index 0000000000..a20ec19f55 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Kern/KernFch.h @@ -0,0 +1,200 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * FCH registers definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: FCH + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#define KERN_FCH_SATA_DID 0x7900 +#define KERN_FCH_SATA_AHCI_DID 0x7901 +#define KERN_FCH_SATA_AMDAHCI_DID 0x7904 + +#define KERN_FCH_USB_XHCI_DID 0x7914 // Dev 0x10 Func 0 +#define KERN_FCH_USB_EHCI_DID 0x7908 // Dev 0x12 Func 0 +#define KERN_FCH_SMBUS_DID 0x790B // Dev 0x14 Func 0 +#define KERN_FCH_LPC_DID 0x790E // Dev 0x14 Func 3 +#define KERN_FCH_SD_DID 0x7906 // Dev 0x14 Func 7 + +#define KERN_EHCI1_BUS_DEV_FUN ((0x12 << 3) + 0) +#define KERN_EHCI1_BUS 0 +#define KERN_EHCI1_DEV 18 +#define KERN_EHCI1_FUNC 0 +#define KERN_EHCI2_BUS_DEV_FUN ((0x13 << 3) + 0) +#define KERN_EHCI2_BUS 0 +#define KERN_EHCI2_DEV 19 +#define KERN_EHCI2_FUNC 0 +#define KERN_EHCI3_BUS_DEV_FUN ((0x16 << 3) + 0) +#define KERN_EHCI3_BUS 0 +#define KERN_EHCI3_DEV 22 +#define KERN_EHCI3_FUNC 0 + +// Specific FCH register for Kern +#define FCH_EHCI_REG64 0x64 +#define FCH_EHCI_REGA4 0xA4 + +// HD Audio/Azalia +#define KERN_EVENT_HD_AUDIO_MSI_ENABLE 0x02010100ul // HD Audio/Azalia MSI enable. +#define KERN_EVENT_HD_AUDIO_DISABLE 0x02010101ul // HD Audio/Azalia Disable. +#define KERN_EVENT_HD_AUDIO_CONFIG_CODEC 0x02010102ul // HD Audio/Azalia Configure CODEC. +#define KERN_EVENT_HD_AUDIO_CONFIG_CODEC_BUSY 0x02010103ul // HD Audio/Azalia Configure CODEC Reset. +#define KERN_ERROR_HD_AUDIO_RESET 0x02030100ul // HD Audio/Azalia Reset Failure. +#define KERN_ERROR_HD_AUDIO_CODEC 0x02030101ul // HD Audio/Azalia Codec Not Found. +// HW ACPI +#define KERN_EVENT_HWACPI_PROG_ACPI_PMTBL 0x02010200ul // FCH program ACPI PM Controller Base Address. +#define KERN_EVENT_HWACPI_PROG_ACPI_MMIO_IN_RESET 0x02010201ul // FCH program ACPIMMIO registers in RESET. +#define KERN_EVENT_HWACPI_PROG_SCI_MAP 0x02010202ul // FCH program SCI map by OEM table (ACPIMMIO 0xFED803xx). +#define KERN_EVENT_HWACPI_PROG_GPIO_MAP 0x02010203ul // FCH program GPIO setting by OEM table (ACPIMMIO 0xFED801xx). +#define KERN_EVENT_HWACPI_PROG_SATA_PHY 0x02010204ul // FCH program SATA PHY by OEM table. +#define KERN_EVENT_RTC_DAYLIGHT_SAVING_TIME 0x02010205ul // FCH RTC DayLight Saving Workaround. +#define KERN_EVENT_RTC_CLEAR_BANK_SELECTION 0x02010206ul // FCH RTC clear BankSelection 0x0A Bit4 prevent error. +#define KERN_EVENT_RTC_WA 0x02010207ul // FCH RTC workaround is set. +#define KERN_EVENT_KBD_CONNECTED_THRU_USB 0x02010208ul // FCH IRQ1/IRQ12 connected to USB controller. +#define KERN_EVENT_LEGACY_FREE_SET 0x02010209ul // FCH None Legacy IO setting. +#define KERN_EVENT_ENABLED_ASF_REMOTE_CTRL 0x0201020Aul // FCH Enable ASF remote control function. +#define KERN_EVENT_PCIEXP_WAKESTATUS_WA 0x0201020Bul // FCH PciExp Wake Status Workaround. +#define KERN_EVENT_HWACPI_PROG_OEM_MMIOTBL_IN_RESET 0x0201020Cul // FCH program OEM/Platform BIOS ACPIMMIO registers. +#define KERN_EVENT_HWACPI_PROG_MMIOTBL 0x02010200ul // FCH program ACPIMMIO registers. (1st.) +#define KERN_EVENT_HWACPI_NO_SIOKBC_ENABLE 0x02010201ul // FCH No SIO/KBC function is enabled. +#define KERN_EVENT_HWACPI_NO_SIOKBC_DISABLE 0x02010202ul // FCH No SIO/KBC function is disabled. +#define KERN_EVENT_HWACPI_PROG_SPECIFIC_MMIOTBL 0x02010203ul // FCH program Specific ACPIMMIO registers. (2nd.) +#define KERN_EVENT_HWACPI_PROG_OEM_MMIOTBL 0x02010204ul // FCH program OEM/Platform BIOS ACPIMMIO registers (3rd.) +#define KERN_EVENT_HWACPI_SPREAD_SPECTRUM 0x02010205ul // FCH Enable Spread Spectrum function. +#define KERN_EVENT_HWACPI_INT_CLK_SET 0x02010206ul // FCH Set Intermal Clock Display as 48Mhz. +#define KERN_EVENT_HPET_TIMER_TICK_INTERVAL_WA_SET 0x02010207ul // FCH HPET timer tick interval workaround is set. +#define KERN_EVENT_C1E_ENABLE 0x02010208ul // FCH C1e Enabled. +#define KERN_EVENT_NATIVEPCIE_MODE_SET 0x02010208ul // FCH Native PCIe mode is set. +#define KERN_ERROR_HPET_TBL_NOT_FOUND 0x02030200ul // FCH HPET Table does not found. +// HWM +#define KERN_EVENT_IMC_DISABLE 0x02010300ul // FCH HWM/IMC is disabled. +#define KERN_EVENT_IMC_ENABLE 0x02010301ul // FCH HWM/IMC is enabled. +// IMC +#define KERN_EVENT_IMC_SW_TOGGLE_EVENT 0x02010302ul // FCH IMC Software Toggle Strapping. (IMC statement change) +#define KERN_EVENT_EC_ENABLE 0x02020303ul // FCH EC enabled. +#define KERN_EVENT_EC_KBD_ENABLE 0x02010304ul // FCH IMC EC KBD enabled. +#define KERN_EVENT_EC_CHANNEL0_ENABLE 0x02010305ul // FCH IMC EC channel0 function enabled. +#define KERN_EVENT_IMC_INTO_SLEEP_MODE 0x02010306ul // FCH IMC goes into sleep mode. +#define KERN_EVENT_IMC_CRASH_RESET 0x02010307ul // FCH IMC Crash Reset to prevent repeating the reset forever. +#define KERN_EVENT_IMC_SW_DISABLE_IMC 0x02010308ul // FCH Software disable IMC thru mailbox command. +#define KERN_EVENT_IMC_DISABLE_SUREBOOT_TIMMER 0x02010309ul // FCH Disable SureBoot Timmer. +#define KERN_EVENT_IMC_WAKEUP 0x0201030Aul // FCH IMC wakeup command. +#define KERN_EVENT_IMC_IDLE 0x0201030Bul // FCH IMC idle command. +#define KERN_EVENT_EC_DISABLE 0x0201030Cul // FCH EC disable by jumper setting or board config. +#define KERN_ERROR_IMC_FW_VALIDATE_FAILED 0x02030300ul // FCH IMC firmware validation failure. +// PCIE/AB +#define KERN_EVENT_AB_SLOW_SPEED_ABLINK_CLOCK 0x02010400ul // FCH Set Low Speed AB link clock. +#define KERN_EVENT_AB_RESET_CPU_ON_SYNC_FLOOD 0x02010401ul // FCH set AB reset CPU on sync flood enabled. +#define KERN_EVENT_AB_CLOCK_GATING_ENABLE 0x02010402ul // FCH set AB Clock Gating function enabled. +#define KERN_EVENT_AB_CLOCK_GATING_DISABLE 0x02010403ul // FCH set AB clock Gating function disabled. +#define KERN_EVENT_AB_DMA_MEMORY_W3264B_ENABLE 0x02010404ul // FCH set AB DMA MEMORY Write 32/64B enabled. +#define KERN_EVENT_AB_DMA_MEMORY_W3264B_DISABLED 0x02010405ul // FCH set AB DMA MEMORY Write 32/64B disabled. +#define KERN_EVENT_AB_MEMORY_POWERSAVING_ENABLED 0x02010406ul // FCH Set AB Memory Power Saving enabled. +#define KERN_EVENT_AB_MEMORY_POWERSAVING_DISABLED 0x02010407ul // FCH Set AB Memory Power Saving disabled. +#define KERN_EVENT_AB_ALINK_CLK_GATEOFF_ENABLED 0x02010408ul // FHC set ALink clock Gate-off enabled. +#define KERN_EVENT_AB_ALINK_CLK_GATEOFF_DISABLED 0x02010409ul // FHC set ALink clock Gate-off disabled. +#define KERN_EVENT_AB_BLINK_CLK_GATEOFF_ENABLED 0x0201040Aul // FHC set BLink clock Gate-off enabled. +#define KERN_EVENT_AB_BLINK_CLK_GATEOFF_DISABLED 0x0201040Bul // FHC set BLink clock Gate-off disabled. +// SATA +#define KERN_EVENT_SATA_ENABLE 0x02010500ul // FCH set SATA controller enabled. +#define KERN_EVENT_SATA_MAX_GEN2_MODE_ENABLE 0x02010501ul // FCH set SATA support only Max. GEN2 mode. +#define KERN_EVENT_SATA_SET_CLK_SOURCE_ORG_EXT 0x02010502ul // FCH set SATA clock source as external 48Mhz. +#define KERN_EVENT_SATA_SET_CLK_SOURCE_ORG_INT 0x02010502ul // FCH set SATA clock source as internal 48Mhz. +#define KERN_EVENT_SATA_SET_CLK_SOURCE_100_INT 0x02010503ul // FCH set SATA clock source as internal 100Mhz. +#define KERN_EVENT_SATA_STABLE_MEM_SHUTDOWN_ENABLE 0x02010504ul // FCH set SATA stable memory sutdown enable * Misc. +#define KERN_EVENT_SATA_PROG_SATA_PORT_PHY 0x02010505ul // FCH programming SATA port's PHY. +#define KERN_EVENT_SATA_READ_SQUELCH_FROM_EFUSE 0x02010506ul // FCH programming SATA squelch value from eFuse. +#define KERN_EVENT_SATA_DISABLE 0x02010507ul // FCH set SATA controller disabled. +#define KERN_EVENT_SATA_AHCI_MODE 0x02010508ul // FCH set SATA as AHCI mode. +#define KERN_EVENT_SATA_IDE_2_AHCI_MODE 0x02010509ul // FCH set SATA as IDE_2_AHCI mode. +#define KERN_EVENT_SATA_IDE_MODE 0x0201050Aul // FCH set SATA as IDE mode. +#define KERN_EVENT_SATA_RAID_MODE 0x0201050Bul // FCH set SATA as RAID mode. +#define KERN_EVENT_SATA_MSI_CAP_ENABLE 0x0201050Cul // FCH set SATA MSI Capability Enabled. +#define KERN_EVENT_SATA_SUPPORT_8_DEVICE 0x0201050Dul // FCH set SATA support 8 device mode. +#define KERN_EVENT_SATA_DISABLED_GENERIC_MODE 0x0201050Eul // FCH set SATA disable generic mode. +#define KERN_EVENT_SATA_PHY_PLL_SHUTDOWN 0x0201050Ful // FCH set SATA PHY PLL shutdown. +#define KERN_EVENT_SATA_OOB_DETECTION_ENH 0x02010510ul // FCH set SATA OOB Detection Enhance Mode. +#define KERN_EVENT_SATA_MEM_POWER_SAVING 0x02010511ul // FCH set SATA memory power saving. +#define KERN_EVENT_SATA_DEV_SLP_PORT0 0x02010512ul // FCH set SATA Deep Sleep Mode on Port0. +#define KERN_EVENT_SATA_DEV_SLP_PORT1 0x02010513ul // FCH set SATA Deep Sleep Mode on Port1. +#define KERN_EVENT_SATA_AHCI_DIS_PREFETCH 0x02010514ul // FCH set SATA AHCI disable Prefetch. +#define KERN_EVENT_SATA_PORT_MULT_CAP 0x02010515ul // FCH set SATA Port Mult Capability Enabled. +#define KERN_EVENT_SATA_FIS_BASE_SWITCHING 0x02010516ul // FCH set SATA support FIS-based switching. +#define KERN_EVENT_SATA_AGGR_LINK_PM_CAP 0x02010517ul // FCH set SATA aggressive link power management. +#define KERN_EVENT_SATA_PSC_CAP 0x02010518ul // FCH set SATA support partial state. +#define KERN_EVENT_SATA_SSC_CAP 0x02010519ul // FCH set SATA support Slumber mode. +#define KERN_EVENT_SATA_CCC_CAP 0x0201051Aul // FCH set SATA support command completion coalescing. +#define KERN_EVENT_SATA_AHCI_ENCLOSURE_MANAGEMENT 0x0201051Bul // FCH set SATA support Enclosure Management. +#define KERN_EVENT_SATA_ESP_PORT_ENABLE 0x0201051Cul // FCH set SATA ESP ports (one of ESP ports are set). +#define KERN_EVENT_SATA_BIOS_OS_HANDOFF 0x0201051Dul // FCH set SATA HBA supports the BIOS/OS handoff mechanism. +#define KERN_EVENT_SATA_DRIVE_DETECTION 0x0201051Eul // FCH SATA is excuting SATA drive detection. +#define KERN_EVENT_SATA_CLK_AUTO_OFF 0x0201051Ful // FCH set SATA Auto Clock off function. +#define KERN_EVENT_SATA_PORT_GEN_MODE 0x02010520ul // FCH set SATA port GEN mode. +#define KERN_EVENT_SATA_HOT_REMOVAL_ENH 0x02010521ul // FCH set SATA hot removal enhance mode. +// SD +#define KERN_EVENT_SD_ENABLE 0x02010600ul // FCH set SD controller to enable. +#define KERN_EVENT_SD_AS_DMA_MODE 0x02010601ul // FCH set SD as DMA mode. +#define KERN_EVENT_SD_AS_PIO_MODE 0x02010602ul // FCH set SD as PIO mode. +#define KERN_EVENT_SD_AS_2_0_MODE 0x02010603ul // FCH set SD as 2.0 mode. +#define KERN_EVENT_SD_AS_3_0_MODE 0x02010604ul // FCH set SD as 3.0 mode. +#define KERN_EVENT_SD_CLOCK_MULTIPLIER 0x02010605ul // FCH set SD clock multiplier. +#define KERN_EVENT_SD_DISABLE 0x02010606ul // FCH set SD controller to disable. +// LPC/SPI +#define KERN_EVENT_LPC_CLK0_DISABLE 0x02010700ul // FCH set LPC0 clock disabled. +#define KERN_EVENT_LPC_CLK1_DISABLE 0x02010701ul // FCH set LPC1 clock disabled. +#define KERN_EVENT_LPC_LEGACY_FREE_MODE 0x02010702ul // FCH set LPC as legacy free mode. +#define KERN_EVENT_SPI_QUAL_MODE 0x02010703ul // FCH SPI Qual Mode is enabled (by user selection). +#define KERN_EVENT_SPI_SPEED 0x02010704ul // FCH SPI speed is set by user selection. +#define KERN_EVENT_SPI_FAST_SPEED 0x02010705ul // FCH SPI fast speed is set. +#define KERN_EVENT_SPI_QUALIFY_QUAL_MODE 0x02010706ul // FCH SPI Qual Mode is validated. +// USB +#define KERN_ERROR_USB_ROMSIG_NOT_FOUND 0x02030800ul // FCH ROMSIG not found. +#define KERN_ERROR_USB_XHCI_FW_FOUND 0x02030801ul // FCH XHCI firmware does not exist. +#define KERN_EVENT_USB_EHCI1_ENABLE 0x02010800ul // FCH set EHCI1 enable. +#define KERN_EVENT_USB_EHCI2_ENABLE 0x02010801ul // FCH set EHCI2 enable. +#define KERN_EVENT_USB_EHCI3_ENABLE 0x02010802ul // FCH set EHCI3 enable. +#define KERN_EVENT_USB_XHCI_DISABLE 0x02010803ul // FCH set XHCI disable. +#define KERN_EVENT_USB_PHY_POWER_DOWN 0x02010804ul // FCH set USB PHY powerdown enable. +#define KERN_EVENT_USB_PHY_CALIBRATED 0x02010805ul // FCH set USB PHY calibrated. +#define KERN_EVENT_USB_PORT_PHY_SETTING 0x02010806ul // FCH set USB Port PHY setting. +#define KERN_EVENT_USB_PORT_PHY_CLK_GATING 0x02010807ul // FCH set USB Port PHY Clock Gating. +#define KERN_EVENT_USB_XHCI_USED_PREDEFINE_ADDRESS 0x02010808ul // FCH XHCI ROM location is used user-define address. +#define KERN_EVENT_USB_XHCI_BOOTRAM_PRELOAD 0x02010809ul // FCH XHCI preload its BOOTRAM. +#define KERN_EVENT_USB_XHCI_INSTRUCTRAM_PRELOAD 0x0201080Aul // FCH XHCI preload its InstructionRAM. +#define KERN_EVENT_USB_XHCI_ROM_PREINIT_COMPLETED 0x0201080Bul // FCH XHCI preinit completed. +#define KERN_EVENT_USB_XHCI0_ENABLE 0x0201080Cul // FCH set XHCI0 enable. +#define KERN_EVENT_USB_XHCI1_ENABLE 0x0201080Dul // FCH set XHCI1 enable. diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.c b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.c new file mode 100644 index 0000000000..20a359ad0e --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.c @@ -0,0 +1,464 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PSP Base Library + * + * Contains interface to the PSP library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: PSP + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Filecode.h" +#include "PspBaseLib.h" + +#define FILECODE PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE +#define PSP_BAR1_TMP_BASE 0xFEA00000ul + +#define GET_PCI_BUS(Reg) (((UINT32) Reg >> 16) & 0xFF) +#define GET_PCI_DEV(Reg) (((UINT32) Reg >> 11) & 0x1F) +#define GET_PCI_FUNC(Reg) (((UINT32) Reg >> 8) & 0x7) +#define GET_PCI_OFFSET(Reg) ((UINT32)Reg & 0xFF) + +#define PCI_CONFIG_SMU_INDIRECT_INDEX 0xB8 ///< Gnb Offset index for SMU mbox +#define PCI_CONFIG_SMU_INDIRECT_DATA 0xBC ///< Gnb Offset data for SMU mbox + +#define SMU_CC_PSP_FUSES_STATUS 0xC0018000ul ///< offset in GNB to find PSP fusing +#define SMU_CC_PSP_FUSES_SECURE BIT0 ///< BIT0 +#define SMU_CC_PSP_FUSES_FRA_ENABLE BIT1 ///< BIT1 +#define SMU_CC_PSP_FUSES_PROTO BIT2 ///< BIT2 +#define PLATFORM_SECURE_BOOT_EN BIT4 ///< BIT4 + + +#define PSP_BLANK_PART 0 ///< Blank part +#define PSP_PROTO_PART SMU_CC_PSP_FUSES_PROTO ///< Proto Part +#define PSP_NON_SECURE_PART (SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_PCPU_DIS) ///< Non Secure Part +#define PSP_SECURE_PART (SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE) ///< Secure Part +#define PSP_FRA_MODE (SMU_CC_PSP_FUSES_FRA_ENABLE + SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE) ///< FRA Part + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + + +UINT32 +PspLibPciReadConfig ( + IN UINT32 Register + ) +{ + UINT32 Value; + PCI_ADDR PciAddr; + + Value = 0; + PciAddr.AddressValue = MAKE_SBDFO (0, GET_PCI_BUS (Register), GET_PCI_DEV (Register), GET_PCI_FUNC (Register), GET_PCI_OFFSET (Register)); + + LibAmdPciRead (AccessWidth32, PciAddr, &Value, NULL); + + return Value; +} + +VOID +PspLibPciWriteConfig ( + IN UINT32 Register, + IN UINT32 Value + ) +{ + PCI_ADDR PciAddr; + PciAddr.AddressValue = MAKE_SBDFO (0, GET_PCI_BUS (Register), GET_PCI_DEV (Register), GET_PCI_FUNC (Register), GET_PCI_OFFSET (Register)); + + LibAmdPciWrite (AccessWidth32, PciAddr, &Value, NULL); + +} + +UINT32 +PspLibPciReadPspConfig ( + IN UINT16 Offset + ) +{ + return (PspLibPciReadConfig ((UINT32) (PSP_PCI_BDA + Offset))); +} + +VOID +PspLibPciWritePspConfig ( + IN UINT16 Offset, + IN UINT32 Value + ) +{ + PspLibPciWriteConfig ((UINT32) (PSP_PCI_BDA + Offset), Value); +} + +BOOLEAN +GetPspDirBase ( + IN OUT UINT32 *Address + ) +{ + UINTN i; + FIRMWARE_ENTRY_TABLE *FirmwareTableBase; + CONST UINT32 RomSigAddrTable[] = + { + 0xFFFA0000, // --> 512KB base + 0xFFF20000, // --> 1MB base + 0xFFE20000, // --> 2MB base + 0xFFC20000, // --> 4MB base + 0xFF820000, // --> 8MB base + 0xFF020000 // --> 16MB base + }; + + for (i = 0; i < sizeof (RomSigAddrTable) / sizeof (UINT32); i++) { + FirmwareTableBase = (FIRMWARE_ENTRY_TABLE *) (UINTN) RomSigAddrTable[i]; + // Search flash for unique signature 0x55AA55AA + if (FirmwareTableBase->Signature == FIRMWARE_TABLE_SIGNATURE) { + *Address = FirmwareTableBase->PspDirBase; + return TRUE; + } + } + + return (FALSE); +} + +BOOLEAN +PSPEntryInfo ( + IN PSP_DIRECTORY_ENTRY_TYPE EntryType, + IN OUT UINT64 *EntryAddress, + IN UINT32 *EntrySize + ) +{ + PSP_DIRECTORY *PspDir; + UINTN i; + + if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) { + return FALSE; + } + + for (i = 0; i < PspDir->Header.TotalEntries; i++) { + if (PspDir->PspEntry[i].Type == EntryType) { + *EntryAddress = PspDir->PspEntry[i].Location; + *EntrySize = PspDir->PspEntry[i].Size; + return (TRUE); + } + } + + return (FALSE); +} + +/** + Check if PSP device is present + + @retval BOOLEAN 0: PSP Disabled, 1: PSP Enabled + +**/ +BOOLEAN +CheckPspDevicePresent ( + VOID + ) +{ + UINT32 SecureFuseReg; + PspLibPciWriteConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_INDEX, (UINT32)SMU_CC_PSP_FUSES_STATUS); + SecureFuseReg = PspLibPciReadConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_DATA); + + if (SecureFuseReg &= SMU_CC_PSP_FUSES_PROTO) { + return (TRUE); + } + return (FALSE); +} + +/** + Check PSP Platform Seucre Enable State + HVB & Secure S3 (Resume vector set to Dram, & core content will restore by uCode) + will be applied if Psp Plaform Secure is enabled + + @retval BOOLEAN 0: PSP Platform Secure Disabled, 1: PSP Platform Secure Enabled + +**/ +BOOLEAN +CheckPspPlatformSecureEnable ( + VOID + ) +{ + UINT32 SecureFuseReg; + PspLibPciWriteConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_INDEX, (UINT32)SMU_CC_PSP_FUSES_STATUS); + SecureFuseReg = PspLibPciReadConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_DATA); + + if (SecureFuseReg &= PLATFORM_SECURE_BOOT_EN) { + return (TRUE); + } + return (FALSE); +} + +/** + Check PSP Recovery Flag + Target will set Recovery flag if some PSP entry point by PSP directory has been corrupted. + + @retval BOOLEAN 0: Recovery Flag is cleared, 1: Recovery Flag has been set + +**/ +BOOLEAN +CheckPspRecoveryFlag ( + VOID + ) +{ + MBOX_STATUS *MboxStatus; + + //Init PSP MMIO + PspBarInitEarly (); + + GetPspMboxStatus (&MboxStatus); + + return (BOOLEAN) (MboxStatus->Recovery); +} + +/** + Return the PspMbox MMIO location + + + @retval BOOLEAN FALSE: ERROR, TRUE: SUCCEED + +**/ +BOOLEAN +GetPspMboxStatus ( + IN OUT MBOX_STATUS **MboxStatus + ) +{ + UINT32 PspMmio; + + if (GetPspBar1Addr (&PspMmio) == FALSE) { + return (FALSE); + } + + *MboxStatus = (MBOX_STATUS *)( (UINTN)PspMmio + PSP_MAILBOX_BASE + PSP_MAILBOX_STATUS_OFFSET); // PSPMbox base is at offset CP2MSG_28 ie. offset 28*4 = 0x70 + + return (TRUE); +} + +BOOLEAN +PspBarInitEarly (void) +{ + UINT32 PspMmioSize; + UINT32 Value32; + + if (PspLibPciReadPspConfig (PSP_PCI_DEVID_REG) == 0xffffffff) { + return (FALSE); + } + + //Check if PSP BAR has been assigned, if not do the PSP BAR initialation + if (PspLibPciReadPspConfig (PSP_PCI_BAR1_REG) == 0) { + /// Get PSP BAR1 Size + PspLibPciWritePspConfig (PSP_PCI_BAR1_REG, 0xFFFFFFFF); + PspMmioSize = PspLibPciReadPspConfig (PSP_PCI_BAR1_REG); + PspMmioSize = ~PspMmioSize + 1; + /// Assign BAR1 Temporary Address + PspLibPciWritePspConfig (PSP_PCI_BAR1_REG, PSP_BAR1_TMP_BASE); + PspLibPciWritePspConfig ( PSP_PCI_CMD_REG, 0x06); + + /// Enable GNB redirection to this space @todo use equate & also find proper fix + PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xBC), ((PSP_BAR1_TMP_BASE + PspMmioSize -1) >> 8) & ~0xFF); + PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xB8), (PSP_BAR1_TMP_BASE >> 8) | 3); + /// Enable MsixBarEn, Bar1En, Bar3En + PspLibPciWritePspConfig ( PSP_PCI_EXTRAPCIHDR_REG, 0x34); + /// Capability chain update + Value32 = PspLibPciReadPspConfig (PSP_PCI_MIRRORCTRL1_REG); + Value32 &= ~D8F0x44_PmNxtPtrW_MASK; + Value32 |= 0xA4; + PspLibPciWritePspConfig (PSP_PCI_MIRRORCTRL1_REG, Value32); + } + + return (TRUE); +} + +/** + Return the PspMMIO MMIO location + + @param[in] PspMmio Pointer to Psp MMIO address + + @retval BOOLEAN 0: Error, 1 Success +**/ +BOOLEAN +GetPspBar1Addr ( + IN OUT UINT32 *PspMmio + ) +{ + if (CheckPspDevicePresent () == FALSE) { + return (FALSE); + } + + *PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR1_REG); + + if ((*PspMmio) == 0xffffffff) { + return (FALSE); + } + + return (TRUE); +} + +/** + Return the PspMMIO MMIO location + + @param[in] PspMmio Pointer to Psp MMIO address + + @retval BOOLEAN 0: Error, 1 Success +**/ +BOOLEAN +GetPspBar3Addr ( + IN OUT UINT32 *PspMmio + ) +{ + if (CheckPspDevicePresent () == FALSE) { + return (FALSE); + } + + *PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG); + + if ((*PspMmio) == 0xffffffff) { + return (FALSE); + } + + return (TRUE); +} + +/*---------------------------------------------------------------------------------------*/ +/** + * Returns the access width mask for the processor + * + * + * @param[in] AccessWidth Access width + * @retval Width in number of bytes + */ + + +UINT8 +PspLibAccessWidth ( + IN ACCESS_WIDTH AccessWidth + ) +{ + UINT8 Width; + + switch (AccessWidth) { + case AccessWidth8: + case AccessS3SaveWidth8: + Width = 1; + break; + case AccessWidth16: + case AccessS3SaveWidth16: + Width = 2; + break; + case AccessWidth32: + case AccessS3SaveWidth32: + Width = 4; + break; + case AccessWidth64: + case AccessS3SaveWidth64: + Width = 8; + break; + default: + Width = 0; + } + return Width; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Read GNB indirect registers + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] Width Width + * @param[out] Value Pointer to value + */ +VOID +PspLibPciIndirectRead ( + IN PCI_ADDR Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + OUT VOID *Value + ) +{ + UINT32 IndexOffset; + + IndexOffset = PspLibAccessWidth (Width); + LibAmdPciWrite (Width, Address, &IndirectAddress, NULL); + Address.AddressValue += IndexOffset; + LibAmdPciRead (Width, Address, Value, NULL); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Write GNB indirect registers + * + * + * + * @param[in] Address PCI address of indirect register + * @param[in] IndirectAddress Offset of indirect register + * @param[in] Width Width + * @param[in] Value Pointer to value + */ +VOID +PspLibPciIndirectWrite ( + IN PCI_ADDR Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN VOID *Value + ) +{ + UINT32 IndexOffset; + + IndexOffset = PspLibAccessWidth (Width); + LibAmdPciWrite (Width, Address, &IndirectAddress, NULL); + Address.AddressValue += IndexOffset; + LibAmdPciWrite (Width, Address, Value, NULL); +} + + diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h new file mode 100644 index 0000000000..c18e191780 --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h @@ -0,0 +1,187 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PSP Base Library + * + * Contains interface to the PSP library + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: PSP + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + * + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _PSP_BASE_LIB_H_ +#define _PSP_BASE_LIB_H_ + +#include "AMD.h" +#include "amdlib.h" +#include "PspDirectory.h" + +#define PSP_PCI_SEG 0x00 ///< PSP Seg address +#define PSP_PCI_BUS 0x00 ///< PSP Bus address +#define PSP_PCI_DEV 0x08 ///< PSP Device address +#define PSP_PCI_FN 0x00 ///< PSP Fn address +#define PSP_PCI_BDA ((PSP_PCI_DEV << 11) + (PSP_PCI_FN << 8)) +#define GET_PSP_PCI_ADDR (Offset) MAKE_SBDFO (PSP_PCI_SEG, PSP_PCI_BUS, PSP_PCI_DEV, PSP_PCI_FN, Offset) + +#define PSP_PCI_DEVID_REG 0x00 ///< DevId +#define PSP_PCI_CMD_REG 0x04 ///< CmdReg +#define PSP_PCI_BAR1_REG 0x18 ///< Pci Bar1 +#define PSP_PCI_BAR3_REG 0x20 ///< Pci Bar3 +#define PSP_PCI_MIRRORCTRL1_REG 0x44 ///< PSP Mirror Reg Ctrl 1 +#define PSP_PCI_EXTRAPCIHDR_REG 0x48 ///< Extra PCI Header Ctr +#define PSP_PCI_HTMSICAP_REG 0x5C ///< HT MSI Capability + +#define D8F0x44_PmNxtPtrW_MASK 0xff + +#define PSP_MAILBOX_BASE 0x70 ///< Mailbox base offset on PCIe BAR +#define PSP_MAILBOX_STATUS_OFFSET 0x4 ///< Staus Offset + +//====================================================================================== +// +// Define Mailbox Status field +// +//====================================================================================== +// +/// MBox Status MMIO space +/// +typedef struct { + UINT32 MboxInitialized:1; ///< Target will set this to 1 to indicate it is initialized (for ex. PSP/TPM ready) + UINT32 Error:1; ///< Target in adddtion to Done bit will also set this bit to indicate success/error on last command + UINT32 Terminated:1; ///< Target will set this bit if it aborted the command due to abort request + UINT32 Halt:1; ///< Target will set this error if there is critical error that require reset etc + UINT32 Recovery:1; ///< Target will set this error if some PSP entry point by PSP directory has been corrupted. + UINT32 Reserved:27; ///< Reserved +} MBOX_STATUS; + +// +// Above defined as bitmap +#define MBOX_STATUS_INITIALIZED 0x00000001ul ///< Mailbox Status: Initialized +#define MBOX_STATUS_ERROR 0x00000002ul ///< Mailbox Status: Error +#define MBOX_STATUS_ABORT 0x00000004ul ///< Mailbox Status: Abort +#define MBOX_STATUS_HALT 0x00000008ul ///< Mailbox Status: Halt +#define MBOX_STATUS_RECOVERY 0x00000010ul ///< Mailbox Status: Recovery required + + + +UINT32 +PspLibPciReadConfig ( + IN UINT32 Register + ); + +VOID +PspLibPciWriteConfig ( + IN UINT32 Register, + IN UINT32 Value + ); + +UINT32 +PspLibPciReadPspConfig ( + IN UINT16 Offset + ); + +VOID +PspLibPciWritePspConfig ( + IN UINT16 Offset, + IN UINT32 Value + ); + +BOOLEAN +GetPspDirBase ( + IN OUT UINT32 *Address +); + +BOOLEAN +PSPEntryInfo ( + IN PSP_DIRECTORY_ENTRY_TYPE EntryType, + IN OUT UINT64 *EntryAddress, + IN UINT32 *EntrySize + ); + +BOOLEAN +CheckPspDevicePresent ( + VOID + ); + +BOOLEAN +CheckPspPlatformSecureEnable ( + VOID + ); + +BOOLEAN +CheckPspRecoveryFlag ( + VOID + ); + +BOOLEAN +GetPspBar1Addr ( + IN OUT UINT32 *PspMmio + ); + +BOOLEAN +GetPspBar3Addr ( + IN OUT UINT32 *PspMmio + ); + + +BOOLEAN +GetPspMboxStatus ( + IN OUT MBOX_STATUS **MboxStatus + ); + + +BOOLEAN +PspBarInitEarly (void); + +VOID +PspLibPciIndirectRead ( + IN PCI_ADDR Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + OUT VOID *Value + ); + +VOID +PspLibPciIndirectWrite ( + IN PCI_ADDR Address, + IN UINT32 IndirectAddress, + IN ACCESS_WIDTH Width, + IN VOID *Value + ); + +UINT8 +PspLibAccessWidth ( + IN ACCESS_WIDTH AccessWidth + ); +#endif // _AMD_LIB_H_ diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspDirectory.h b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspDirectory.h new file mode 100644 index 0000000000..193cc6506c --- /dev/null +++ b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspDirectory.h @@ -0,0 +1,94 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PSP directory related functions Prototype definition + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: PSP + * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $ + */ + /***************************************************************************** + * + * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _PSP_DIRECTORY_H_ +#define _PSP_DIRECTORY_H_ + + +#define FIRMWARE_TABLE_SIGNATURE 0x55AA55AAul +/// Define the structure OEM signature table +typedef struct _FIRMWARE_ENTRY_TABLE { + UINT32 Signature; ///< Signature should be 0x55AA55AAul + UINT32 ImcRomBase; ///< Base Address for Imc Firmware + UINT32 GecRomBase; ///< Base Address for Gmc Firmware + UINT32 XHCRomBase; ///< Base Address for XHCI Firmware + UINT32 PspDirBase; ///< Base Address for PSP directory +} FIRMWARE_ENTRY_TABLE; + +/// Define structure for PSP directory +typedef struct { + UINT32 PspCookie; ///< "$PSP" + UINT32 Checksum; ///< 32 bit CRC of header items below and the entire table + UINT32 TotalEntries; ///< Number of PSP Entries + UINT32 Reserved; ///< Unused +} PSP_DIRECTORY_HEADER; + + +/// define various enum type for PSP entry type +enum _PSP_DIRECTORY_ENTRY_TYPE { + AMD_PUBLIC_KEY = 0, ///< PSP entry pointer to AMD public key + PSP_FW_BOOT_LOADER = 1, ///< PSP entry points to PSP boot loader in SPI space + PSP_FW_TRUSTED_OS = 2, ///< PSP entry points to PSP Firmware region in SPI space + PSP_FW_RECOVERY_BOOT_LOADER = 3, ///< PSP entry point to PSP recovery region. + PSP_NV_DATA = 4, ///< PSP entry points to PSP data region in SPI space + BIOS_PUBLIC_KEY = 5, ///< PSP entry points to BIOS public key stored in SPI space + BIOS_RTM_FIRMWARE = 6, ///< PSP entry points to BIOS RTM code (PEI volume) in SPI space + BIOS_RTM_SIGNATURE = 7, ///< PSP entry points to signed BIOS RTM hash stored in SPI space + SMU_OFFCHIP_FW = 8 ///< PSP entry points to SMU image +}; +typedef UINT32 PSP_DIRECTORY_ENTRY_TYPE; + +/// Structure for PSP Entry +typedef struct { + PSP_DIRECTORY_ENTRY_TYPE Type; ///< Type of PSP entry; 32 bit long + UINT32 Size; ///< Size of PSP Entry in bytes + UINT64 Location; ///< Location of PSP Entry (byte offset from start of SPI-ROM) +} PSP_DIRECTORY_ENTRY; + +/// Structure for PSP directory +typedef struct { + PSP_DIRECTORY_HEADER Header; ///< PSP directory header + PSP_DIRECTORY_ENTRY PspEntry[1]; ///< Array of PSP entries each pointing to a binary in SPI flash + ///< The actual size of this array comes from the + ///< header (PSP_DIRECTORY.Header.TotalEntries) +} PSP_DIRECTORY; + +#endif //_PSP_DIRECTORY_H_ |