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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-07 22:13:10 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-27 10:39:20 +0000
commit56397364c9178cae527520a5fffb9eab2f6cc35b (patch)
tree6eef7e601f8e7c07c0e8f6f59caa776ade7af06f /src/vendorcode/amd/pi/00630F01/binaryPI
parent46f04cbb49fbab5854d395edefea5b5f81df572e (diff)
binaryPI: Drop CAR teardown without POSTCAR_STAGE
The remaining (active) binaryPI boards moved away from BINARYPI_LEGACY_WRAPPER and have POSTCAR_STAGE now. As the cache_as_ram.S is also used with AGESA, this slightly reduces the codesize there for romstage and postcar as well. This commit is actually a revert for the vendorcode parts, AMD originally shipped the codes using 'invd' for the CAR teardown, but these were changed for coreboot due the convoluted teardown that used to happen with non-empty stack. Change-Id: I693c104c3aab3be537c00695cbd764a48bd603b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/18526 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/pi/00630F01/binaryPI')
-rw-r--r--src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc29
1 files changed, 2 insertions, 27 deletions
diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
index 75ba9e7df5..4d903e686f 100644
--- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
@@ -696,13 +696,6 @@ fam15_enable_stack_hook_exit:
* Return any family specific controls to their 'standard'
* settings for using cache with main memory.
*
-* Note: Customized for coreboot:
-* A wbinvd is used to send cache to memory. The existing stack is preserved
-* at its original location and additional information is preserved (e.g.
-* coreboot CAR globals, heap structures, etc.). This implementation should
-* NOT be used with S3 resume IF the stack/cache area is not reserved and
-* over system memory.
-*
* Inputs:
* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
* Outputs:
@@ -911,16 +904,7 @@ fam15_disable_stack_remote_read_exit:
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
- #--------------------------------------------------------------------------
- # Send cache to memory. Preserve stack and coreboot CAR globals.
- # This shouldn't be used with S3 resume IF the stack/cache area is
- # not reserved and over system memory.
- #--------------------------------------------------------------------------
-#if !CONFIG(POSTCAR_STAGE)
- wbinvd
-#else
invd
-#endif
#.if (bh == 01h) || (bh == 03h) ; Is this TN or KV?
cmp $01, %bh
@@ -1563,17 +1547,8 @@ ClearTheStack: # Stack base is in SS, stack pointer is
.endm
/*****************************************************************************
-* AMD_DISABLE_STACK: Implementation is modified for coreboot from
-* the original AMD intent. A WBINVD is used in the HOOK
-* to send dirty cache contents to DRAM backing before
-* disabling cache-as-ram. This is not safe for S3 resume.
-*
-* todo:
-* * rework PI/AGESA source to set DRAM to UC to send
-* writes directly to memory
-* * move DCACHE_BASE or use postcar stage for teardown
-* to eliminate car_migrated problem that will occur
-* after wbinvd is changed back to invd
+* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
+* should only be executed on the BSP
*
* In:
* none