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| author | Matt DeVillier <matt.devillier@amd.corp-partner.google.com> | 2022-08-22 17:07:58 -0500 |
|---|---|---|
| committer | Martin Roth <martin.roth@amd.corp-partner.google.com> | 2022-08-24 15:14:15 +0000 |
| commit | d77525b5bd28011a56194fcb5f8f77bc709dd039 (patch) | |
| tree | 63ad3627c84692456e7c502a0f6026d60b1475a3 /src/vendorcode/amd/fsp | |
| parent | 93447c42a8349565530bffd47bf5c0214f22d690 (diff) | |
vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPE
Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h.
Add/correct values for DDR5, LPDDR5, LPDDR5X.
BUG=b:239000826
TEST=Build and verify with other patches in train
Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/vendorcode/amd/fsp')
| -rw-r--r-- | src/vendorcode/amd/fsp/mendocino/dmi_info.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/vendorcode/amd/fsp/mendocino/dmi_info.h b/src/vendorcode/amd/fsp/mendocino/dmi_info.h index d2c26fad4c..bd9ac5f797 100644 --- a/src/vendorcode/amd/fsp/mendocino/dmi_info.h +++ b/src/vendorcode/amd/fsp/mendocino/dmi_info.h @@ -141,7 +141,9 @@ typedef enum { LpDdr2MemType, ///< Assign 28 to LPDDR2 LpDdr3MemType, ///< Assign 29 to LPDDR3 LpDdr4MemType, ///< Assign 30 to LPDDR4 - LpDdr5MemType, ///< Assign 31 to LPDDR5 + Ddr5MemType = 0x22, ///< Assign 34 to DDR5 + LpDdr5MemType, ///< Assign 35 to LPDDR5 + LpDdr5xMemType, ///< Assign 36 to LPDDR5X } DMI_T17_MEMORY_TYPE; /// DMI Type 17 offset 13h - Type Detail |