diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2022-03-21 23:54:32 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-27 15:16:17 +0000 |
| commit | b6bb0c88be0d137964342caf01a3a368a5b92f2c (patch) | |
| tree | f54845a276ab92b51af126f2c6f9b806e4d57215 /src/vendorcode/amd/fsp | |
| parent | e102154a5e97151b2d42ca1a6e39f4d3956607e5 (diff) | |
vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping table
Sabrina only supports PCIe and no SATA or 10 GBit/s ethernet on its DXIO
lanes.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib5aa3abf21e20bbe846f1acfdc2755e97eca1e63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63121
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/fsp')
| -rw-r--r-- | src/vendorcode/amd/fsp/sabrina/platform_descriptors.h | 23 |
1 files changed, 7 insertions, 16 deletions
diff --git a/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h b/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h index ada9bbd209..cc6b78cfdd 100644 --- a/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h @@ -160,29 +160,20 @@ typedef struct __packed { } fsp_ddi_descriptor; /* - * Cezanne DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, - * configure bifurcation and other settings. Beware that the lane numbers in - * here are the logical and not the physical lane numbers! + * Sabrina DXIO Descriptor: Used for assigning lanes to PCIe engines, configure + * bifurcation and other settings. Beware that the lane numbers in here are the + * logical and not the physical lane numbers! * - * Cezanne DXIO logical lane to physical PCIe lane mapping: + * Sabrina DXIO logical lane to physical PCIe lane mapping: * - * logical | FT6 | AM4 - * --------|------------|---------------------- - * [00:03] | GPP[00:03] | GPP[00:03] - * [04:07] | GPP[04:07] | GPP[04:07]/HUB[00:03] - * [08:11] | GPP[08:11] | GFX[15:12] - * [12:15] | n/a | GFX[11:08] - * [16:23] | GFX[00:07] | GFX[07:0] + * logical | physical + * --------|------------ + * [00:03] | GPP[03:00] * * Different ports mustn't overlap or be assigned to the same lane(s). Within * ports with the same width the one with a higher start logical lane number * needs to be assigned to a higher PCIe root port number; ports of the same * size don't have to be assigned to consecutive PCIe root ports though. - * - * Lanes 2 and 3 can be mapped to the SATA controller on all packages; the FT6 - * platform additionally supports mapping lanes 8 and 9 to a SATA controller. - * On embedded SKUs lanes 0 and 1 can be mapped to the Gigabit Ethernet - * controllers. */ typedef struct __packed { uint8_t engine_type; // See dxio_engine_type |