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authorKeith Hui <buurin@gmail.com>2023-07-21 10:12:05 -0400
committerFelix Held <felix-coreboot@felixheld.de>2023-10-25 14:04:48 +0000
commit7039edd2da302bb63dc8930a8492b5d6940d7e33 (patch)
tree1359f7144bc20d3f4ba598c43f4afdf6dcff7b65 /src/vendorcode/amd/fsp/cezanne
parentb7cbb7c43157d45187abcf953d693152230a8120 (diff)
SNB+MRC boards: Migrate MRC settings to devicetree
For Sandy Bridge boards with MRC raminit support, migrate as much MRC settings to devicetree as possible, to stop mainboard code from needlessly overwriting entire PEI data structure, so they will not interfere with upcoming transition to one standard Haswell way of providing SPD info to northbridge. Some exceptions allowed are described below and in code comments. SPD-related items are kept out of devicetree for now. They will be migrated (with a different representation) with the Haswell SPD transition. google/{butterfly,link,parrot,stout} have max DDR3 frequency set in pei_data to 1600 (2*800), but in devicetree to 666. The reason for the difference seems to be problems with native raminit code. These are converted into ternaries tied to CONFIG_USE_NATIVE_RAMINIT, with an added "fix me" tag. asus/p8x7x-series also needs the same treatment, based on testing various memory on p8z77-m hardware. TEST=Builds on all affected boards. asus/p8z77-m still works with multiple RAM modules tested. Change-Id: Ie349a8f400eecca3cdbc196ea0790aebe0549e39 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
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