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authorMatt Papageorge <matthewpapa07@gmail.com>2021-10-08 13:08:46 -0500
committerRaul Rangel <rrangel@chromium.org>2021-10-11 15:55:35 +0000
commit0367c47eb08422c0b7364e5864d4e80199ea3699 (patch)
treede006d437aa9ed356de248f4a747c41e469afbc5 /src/vendorcode/amd/fsp/cezanne
parent8b17cb8a8c92a8cd13d2a75c5c5a1b0fe5e1191f (diff)
vc/amd/fsp/cezanne: Add UPD fsp_owns_pcie_resets to FSP-M for Cezanne
Update UPD to include option for FSP to de-assert PCIe reset GPIOs as specified in the DXIO descriptors. This change requires FSP version 1.0.4 revision 2 otherwise setting this value does affect any FSP behavior. BUG=b:199780346 TEST=Verify toggling this value is reflected in FSP Cq-Depend: chrome-internal:4170351 Change-Id: I0dee05fb0a650f026c2f09581117fa7fb5f6a90a Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/vendorcode/amd/fsp/cezanne')
-rw-r--r--src/vendorcode/amd/fsp/cezanne/FspmUpd.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
index 7cb788e175..f21ca42169 100644
--- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
@@ -26,7 +26,8 @@ typedef struct __packed {
/** Offset 0x0078**/ uint32_t serial_port_refclk;
/** Offset 0x007C**/ uint32_t serial_reserved;
/** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52];
- /** Offset 0x0358**/ uint8_t pcie_reserved[52];
+ /** Offset 0x0358**/ uint8_t fsp_owns_pcie_resets;
+ /** Offset 0x0359**/ uint8_t pcie_reserved[51];
/** Offset 0x038C**/ uint32_t ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT];
/** Offset 0x03A0**/ uint8_t ddi_reserved[6];
/** Offset 0x03A6**/ uint8_t ccx_down_core_mode;