diff options
| author | Julian Schroeder <julianmarcusschroeder@gmail.com> | 2021-05-11 10:44:13 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-26 15:15:53 +0000 |
| commit | d2f3308ad7efd01a2d23749aa4ccc6bc5efc8a56 (patch) | |
| tree | 2200586bb2ba0a5dabf6acf60dcfedcdc40adbe0 /src/vendorcode/amd/fsp/cezanne/FspUsb.h | |
| parent | e84a014ee6121424593ded21591c3e759847b784 (diff) | |
soc/amd/cezanne: add support for the changed AMD FSP API for USB PHY
The AMD FSP is using a new structure for USB and USB C phy settings.
This patch removes old, unused structures, adds the new one and
enables the devicetree interface for it.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Diffstat (limited to 'src/vendorcode/amd/fsp/cezanne/FspUsb.h')
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/FspUsb.h | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/vendorcode/amd/fsp/cezanne/FspUsb.h b/src/vendorcode/amd/fsp/cezanne/FspUsb.h new file mode 100644 index 0000000000..6563cacc81 --- /dev/null +++ b/src/vendorcode/amd/fsp/cezanne/FspUsb.h @@ -0,0 +1,56 @@ +#ifndef __FSPUSB_H__ +#define __FSPUSB_H__ + +#include <FspUpd.h> + +#define USB2_PORT_COUNT 8 +#define USB3_PORT_COUNT 4 +#define USBC_COMBO_PHY_COUNT 2 + +struct fch_usb2_phy { + uint8_t compdstune; ///< COMPDSTUNE + uint8_t sqrxtune; ///< SQRXTUNE + uint8_t txfslstune; ///< TXFSLSTUNE + uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE + uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE + uint8_t txrisetune; ///< TXRISETUNE + uint8_t txvreftune; ///< TXVREFTUNE + uint8_t txhsxvtune; ///< TXHSXVTUNE + uint8_t txrestune; ///< TXRESTUNE +} __packed; + +struct fch_usb3_phy { + uint8_t tx_term_ctrl; ///< tx_term_ctrl + uint8_t rx_term_ctrl; ///< rx_term_ctrl + uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN + uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL +} __packed; + +#define USB0_PORT0 0 +#define USB0_PORT1 1 +#define USB0_PORT2 1 +#define USB0_PORT3 3 +#define USB1_PORT0 (0<<2) +#define USB1_PORT1 (1<<2) +#define USB1_PORT2 (1<<2) +#define USB1_PORT3 (3<<2) + +#define USB_COMBO_PHY_MODE_USB_C 0 +#define USB_COMBO_PHY_MODE_USB_ONLY 1 +#define USB_COMBO_PHY_MODE_USB_DPM 2 +#define USB_COMBO_PHY_MODE_USB_DPP 3 + +struct usb_phy_config { + uint8_t Version_Major; ///< USB IP version + uint8_t Version_Minor; ///< USB IP version + uint8_t TableLength; ///< TableLength + uint8_t Reserved0; + struct fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength + struct fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment + uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP + uint8_t Reserved2[4]; +} __packed; + +#endif |