diff options
| author | Patrick Georgi <pgeorgi@google.com> | 2021-02-12 13:49:11 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-15 11:30:40 +0000 |
| commit | 6b688f5329e560ef432f6ea281b2fe3d905ef297 (patch) | |
| tree | 831ff654f7477b293421e38b8ed880f2cc740386 /src/vendorcode/amd/cimx/sb900 | |
| parent | 036d66be051c4aeeac3b6220974e93645489c27d (diff) | |
src: use ARRAY_SIZE where possible
Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci
Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/cimx/sb900')
| -rw-r--r-- | src/vendorcode/amd/cimx/sb900/SBPort.c | 3 | ||||
| -rw-r--r-- | src/vendorcode/amd/cimx/sb900/Sata.c | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/cimx/sb900/SbCmn.c | 3 |
3 files changed, 5 insertions, 3 deletions
diff --git a/src/vendorcode/amd/cimx/sb900/SBPort.c b/src/vendorcode/amd/cimx/sb900/SBPort.c index 90e878e1a6..75df24655c 100644 --- a/src/vendorcode/amd/cimx/sb900/SBPort.c +++ b/src/vendorcode/amd/cimx/sb900/SBPort.c @@ -330,7 +330,8 @@ sbPowerOnInit ( // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14)); // } //Program power on pci init table - programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) ); + programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), + ARRAY_SIZE(sbPorInitPciTable)); programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr)); diff --git a/src/vendorcode/amd/cimx/sb900/Sata.c b/src/vendorcode/amd/cimx/sb900/Sata.c index 9d1655c164..397ed7d0ab 100644 --- a/src/vendorcode/amd/cimx/sb900/Sata.c +++ b/src/vendorcode/amd/cimx/sb900/Sata.c @@ -487,7 +487,7 @@ sataInitBeforePciEnum ( // RPR 9.5 SATA PHY Programming Sequence pPhyTable = (SATAPHYSETTING*)FIXUP_PTR (&sataPhyTable[0]); - for (i = 0; i < (sizeof (sataPhyTable) / sizeof (SATAPHYSETTING)); i++) { + for (i = 0; i < ARRAY_SIZE(sataPhyTable); i++) { RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG80, AccWidthUint16 | S3_SAVE, 0x00, pPhyTable->wPhyCoreControl); RWPCI ((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG98, AccWidthUint32 | S3_SAVE, 0x00, pPhyTable->dwPhyFineTune); ++pPhyTable; diff --git a/src/vendorcode/amd/cimx/sb900/SbCmn.c b/src/vendorcode/amd/cimx/sb900/SbCmn.c index 1767ea1f24..b1784d7ddd 100644 --- a/src/vendorcode/amd/cimx/sb900/SbCmn.c +++ b/src/vendorcode/amd/cimx/sb900/SbCmn.c @@ -397,7 +397,8 @@ commonInitEarlyBoot ( //Make BAR registers of smbus visible. RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0); //Early post initialization of pci config space - programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) ); + programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), + ARRAY_SIZE(sbEarlyPostByteInitTable)); if ( pConfig->BuildParameters.SmbusSsid != 0 ) { RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid); } |