diff options
| author | Kerry She <shekairui@gmail.com> | 2011-08-18 18:44:00 +0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-09-07 01:10:05 +0200 |
| commit | 6209c8299a4bdcdb51cd6bf0c43c571ed575ad96 (patch) | |
| tree | 843a812c073191dd08315f3a4791f0b66480208d /src/vendorcode/amd/cimx/sb800/SBPOR.c | |
| parent | feed329a0c006968242aa3065506b5f37f4308d4 (diff) | |
AMD SB800 southbridge update
This patch enables access to the registers of the hardware monitor
logical device in the superio via isa ports 0x295/0x296.
Previously this was not enabled in the SB8xx LPC device.
This is required for initialisation in init_hwm() in
src/superio/winbond/w83627hf/superio.c and also by OS-level
sensor monitoring such as lm-sensors to access temperature,
fan monitoring and control and voltage registers.
asrock/e350m1 and advansus/a785e-i mainboard changes are included herein.
Change-Id: I2176885549277b335c0c41b48457d09b9b76b703
Signed-off-by: Per Hansen <perh52@runbox.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/159
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/cimx/sb800/SBPOR.c')
| -rw-r--r-- | src/vendorcode/amd/cimx/sb800/SBPOR.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/vendorcode/amd/cimx/sb800/SBPOR.c b/src/vendorcode/amd/cimx/sb800/SBPOR.c index 33d09d622e..daf13c719c 100644 --- a/src/vendorcode/amd/cimx/sb800/SBPOR.c +++ b/src/vendorcode/amd/cimx/sb800/SBPOR.c @@ -144,6 +144,7 @@ sbPowerOnInit ( UINT8 cimSataMode; UINT8 cimSpiFastReadEnable; UINT8 cimSpiFastReadSpeed; + UINT8 cimSioHwmPortEnable; UINT8 SataPortNum; cimNbSbGen2 = pConfig->NbSbGen2; @@ -155,12 +156,14 @@ sbPowerOnInit ( cimSpiFastReadEnable = cimSpiFastReadEnableDefault; } cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed; + cimSioHwmPortEnable = pConfig->SioHwmPortEnable; #if SB_CIMx_PARAMETER == 0 cimNbSbGen2 = cimNbSbGen2Default; cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default); cimSataMode = (UINT8) ((cimSataMode & 0x0F) | (cimSATARefClkSelDefault + cimSATARefDivSelDefault)); cimSpiFastReadEnable = cimSpiFastReadEnableDefault; cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault; + cimSioHwmPortEnable = cimSioHwmPortEnableDefault; #endif // SB800 Only Enabled (Mmio_mem_enablr) // Default value is correct @@ -200,6 +203,12 @@ sbPowerOnInit ( // Set Build option into SB WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress)); + if (cimSioHwmPortEnable) { + // Use Wide IO Port 1 to provide access to the superio HWM registers. + WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG66 , AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioHwmBaseAddress)); + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG48 + 3, AccWidthUint8 | S3_SAVE, 0xFF, BIT0); // Wide IO Port 1: enable + RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG74 , AccWidthUint8 | S3_SAVE, 0xFF, BIT2); // set width 0:512, 1:16 bytes + } RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress)); RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1)); // Enabled SMBUS0/SMBUS1 (ASF) Base Address @@ -354,4 +363,4 @@ sbPowerOnInit ( // Set PMx88[5]to enable LdtStp# output to do the C3 or FidVid transation RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG88, AccWidthUint8, 0xFF, BIT5); -}
\ No newline at end of file +} |