diff options
author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-06-22 09:52:12 +0200 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-10 10:18:37 +0000 |
commit | ad1456f0d7c9fcfcf6ef78969cb0e1ac6f17739a (patch) | |
tree | b9583389468bb967af57ffdc123f51656bcd4443 /src/vendorcode/amd/cimx/sb800/SBCMN.c | |
parent | e29a6ac16a9f478fc00ce7cb83f3779954e3168d (diff) |
vendorcode/amd: Move 'static' to the beginning of declaration
Change-Id: Ib9934f103262c57af076bd27d97c3166d8f2318b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode/amd/cimx/sb800/SBCMN.c')
-rw-r--r-- | src/vendorcode/amd/cimx/sb800/SBCMN.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c index 8e9f0e2814..ab203a111d 100644 --- a/src/vendorcode/amd/cimx/sb800/SBCMN.c +++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c @@ -83,7 +83,7 @@ VOID sbUsbPhySetting (IN UINT32 Value); * sbEarlyPostByteInitTable - PCI device registers initial during early POST. * */ -const static REG8MASK sbEarlyPostByteInitTable[] = +static const REG8MASK sbEarlyPostByteInitTable[] = { // SMBUS Device (Bus 0, Dev 20, Func 0) {0x00, SMBUS_BUS_DEV_FUN, 0}, @@ -134,7 +134,7 @@ const static REG8MASK sbEarlyPostByteInitTable[] = * sbPmioEPostInitTable - Southbridge ACPI MMIO initial during POST. * */ -const static AcpiRegWrite sbPmioEPostInitTable[] = +static const AcpiRegWrite sbPmioEPostInitTable[] = { // HPET workaround {PMIO_BASE >> 8, SB_PMIOA_REG54 + 3, 0xFC, BIT0 + BIT1}, @@ -251,7 +251,7 @@ const static AcpiRegWrite sbPmioEPostInitTable[] = * abTblEntry800 - AB-Link Configuration Table for SB800 * */ -const static ABTBLENTRY abTblEntry800[] = +static const ABTBLENTRY abTblEntry800[] = { // RPR Enable downstream posted transactions to pass non-posted transactions. {ABCFG, SB_ABCFG_REG10090, BIT8 + BIT16, BIT8 + BIT16}, @@ -297,7 +297,7 @@ const static ABTBLENTRY abTblEntry800[] = * SbPcieOrderRule - AB-Link Configuration Table for ablink Post Pass Np Downstream/Upstream Feature * */ -const static ABTBLENTRY SbPcieOrderRule[] = +static const ABTBLENTRY SbPcieOrderRule[] = { // abPostPassNpDownStreamTbl {ABCFG, SB_ABCFG_REG10060, BIT31, BIT31}, |