diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-03-23 21:46:17 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-25 20:13:00 +0000 |
| commit | 2fe012633a3bc35239947e19609447c36f4cd266 (patch) | |
| tree | 946b796068be7361118ec814f1ab57c1076c9558 /src/vendorcode/amd/cimx/sb800/SBCMN.c | |
| parent | 3ba6f8cdf8d95607c8efd8f6d18a9fffc9983e1e (diff) | |
amd/cimx/sb800: Fix building with clang
These are all set but unused variable problems.
Change-Id: I40aaa1d1cdd90731a23142f1f7a0f67a45915f25
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/vendorcode/amd/cimx/sb800/SBCMN.c')
| -rw-r--r-- | src/vendorcode/amd/cimx/sb800/SBCMN.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c index 3d4ce82b6d..149e1defce 100644 --- a/src/vendorcode/amd/cimx/sb800/SBCMN.c +++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c @@ -330,14 +330,11 @@ commonInitEarlyBoot ( UINT32 abValue; UINT16 dwTempVar; CPUID_DATA CpuId; - UINT8 cimNativepciesupport; UINT8 cimIrConfig; UINT8 Data; - cimNativepciesupport = (UINT8) pConfig->NativePcieSupport; cimIrConfig = (UINT8) pConfig->IrConfig; #if SB_CIMx_PARAMETER == 0 - cimNativepciesupport = cimNativepciesupportDefault; cimIrConfig = cimIrConfigDefault; #endif @@ -518,8 +515,6 @@ commonInitEarlyPost ( UINT8 dbPortStatus; UINT8 cimSpreadSpectrum; UINT32 cimSpreadSpectrumType; - AMDSBCFG* pTmp; - pTmp = pConfig; cimSpreadSpectrum = pConfig->SpreadSpectrum; cimSpreadSpectrumType = pConfig->BuildParameters.SpreadSpectrumType; @@ -606,13 +601,11 @@ abLinkInitBeforePciEnum ( { UINT32 cimResetCpuOnSyncFlood; ABTBLENTRY *pAbTblPtr; - AMDSBCFG* Temp; cimResetCpuOnSyncFlood = pConfig->ResetCpuOnSyncFlood; #if SB_CIMx_PARAMETER == 0 cimResetCpuOnSyncFlood = cimResetCpuOnSyncFloodDefault; #endif - Temp = pConfig; if ( pConfig->SbPcieOrderRule ) { pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&SbPcieOrderRule[0]); abcfgTbl (pAbTblPtr); @@ -800,9 +793,7 @@ c3PopupSetting ( IN AMDSBCFG* pConfig ) { - AMDSBCFG* Temp; UINT8 dbValue; - Temp = pConfig; //RPR C-State and VID/FID Change dbValue = getNumberOfCpuCores (); if (dbValue > 1) { |