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authorBen Gardner <gardner.ben@gmail.com>2016-03-11 16:29:54 -0600
committerMartin Roth <martinroth@google.com>2016-03-14 18:24:10 +0100
commit08bfba4f02f8d437357dba1a9523a9891ebd1351 (patch)
treecef95f0bc51fab37270535492447a4770fdb9eb4 /src/vendorcode/amd/cimx/sb800/AMDLIB.c
parent59be62480e2b9f51a66b5da3d552ae47425db9c6 (diff)
intel/fsp_baytrail: Enable LPSS in ACPI mode
This change fixes LPSS ACPI mode. Previously, enabling ACPI mode would result in unusable devices, as the resources were set to 0 and the devices were disabled. lpss.c was copied from intel/baytrail with a few minor adjustment for the different config structure. ACPI mode requires setting PcdLpssSioEnablePciMode==LPSS_PCI_MODE_DISABLE and applying the patch that disables clearing gnvs. https://review.coreboot.org/#/c/14040/ This doesn't handle the case where the FSP has PcdLpssSioEnablePciMode set to disable and the devicetree set to default. Change-Id: I12fffea3820ed948defe7a4f11af6b6363402560 Signed-off-by: Ben Gardner <gardner.ben@gmail.com> Reviewed-on: https://review.coreboot.org/14042 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode/amd/cimx/sb800/AMDLIB.c')
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