diff options
| author | WANG Siyuan <wangsiyuanbuaa@gmail.com> | 2013-07-31 16:55:26 +0800 |
|---|---|---|
| committer | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2013-10-15 05:01:11 +0200 |
| commit | 7b6d412dbc4e5c11d3dd7890abf0edf279b3f504 (patch) | |
| tree | 9d41c0b6299cab6a90616fdbc3e31d6ef67797c6 /src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h | |
| parent | f8bf5a10c599ef071998bbc3f16e9e3d7fcdb6eb (diff) | |
vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7
The platform initialization (PI) code v1.0.0.7 for Kabini has some
enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH
bug fix (RTC) and so on.
Use the name Kabini instead of Kerala everywhere.
Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0
as used in `AGESA_VERSION_STRING`.
Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3935
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h')
| -rw-r--r-- | src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h index a469eb35a3..3ac61d88b7 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h +++ b/src/vendorcode/amd/agesa/f16kb/Proc/GNB/Common/GnbRegistersKB.h @@ -3269,9 +3269,21 @@ typedef union { #define DxFxxE4_xA0_LcL1ImmediateAck_OFFSET 23 #define DxFxxE4_xA0_LcL1ImmediateAck_WIDTH 1 #define DxFxxE4_xA0_LcL1ImmediateAck_MASK 0x800000 -#define DxFxxE4_xA0_Reserved_31_24_OFFSET 24 -#define DxFxxE4_xA0_Reserved_31_24_WIDTH 8 -#define DxFxxE4_xA0_Reserved_31_24_MASK 0xFF000000 +#define DxFxxE4_xA0_Reserved_24_24_OFFSET 24 +#define DxFxxE4_xA0_Reserved_24_24_WIDTH 1 +#define DxFxxE4_xA0_Reserved_24_24_MASK 0x01000000 +#define DxFxxE4_xA0_Reserved_26_25_OFFSET 25 +#define DxFxxE4_xA0_Reserved_26_25_WIDTH 2 +#define DxFxxE4_xA0_Reserved_26_25_MASK 0x06000000 +#define DxFxxE4_xA0_Reserved_27_27_OFFSET 27 +#define DxFxxE4_xA0_Reserved_27_27_WIDTH 1 +#define DxFxxE4_xA0_Reserved_27_27_MASK 0x08000000 +#define DxFxxE4_xA0_Reserved_28_28_OFFSET 28 +#define DxFxxE4_xA0_Reserved_28_28_WIDTH 1 +#define DxFxxE4_xA0_Reserved_28_28_MASK 0x10000000 +#define DxFxxE4_xA0_Reserved_31_29_OFFSET 29 +#define DxFxxE4_xA0_Reserved_31_29_WIDTH 3 +#define DxFxxE4_xA0_Reserved_31_29_MASK 0xE0000000 /// DxFxxE4_xA0 typedef union { @@ -3282,7 +3294,11 @@ typedef union { UINT32 LcL1Inactivity:4; ///< UINT32 Reserved_22_16:7; ///< UINT32 LcL1ImmediateAck:1; ///< - UINT32 Reserved_31_24:8; ///< + UINT32 Reserved_24_24:1; ///< + UINT32 Reserved_26_25:2; ///< + UINT32 Reserved_27_27:1; ///< + UINT32 Reserved_28_28:1; ///< + UINT32 Reserved_31_29:3; ///< } Field; |