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authorBruce Griffith <Bruce.Griffith@se-eng.com>2013-06-25 14:14:14 -0600
committerBruce Griffith <Bruce.Griffith@se-eng.com>2013-08-06 19:21:11 +0200
commit5697df2a84b52f0979d4807fc293dea311e46662 (patch)
tree96406fbd910f57d0d6e087778e8e7a5e2480ddcf /src/vendorcode/amd/agesa/f16kb/Lib
parentee7cd8d85d3339291d8f5e72d2d35798164ac0bb (diff)
AMD AGESA: Add missing breaks to switch statement in one file
This is the same patch as an earlier one applied to family 15 [1]. Static analysis often flags case statements that do not include a terminating "break;" statement. Eclipse's CODAN is an example of this. This changelist modifies amdlib.c to terminate case statements with "break;". [1] e44a89f amd/agesa/f15/Lib/amdlib.c: Add missing breaks ... Change-Id: Ibd1ae6f2b52fde07de3d978d174975f4d93647ab Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/3839 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin@se-eng.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb/Lib')
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c9
1 files changed, 8 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
index 67078a3b7d..99a28b1c08 100644
--- a/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
+++ b/src/vendorcode/amd/agesa/f16kb/Lib/amdlib.c
@@ -297,6 +297,7 @@ LibAmdReadCpuReg (
break;
default:
*Value = -1;
+ break;
}
}
VOID
@@ -325,7 +326,7 @@ LibAmdWriteCpuReg (
__writedr (7, Value);
break;
default:
- ;
+ break;
}
}
VOID
@@ -504,6 +505,7 @@ LibAmdIoRead (
break;
default:
ASSERT (FALSE);
+ break;
}
}
@@ -541,6 +543,7 @@ LibAmdIoWrite (
break;
default:
ASSERT (FALSE);
+ break;
}
}
@@ -641,6 +644,7 @@ LibAmdMemRead (
break;
default:
ASSERT (FALSE);
+ break;
}
}
@@ -679,6 +683,7 @@ LibAmdMemWrite (
break;
default:
ASSERT (FALSE);
+ break;
}
}
/*---------------------------------------------------------------------------------------*/
@@ -1297,6 +1302,7 @@ LibAmdGetDataFromPtr (
break;
default:
IDS_ERROR_TRAP;
+ break;
}
}
@@ -1336,6 +1342,7 @@ LibAmdAccessWidth (
default:
Width = 0;
IDS_ERROR_TRAP;
+ break;
}
return Width;
}