vendorcode/amd/agesa/fam16kb: Fix improper use of .data

AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.

TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.

Change-Id: Ie8817434ee0bc6c195eabe090f195512c0043ae5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

7 files changed, 80 insertions, 81 deletions

diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionCpuFeaturesInstall.h
index 61c750aafb..dde99f2463 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/OptionCpuFeaturesInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionCpuFeaturesInstall.h
@@ -59,7 +59,7 @@
 #include "OptionPrefetchModeInstall.h"
 #include "OptionPreserveMailboxInstall.h"
 
-CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
+CONST CPU_FEATURE_DESCRIPTOR* ROMDATA CONST SupportedCpuFeatureList[] =
 {
   OPTION_MSG_BASED_C1E_FEAT
   OPTION_L3_FEAT
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionFamily16hInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionFamily16hInstall.h
index f85876541a..8604df7371 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/OptionFamily16hInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionFamily16hInstall.h
@@ -87,7 +87,7 @@
 
 
     #if USES_REGISTER_TABLES == TRUE
-      CONST REGISTER_TABLE ROMDATA *F16KbRegisterTables[] =
+      CONST REGISTER_TABLE ROMDATA * CONST F16KbRegisterTables[] =
       {
         #if MODEL_SPECIFIC_PCI == TRUE
           &F16KbPciRegisterTableBeforeApLaunch,
@@ -223,7 +223,7 @@
         #define F16_KB_UCODE_7001 CpuF16KbId7001MicrocodePatch,
       #endif
 
-      CONST UINT8 ROMDATA *CpuF16KbMicroCodePatchArray[] =
+      CONST UINT8 ROMDATA * CONST CpuF16KbMicroCodePatchArray[] =
       {
         F16_KB_UCODE_7001
         F16_KB_UCODE_7000
@@ -253,7 +253,7 @@
 #if USES_REGISTER_TABLES == TRUE
   extern CONST REGISTER_TABLE ROMDATA F16PciUnknownRegisterTable;
   extern CONST REGISTER_TABLE ROMDATA F16MsrUnknownRegisterTable;
-  CONST REGISTER_TABLE ROMDATA *F16UnknownRegisterTables[] =
+  CONST REGISTER_TABLE ROMDATA * CONST F16UnknownRegisterTables[] =
   {
     &F16PciUnknownRegisterTable,
     &F16MsrUnknownRegisterTable
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h
index 64b71ef713..05db0b3e5f 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionFchInstall.h
@@ -832,7 +832,7 @@
       //
       // Define task list for InitReset phase
       //
-      FCH_TASK_ENTRY ROMDATA  *FchInitResetTaskTable[] = {
+      FCH_TASK_ENTRY ROMDATA  * CONST FchInitResetTaskTable[] = {
         InstallFchInitResetHwAcpiP,
         InstallFchInitResetAb,
         InstallFchInitResetSpi,
@@ -859,7 +859,7 @@
       //
       // Define task list for InitEnv phase
       //
-      FCH_TASK_ENTRY ROMDATA  *FchInitEnvTaskTable[] = {
+      FCH_TASK_ENTRY ROMDATA  * CONST FchInitEnvTaskTable[] = {
         InstallFchInitEnvHwAcpiP,
         InstallFchInitEnvPcib,
         InstallFchInitEnvPcie,
@@ -892,7 +892,7 @@
       //
       // Define task list for InitMid phase
       //
-      FCH_TASK_ENTRY ROMDATA  *FchInitMidTaskTable[] = {
+      FCH_TASK_ENTRY ROMDATA  * CONST FchInitMidTaskTable[] = {
         InstallFchInitMidImc,
         InstallFchInitMidUsb,
         InstallFchInitMidUsbEhci,
@@ -913,7 +913,7 @@
       //
       // Define task list for InitLate phase
       //
-      FCH_TASK_ENTRY ROMDATA  *FchInitLateTaskTable[] = {
+      FCH_TASK_ENTRY ROMDATA  * CONST FchInitLateTaskTable[] = {
         InstallFchInitLatePcie,
         InstallFchInitLatePcib,
         InstallFchInitLateSpi,
@@ -940,7 +940,7 @@
       //
       // Define task list for S3 resume before PCI phase
       //
-      FCH_TASK_ENTRY ROMDATA  *FchInitS3EarlyTaskTable[] = {
+      FCH_TASK_ENTRY ROMDATA  * CONST FchInitS3EarlyTaskTable[] = {
         InstallFchInitEnvPcie,
         InstallFchInitEnvPcib,
         InstallFchInitEnvGpp,
@@ -967,7 +967,7 @@
       //
       // Define task list for S3 resume after PCI phase
       //
-      FCH_TASK_ENTRY ROMDATA  *FchInitS3LateTaskTable[] = {
+      FCH_TASK_ENTRY ROMDATA  * CONST FchInitS3LateTaskTable[] = {
         InstallFchInitLatePcie,
         InstallFchInitLatePcib,
         InstallFchInitLateSpi,
@@ -991,7 +991,7 @@
       };
     #endif
   #endif
-  FCH_TASK_ENTRY   *FchGppHotplugSmiCallbackPtr = InstallHpSmiCallback;
+  FCH_TASK_ENTRY   * CONST FchGppHotplugSmiCallbackPtr = InstallHpSmiCallback;
 
 
 #else   // FCH_SUPPORT == FALSE
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h
index 7b1447199a..3190bf3229 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionGnbInstall.h
@@ -91,7 +91,7 @@
   #if (GNB_TYPE_KB == TRUE)
     #include "GnbInitKBInstall.h"
   #endif
-  GNB_SERVICE   *ServiceTable = SERVICES_POINTER;
+  CONST GNB_SERVICE   * CONST ServiceTable = SERVICES_POINTER;
 
 //---------------------------------------------------------------------------------------------------
 // BUILD options
@@ -292,7 +292,7 @@
     #define CFG_UMA_STEERING             0
   #endif
 
-  GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = {
+  CONST GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = {
     CFG_IGFX_AS_PCIE_EP,
     CFG_LCLK_DEEP_SLEEP_EN,
     CFG_LCLK_DPM_EN,
@@ -389,7 +389,7 @@
       #define OPTION_PCIEEARLYINTERFACEKB_ENTRY
     #endif
   //---------------------------------------------------------------------------------------------------
-    OPTION_GNB_CONFIGURATION  GnbEarlyFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbEarlyFeatureTable[] = {
       OPTION_GNBEARLYINTERFACETN_ENTRY
       OPTION_GNBEARLYINTERFACEKB_ENTRY
       OPTION_PCIECONFIGURATIONMAP_ENTRY
@@ -433,7 +433,7 @@
     #endif
 
 
-    OPTION_GNB_CONFIGURATION  GnbEarlierFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbEarlierFeatureTable[] = {
       OPTION_PCIECONFIGURATIONINIT_ENTRY
       OPTION_GNBEARLIERINTERFACETN_ENTRY
       OPTION_GNBEARLIERINTERFACEKB_ENTRY
@@ -522,7 +522,7 @@
     #endif
 
   //---------------------------------------------------------------------------------------------------
-    OPTION_GNB_CONFIGURATION  GnbPostFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbPostFeatureTable[] = {
       OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
       OPTION_PCIEPOSTEARLYINTERFACEKB_ENTRY
       OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
@@ -531,7 +531,7 @@
       {0, NULL, EndGnbTestPoints}
     };
 
-    OPTION_GNB_CONFIGURATION  GnbPostAfterDramFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbPostAfterDramFeatureTable[] = {
       OPTION_GNBPOSTINTERFACETN_ENTRY
       OPTION_GNBPOSTINTERFACEKB_ENTRY
       OPTION_PCIEPOSTINTERFACETN_ENTRY
@@ -605,7 +605,7 @@
 
   //---------------------------------------------------------------------------------------------------
 
-    OPTION_GNB_CONFIGURATION  GnbEnvFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbEnvFeatureTable[] = {
       OPTION_GNBENVINTERFACETN_ENTRY
       OPTION_GNBENVINTERFACEKB_ENTRY
       OPTION_PCIEENVINTERFACETN_ENTRY
@@ -747,7 +747,7 @@
       #define OPTION_GNBNBIOAPICINTERFACE_ENTRY
     #endif
   //---------------------------------------------------------------------------------------------------
-    OPTION_GNB_CONFIGURATION  GnbMidFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbMidFeatureTable[] = {
       OPTION_GFXCONFIGMIDINTERFACE_ENTRY
       OPTION_GFXMIDINTERFACETN_ENTRY
       OPTION_GFXMIDINTERFACEKB_ENTRY
@@ -797,7 +797,7 @@
 
       #if (GNB_TYPE_KB == TRUE)
         extern F_ALIB_GET PcieAlibGetBaseTableKB;
-        F_ALIB_GET  *AlibGetBaseTableV2 = PcieAlibGetBaseTableKB;
+        F_ALIB_GET  * CONST AlibGetBaseTableV2 = PcieAlibGetBaseTableKB;
         extern F_ALIB_UPDATE PcieAlibUpdateVoltageData;
         extern F_ALIB_UPDATE PcieAlibUpdatePcieData;
         #undef ALIB_CALL_TABLEV2
@@ -806,11 +806,11 @@
       #endif
 
 
-      F_ALIB_UPDATE* AlibDispatchTable [] = {
+      F_ALIB_UPDATE* CONST AlibDispatchTable [] = {
         ALIB_CALL_TABLE
         NULL
       };
-      F_ALIB_UPDATE* AlibDispatchTableV2 [] = {
+      F_ALIB_UPDATE* CONST AlibDispatchTableV2 [] = {
         ALIB_CALL_TABLEV2
         NULL
       };
@@ -823,12 +823,12 @@
         #define OPTION_PCIEALIBV2FEATURE_ENTRY              {AMD_FAMILY_KB, PcieAlibV2Feature, TpGnbPcieAlibFeature},
       #endif
     #else
-      F_ALIB_GET  *AlibGetBaseTable = NULL;
-      F_ALIB_GET  *AlibGetBaseTableV2 = NULL;
-      F_ALIB_UPDATE* AlibDispatchTable [] = {
+      F_ALIB_GET  * CONST AlibGetBaseTable = NULL;
+      F_ALIB_GET  * CONST AlibGetBaseTableV2 = NULL;
+      F_ALIB_UPDATE* CONST AlibDispatchTable [] = {
         NULL
       };
-      F_ALIB_UPDATE* AlibDispatchTableV2 [] = {
+      F_ALIB_UPDATE* CONST AlibDispatchTableV2 [] = {
         NULL
       };
       #define OPTION_PCIEALIBFEATURE_ENTRY
@@ -855,7 +855,7 @@
       #define OPTIONIOMMUSCRATCHMEMORYLATE_ENTRY
     #endif
   //---------------------------------------------------------------------------------------------------
-    OPTION_GNB_CONFIGURATION  GnbLateFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbLateFeatureTable[] = {
       #if (GNB_TYPE_TN == TRUE)
         OPTION_PCIEALIBFEATURE_ENTRY
       #endif
@@ -880,7 +880,7 @@
       #define OPTION_GFXINITSVIEW_ENTRY
     #endif
 
-    OPTION_GNB_CONFIGURATION  GnbS3SaveFeatureTable[] = {
+    CONST OPTION_GNB_CONFIGURATION  GnbS3SaveFeatureTable[] = {
       OPTION_GFXINITSVIEW_ENTRY
       {0, NULL, EndGnbTestPoints}
     };
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h
index c5484f1f1c..64a5b30bce 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionMemoryInstall.h
@@ -219,7 +219,7 @@ BOOLEAN MemFS3DefConstructorRet (
   #endif
 
 
-  MEM_FLOW_CFG* memFlowControlInstalled[] = {
+  MEM_FLOW_CFG* CONST memFlowControlInstalled[] = {
     MEM_MAIN_FLOW_CONTROL_PTR_TN
     MEM_MAIN_FLOW_CONTROL_PTR_KB
     NULL
@@ -478,7 +478,7 @@ BOOLEAN MemFS3DefConstructorRet (
     #endif
     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 
-    MEM_FEAT_BLOCK_NB  MemFeatBlockTN = {
+    CONST MEM_FEAT_BLOCK_NB  MemFeatBlockTN = {
       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
       MEM_FEATURE_ONLINE_SPARE,
       MEM_FEATURE_BANK_INTERLEAVE,
@@ -572,7 +572,7 @@ BOOLEAN MemFS3DefConstructorRet (
     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
     #define MEM_FEATURE_TRAINING  MemFStandardTraining
 
-    MEM_FEAT_BLOCK_NB  MemFeatBlockKB = {
+    CONST MEM_FEAT_BLOCK_NB  MemFeatBlockKB = {
       MEM_FEAT_BLOCK_NB_STRUCT_VERSION,
       MEM_FEATURE_ONLINE_SPARE,
       MEM_FEATURE_BANK_INTERLEAVE,
@@ -608,7 +608,7 @@ BOOLEAN MemFS3DefConstructorRet (
    * MAIN FEATURE BLOCK
    *---------------------------------------------------------------------------------------------------
    */
-  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
+  CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = {
     MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION,
     MEM_MAIN_FEATURE_TRAINING,
     MEM_MAIN_FEATURE_DIMM_EXCLUDE,
@@ -731,7 +731,7 @@ BOOLEAN MemFS3DefConstructorRet (
         #undef TECH_TRAIN_DQS_2D_DDR3
         #define TECH_TRAIN_DQS_2D_DDR3 MemTFeatDef
       #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3TN = {
+      CONST MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3TN = {
         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
         TECH_TRAIN_ENTER_HW_TRN_DDR3,
         TECH_TRAIN_SW_WL_DDR3,
@@ -871,7 +871,7 @@ BOOLEAN MemFS3DefConstructorRet (
         #undef TECH_TRAIN_DQS_2D_DDR3
         #define TECH_TRAIN_DQS_2D_DDR3 MemTFeatDef
       #endif
-      MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3KB = {
+      CONST MEM_TECH_FEAT_BLOCK  memTechTrainingFeatSequenceDDR3KB = {
         MEM_TECH_FEAT_BLOCK_STRUCT_VERSION,
         TECH_TRAIN_ENTER_HW_TRN_DDR3,
         TECH_TRAIN_SW_WL_DDR3,
@@ -916,13 +916,13 @@ BOOLEAN MemFS3DefConstructorRet (
 
 
   #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_END { MEM_NB_SUPPORT_STRUCT_VERSION, 0, 0, 0 }
-  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
+  CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_TN
     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR2_KB
     MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
   };
 
-  MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
+  CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_TN
     MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_KB
     MEM_TECH_ENABLE_TRAINING_SEQUENCE_END
@@ -933,7 +933,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *---------------------------------------------------------------------------------------------------
    */
-  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
+  OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = {    // Training flow control
     NB_TRAIN_FLOW_DDR2,
     NB_TRAIN_FLOW_DDR3,
   };
@@ -943,7 +943,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *---------------------------------------------------------------------------------------------------
    */
-  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
+  MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = {    // Types of technology installed
     MEM_TECH_CONSTRUCTOR_DDR2
     MEM_TECH_CONSTRUCTOR_DDR3
     NULL
@@ -968,7 +968,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *----------------------------------------------------------------------
    */
 
-  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
+  MEM_PLATFORM_CFG* CONST memPlatformTypeInstalled[] = {
     NULL
   };
   CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
@@ -981,7 +981,7 @@ BOOLEAN MemFS3DefConstructorRet (
    */
   #define MEM_PSC_FLOW_BLOCK_END NULL
   #define PSC_TBL_END NULL
-  #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
+  #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, CONST MEM_PSC_TABLE_BLOCK *)) memDefTrue
 
   #define PSC_TBL_TN_UDIMM3_S2D_FM2
   #define PSC_TBL_TN_SODIMM3_S2D_FS1
@@ -1143,7 +1143,7 @@ BOOLEAN MemFS3DefConstructorRet (
       #define PSC_TBL_TN_CS_TRI_FP2
     #endif
 
-    PSC_TBL_ENTRY* memPSCTblMaxFreqArrayTN[] = {
+    PSC_TBL_ENTRY* CONST  memPSCTblMaxFreqArrayTN[] = {
       PSC_TBL_TN_SODIMM3_MAX_FREQ_FS1
       PSC_TBL_TN_SODIMM3_MAX_FREQ_FP2
       PSC_TBL_RL_SODIMM3_MAX_FREQ_FP2
@@ -1156,36 +1156,36 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblDramTermArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblDramTermArrayTN[] = {
       PSC_TBL_TN_UDIMM3_DRAM_TERM
       PSC_TBL_TN_SODIMM3_DRAM_TERM
       PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblODTPatArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblODTPatArrayTN[] = {
       &TNOdtPatTblEnt,
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblSAOArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblSAOArrayTN[] = {
       PSC_TBL_TN_SODIMM3_SAO
       PSC_TBL_TN_SODWN_SODIMM3_SAO
       PSC_TBL_TN_UDIMM3_SAO
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblMR0WRArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblMR0WRArrayTN[] = {
       &TNMR0WrTblEntry,
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblMR0CLArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblMR0CLArrayTN[] = {
       &TNMR0CLTblEntry,
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblGenArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblGenArrayTN[] = {
       &TNDdr3CKETriEnt,
       PSC_TBL_TN_CLK_DIS_FM2
       PSC_TBL_TN_ODT_TRI_FM2
@@ -1199,7 +1199,7 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblS2DArrayTN[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblS2DArrayTN[] = {
       PSC_TBL_TN_UDIMM3_S2D_FM2
       PSC_TBL_TN_SODIMM3_S2D_FS1
       PSC_TBL_TN_SODIMM3_S2D_FP2
@@ -1207,7 +1207,7 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    MEM_PSC_TABLE_BLOCK memPSCTblBlockTN = {
+    CONST MEM_PSC_TABLE_BLOCK memPSCTblBlockTN = {
       (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayTN,
       (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayTN,
       (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayTN,
@@ -1232,7 +1232,7 @@ BOOLEAN MemFS3DefConstructorRet (
     extern MEM_PSC_FLOW MemPGetMR0WrCL;
     extern MEM_PSC_FLOW MemPGetS2D;
 
-    MEM_PSC_FLOW_BLOCK memPlatSpecFlowTN = {
+    CONST MEM_PSC_FLOW_BLOCK memPlatSpecFlowTN = {
       &memPSCTblBlockTN,
       MemPGetMaxFreqSupported,
       MemPGetRttNomWr,
@@ -1382,7 +1382,7 @@ BOOLEAN MemFS3DefConstructorRet (
       #define PSC_TBL_KB_CS_TRI_FT3
     #endif
 
-    PSC_TBL_ENTRY* memPSCTblMaxFreqArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblMaxFreqArrayKB[] = {
       // 4 layer tables block
       PSC_TBL_KB_SODIMM3_MAX_FREQ_4L
       PSC_TBL_KB_SODWN_PLUS_SODIMM3_MAX_FREQ_4L
@@ -1397,7 +1397,7 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblDramTermArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblDramTermArrayKB[] = {
       PSC_TBL_KB_UDIMM3_DRAM_TERM_FT3
       PSC_TBL_KB_SODIMM3_DRAM_TERM
       PSC_TBL_KB_SODWN_PLUS_SODIMM3_DRAM_TERM
@@ -1405,13 +1405,13 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblODTPatArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblODTPatArrayKB[] = {
       &KB1DOdtPatTblEnt,
       &KB2DOdtPatTblEnt,
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblSAOArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblSAOArrayKB[] = {
       PSC_TBL_KB_SODIMM3_SAO
       PSC_TBL_KB_SODWN_PLUS_SODIMM3_SAO
       PSC_TBL_KB_SODWN_SAO
@@ -1419,17 +1419,17 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblMR0WRArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblMR0WRArrayKB[] = {
       &KBMR0WrTblEntry,
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblMR0CLArrayKB[] = {
+    PSC_TBL_ENTRY* CONST  memPSCTblMR0CLArrayKB[] = {
       &KBMR0CLTblEntry,
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblGenArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblGenArrayKB[] = {
       &KBDdr3CKETriEnt,
       PSC_TBL_KB_CLK_DIS_FT3
       PSC_TBL_KB_ODT_TRI_FT3
@@ -1437,13 +1437,13 @@ BOOLEAN MemFS3DefConstructorRet (
       PSC_TBL_END
     };
 
-    PSC_TBL_ENTRY* memPSCTblS2DArrayKB[] = {
+    PSC_TBL_ENTRY* CONST memPSCTblS2DArrayKB[] = {
       PSC_TBL_KB_UDIMM3_S2D_FT3
       PSC_TBL_KB_SODIMM3_S2D_FT3
       PSC_TBL_END
     };
 
-    MEM_PSC_TABLE_BLOCK memPSCTblBlockKB = {
+    CONST MEM_PSC_TABLE_BLOCK memPSCTblBlockKB = {
       (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayKB,
       (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayKB,
       (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayKB,
@@ -1468,7 +1468,7 @@ BOOLEAN MemFS3DefConstructorRet (
     extern MEM_PSC_FLOW MemPGetMR0WrCL;
     extern MEM_PSC_FLOW MemPGetS2D;
 
-    MEM_PSC_FLOW_BLOCK memPlatSpecFlowKB = {
+    CONST MEM_PSC_FLOW_BLOCK memPlatSpecFlowKB = {
       &memPSCTblBlockKB,
       MemPGetMaxFreqSupported,
       MemPGetRttNomWr,
@@ -1489,7 +1489,7 @@ BOOLEAN MemFS3DefConstructorRet (
   #endif
 
 
-  MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
+  CONST MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = {
     MEM_PSC_FLOW_BLOCK_TN
     MEM_PSC_FLOW_BLOCK_KB
     MEM_PSC_FLOW_BLOCK_END
@@ -1510,7 +1510,7 @@ BOOLEAN MemFS3DefConstructorRet (
   #else //#if (OPTION_LRDIMMS == FALSE)
     #define MEM_TECH_FEATURE_LRDIMM_INIT    MemTFeatDef
   #endif
-  MEM_TECH_LRDIMM memLrdimmSupported = {
+  CONST MEM_TECH_LRDIMM memLrdimmSupported = {
     MEM_TECH_LRDIMM_STRUCT_VERSION,
     MEM_TECH_FEATURE_LRDIMM_INIT
   };
@@ -1521,7 +1521,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *---------------------------------------------------------------------------------------------------
    */
-  MEM_FLOW_CFG* memFlowControlInstalled[] = {
+  MEM_FLOW_CFG* CONST memFlowControlInstalled[] = {
     NULL
   };
   /*---------------------------------------------------------------------------------------------------
@@ -1530,7 +1530,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *---------------------------------------------------------------------------------------------------
    */
-  OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = {    // Training flow control
+  OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = {    // Training flow control
     NULL,
     NULL,
   };
@@ -1540,7 +1540,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *---------------------------------------------------------------------------------------------------
    */
-  MEM_TECH_CONSTRUCTOR* memTechInstalled[] = {    // Types of technology installed
+  MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = {    // Types of technology installed
     NULL
   };
 
@@ -1550,13 +1550,13 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *---------------------------------------------------------------------------------------------------
    */
-  UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
+  CONST UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0};
 
   /*---------------------------------------------------------------------------------------------------
    * DEFAULT MAIN FEATURE BLOCK
    *---------------------------------------------------------------------------------------------------
    */
-  MEM_FEAT_BLOCK_MAIN MemFeatMain = {
+  CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = {
     0
   };
 
@@ -1581,18 +1581,18 @@ BOOLEAN MemFS3DefConstructorRet (
    *---------------------------------------------------------------------------------------------------
    */
   #if OPTION_DDR2
-    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR2 = {
+    CONST MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR2 = {
       0
     };
-    MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
+    CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
       { 0 }
     };
   #endif
   #if OPTION_DDR3
-    MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
+    CONST MEM_TECH_FEAT_BLOCK  memTechTrainingFeatDDR3 = {
       0
     };
-    MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
+    CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
       { 0 }
     };
   #endif
@@ -1607,7 +1607,7 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *----------------------------------------------------------------------
    */
-  MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = {
+  MEM_PLATFORM_CFG* CONST memPlatformTypeInstalled[] = {
     NULL
   };
 
@@ -1616,11 +1616,11 @@ BOOLEAN MemFS3DefConstructorRet (
    *
    *----------------------------------------------------------------------
    */
-  MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = {
+  MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = {
     NULL
   };
 
-  MEM_TECH_LRDIMM memLrdimmSupported = {
+  CONST MEM_TECH_LRDIMM memLrdimmSupported = {
     MEM_TECH_LRDIMM_STRUCT_VERSION,
     NULL
   };
@@ -1632,13 +1632,13 @@ BOOLEAN MemFS3DefConstructorRet (
  *
  *---------------------------------------------------------------------------------------------------
  */
-MEM_NB_SUPPORT memNBInstalled[] = {
+CONST MEM_NB_SUPPORT memNBInstalled[] = {
   MEM_NB_SUPPORT_TN
   MEM_NB_SUPPORT_KB
   MEM_NB_SUPPORT_END
 };
 
-UINT8 SizeOfNBInstalledTable = sizeof (memNBInstalled) / sizeof (memNBInstalled[0]);
+CONST UINT8 SizeOfNBInstalledTable = sizeof (memNBInstalled) / sizeof (memNBInstalled[0]);
 
 
 #endif  // _OPTION_MEMORY_INSTALL_H_
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionMultiSocketInstall.h
index cc79ceb883..0a4dbdfa99 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/OptionMultiSocketInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionMultiSocketInstall.h
@@ -89,7 +89,7 @@
 #endif
 
 /*  Declare the instance of the multisocket option configuration structure  */
-OPTION_MULTISOCKET_CONFIGURATION  OptionMultiSocketConfiguration = {
+CONST OPTION_MULTISOCKET_CONFIGURATION  OptionMultiSocketConfiguration = {
   MULTISOCKET_STRUCT_VERSION,
   GET_NUM_PM_STEPS,
   CORE0_PM_TASK,
diff --git a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h
index 8896b03dc0..7db98f2926 100644
--- a/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f16kb/Config/PlatformInstall.h
@@ -48,7 +48,7 @@
  *
  ****************************************************************************/
 
-VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
+CONST  AMD_MODULE_HEADER mCpuModuleID = {
   //ModuleHeaderSignature
   // Remove 'DOM$' as temp solution before update BinUtil.exe ,
   Int32FromChar ('0', '0', '0', '0'),
@@ -1706,7 +1706,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
  *
  ****************************************************************************/
 
-FCH_PLATFORM_POLICY  FchUserOptions = {
+CONST FCH_PLATFORM_POLICY  FchUserOptions = {
   CFG_SMBUS0_BASE_ADDRESS,              // CfgSmbus0BaseAddress
   CFG_SMBUS1_BASE_ADDRESS,              // CfgSmbus1BaseAddress
   CFG_SIO_PME_BASE_ADDRESS,             // CfgSioPmeBaseAddress
@@ -1754,7 +1754,7 @@ FCH_PLATFORM_POLICY  FchUserOptions = {
   CFG_FCH_RTC_WORKAROUND                // CfgFchRtcWorkaround
 };
 
-BUILD_OPT_CFG UserOptions = {
+CONST BUILD_OPT_CFG UserOptions = {
   {                                             // AGESA version string
     AGESA_CODE_SIGNATURE,                       //    code header Signature
     AGESA_PACKAGE_STRING,                       //    16 character ID
@@ -2130,4 +2130,3 @@ CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
 #if (OPTION_CPU_SCS == TRUE) || (CFG_GNB_BAPM_SUPPORT == TRUE)
   CONST INT32 _fltused = 0;
 #endif
-