src: use ARRAY_SIZE where possible

Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci

Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

19 files changed, 66 insertions, 62 deletions

diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
index 16487bf918..feadd8ba7d 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnPowerPlane.c
@@ -150,7 +150,7 @@ F15TnPmPwrPlaneInit (
     // Next, round it to the appropriate encoded value.  We will start from encoding 111b which corresponds
     // to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable
     // VRM can be.
-    for (VSRampSlamTime = ((sizeof (F15TnVSRampSlamWaitTimes) / sizeof (F15TnVSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) {
+    for (VSRampSlamTime = (ARRAY_SIZE(F15TnVSRampSlamWaitTimes)- 1); VSRampSlamTime > 0; VSRampSlamTime--) {
       if (WaitTime <= F15TnVSRampSlamWaitTimes[VSRampSlamTime]) {
         break;
       }
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
index 2f8a90539d..b6a10a48c9 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
@@ -97,7 +97,7 @@ AMD_WHEA_INIT_DATA F15WheaInitData = {
   0x00,                     // AmdMcbClrStatusOnInit
   0x02,                     // AmdMcbStatusDataFormat
   0x00,                     // AmdMcbConfWriteEn
-  (sizeof (F15HestBankInitData) / sizeof (F15HestBankInitData[0])), // HestBankNum
+  ARRAY_SIZE(F15HestBankInitData), // HestBankNum
   &F15HestBankInitData[0]   // Pointer to Initial data of HEST Bank
 };
 
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c
index 1cfddbea63..98d8d2908a 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2HwAcpiEnvService.c
@@ -211,7 +211,8 @@ ProgramFchEnvHwAcpiPciReg (
   //
   //Early post initialization of pci config space
   //
-  ProgramPciByteTable ((REG8_MASK*) (&FchHudson2InitEnvHwAcpiPciTable[0]), sizeof (FchHudson2InitEnvHwAcpiPciTable) / sizeof (REG8_MASK), StdHeader);
+  ProgramPciByteTable ((REG8_MASK*) (&FchHudson2InitEnvHwAcpiPciTable[0]),
+                       ARRAY_SIZE(FchHudson2InitEnvHwAcpiPciTable), StdHeader);
 
   if ( LocalCfgPtr->Smbus.SmbusSsid != 0 ) {
     RwPci ((SMBUS_BUS_DEV_FUN << 16) + FCH_CFG_REG2C, AccessWidth32, 0x00, LocalCfgPtr->Smbus.SmbusSsid, StdHeader);
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c
index ebb53bec88..fefc651130 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/HwAcpiLate.c
@@ -90,7 +90,7 @@ STATIC PCI_IRQ_REG_BLOCK FchInternalDeviceIrqForApicMode[] = {
     { (FCH_IRQ_GPPINT3 | FCH_IRQ_IOAPIC), 0x13},
   };
 
-#define NUM_OF_DEVICE_FOR_APICIRQ  sizeof (FchInternalDeviceIrqForApicMode) / sizeof (PCI_IRQ_REG_BLOCK)
+#define NUM_OF_DEVICE_FOR_APICIRQ  ARRAY_SIZE(FchInternalDeviceIrqForApicMode)
 
 /**
  * FchInitLateHwAcpi - Prepare HwAcpi controller to boot to OS.
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c
index 28ab4261d0..fa185d1568 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibEnv.c
@@ -88,7 +88,8 @@ FchInitEnvPcib (
   //
   //Early post initialization of pci config space
   //
-  ProgramPciByteTable ((REG8_MASK*) (&FchInitEnvPcibPciTable[0]), sizeof (FchInitEnvPcibPciTable) / sizeof (REG8_MASK), StdHeader);
+  ProgramPciByteTable ((REG8_MASK*) (&FchInitEnvPcibPciTable[0]),
+                       ARRAY_SIZE(FchInitEnvPcibPciTable), StdHeader);
 
   //
   //Disable or Enable PCI Clks based on input
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c
index 173a278b9e..bdb214df42 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c
@@ -82,7 +82,7 @@ FchInitResetPcib (
 
   ProgramPciByteTable (
     (REG8_MASK*) (&FchInitResetPcibPciTable[0]),
-    sizeof (FchInitResetPcibPciTable) / sizeof (REG8_MASK),
+    ARRAY_SIZE(FchInitResetPcibPciTable),
     StdHeader
     );
   if ( UserOptions.FchBldCfg->CfgFchPort80BehindPcib ) {
@@ -129,7 +129,7 @@ FchInitResetPcibPort80Enable (
 
   ProgramPciByteTable (
     (REG8_MASK*) (&FchInitResetPcibPort80EnableTable[0]),
-    sizeof (FchInitResetPcibPort80EnableTable) / sizeof (REG8_MASK),
+    ARRAY_SIZE(FchInitResetPcibPort80EnableTable),
     StdHeader
     );
 }
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
index 26ff51ddfc..5cec9bede4 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Sata/Family/Hudson2/Hudson2SataEnvService.c
@@ -211,7 +211,7 @@ FchProgramSataPhy (
 
   PhyTablePtr = &SataPhyTable[0];
 
-  for (Index = 0; Index < (sizeof (SataPhyTable) / sizeof (SATA_PHY_SETTING)); Index++) {
+  for (Index = 0; Index < ARRAY_SIZE(SataPhyTable); Index++) {
     RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, PhyTablePtr->PhyCoreControlWord, StdHeader);
     RwPci ((SATA_BUS_DEV_FUN << 16) + 0x98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader);
     ++PhyTablePtr;
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c
index b1ae0c81f9..b6806317f2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcEnvService.c
@@ -82,7 +82,8 @@ FchInitEnvLpcProgram (
   LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr;
   StdHeader = LocalCfgPtr->StdHeader;
 
-  ProgramPciByteTable ((REG8_MASK*) (&FchInitHudson2EnvLpcPciTable[0]), sizeof (FchInitHudson2EnvLpcPciTable) / sizeof (REG8_MASK), StdHeader);
+  ProgramPciByteTable ((REG8_MASK*) (&FchInitHudson2EnvLpcPciTable[0]),
+                       ARRAY_SIZE(FchInitHudson2EnvLpcPciTable), StdHeader);
 
   //
   // Disable LPC A-Link Cycle Bypass
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
index 36259d3cbc..107e181394 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c
@@ -99,7 +99,8 @@ FchInitResetLpcProgram (
   //
   RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader);
 
-  ProgramPciByteTable ( (REG8_MASK*) (&FchInitHudson2ResetLpcPciTable[0]), sizeof (FchInitHudson2ResetLpcPciTable) / sizeof (REG8_MASK), StdHeader);
+  ProgramPciByteTable ( (REG8_MASK*) (&FchInitHudson2ResetLpcPciTable[0]),
+                       ARRAY_SIZE(FchInitHudson2ResetLpcPciTable), StdHeader);
 
   //
   // Enabling ClkRun Function
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
index 2d42063340..66bdad5494 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
@@ -253,7 +253,7 @@ GfxIntegratedExtConnectorInfo (
   )
 {
   UINTN Index;
-  for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) {
+  for (Index = 0; Index < ARRAY_SIZE(ConnectorInfoTable); Index++) {
     if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) {
       return &ConnectorInfoTable[Index];
     }
@@ -331,7 +331,7 @@ GfxIntegratedExtDisplayDeviceInfo (
   UINT8 Index;
   UINT8 LastIndex;
   LastIndex = 0xff;
-  for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) {
+  for (Index = 0; Index < ARRAY_SIZE(DisplayDeviceInfoTable); Index++) {
     if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) {
       LastIndex = Index;
       if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) {
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
index 1bbb397596..422cbae007 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c
@@ -759,9 +759,9 @@ GfxPowerPlayBuildVceStateTable (
   UINT8                       UsedStateBitmap;
   UsedStateBitmap = 0;
   // build used state
-  for (Index = 0; Index < (sizeof (PpWorkspace->PpFuses->VceFlags) / sizeof (PpWorkspace->PpFuses->VceFlags[0])) ; Index++) {
+  for (Index = 0; Index < ARRAY_SIZE(PpWorkspace->PpFuses->VceFlags); Index++) {
     UsedStateBitmap |= PpWorkspace->PpFuses->VceFlags[Index];
-    for (VceStateIndex = 0; VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); VceStateIndex++) {
+    for (VceStateIndex = 0; VceStateIndex < ARRAY_SIZE(PpWorkspace->VceStateArray); VceStateIndex++) {
       if ((PpWorkspace->PpFuses->VceFlags[Index] & (1 << VceStateIndex)) != 0) {
         Sclk = GfxFmCalculateClock (PpWorkspace->PpFuses->SclkDpmDid[PpWorkspace->PpFuses->VceReqSclkSel[Index]], GnbLibGetHeader (PpWorkspace->Gfx));
         Vid = PpWorkspace->PpFuses->SclkDpmVid[PpWorkspace->PpFuses->VceReqSclkSel[Index]];
@@ -777,7 +777,7 @@ GfxPowerPlayBuildVceStateTable (
     }
   }
   //build unused states
-  for (VceStateIndex = 0; VceStateIndex < (sizeof (PpWorkspace->VceStateArray) / sizeof (PpWorkspace->VceStateArray[0])); VceStateIndex++) {
+  for (VceStateIndex = 0; VceStateIndex < ARRAY_SIZE(PpWorkspace->VceStateArray); VceStateIndex++) {
     if ((UsedStateBitmap & (1 << VceStateIndex)) == 0) {
       PpWorkspace->VceStateArray[VceStateIndex].ucClockInfoIndex = 0;
       PpWorkspace->VceStateArray[VceStateIndex].ucVCEClockInfoIndex = GfxPowerPlayAddEclkState (PpWorkspace, 0);
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
index 75ec2fb387..89d317ea6e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c
@@ -260,7 +260,7 @@ GfxGmcDctMemoryChannelInfoTN (
   UINT32       Index;
   UINT32       Value;
 
-  for (Index = 0; Index < (sizeof (DctRegisterTable) / sizeof (DCT_REGISTER_ENTRY)); Index++) {
+  for (Index = 0; Index < ARRAY_SIZE(DctRegisterTable); Index++) {
     GnbRegisterReadTN (
       DctRegisterTable[Index].RegisterSpaceType,
       DctRegisterTable[Index].Address,
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
index c700a64541..8b388d583e 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbEarlyInitTN.c
@@ -417,7 +417,7 @@ GnbCacEnablement (
 
   // Program GPU CAC weights
 
-  for (Index = 0; Index < (sizeof (CacWeightsTN) / sizeof (CacWeightsTN[0])); Index++) {
+  for (Index = 0; Index < ARRAY_SIZE(CacWeightsTN); Index++) {
     GnbRegisterWriteTN (TYPE_D0F0xBC , (0x1f9a0  + (Index * 4)), &CacWeightsTN[Index], 0, StdHeader);
   }
 
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
index 9737bd2930..8c580a07b7 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbFuseTableTN.c
@@ -615,175 +615,175 @@ FUSE_TABLE_ENTRY_TN  FuseRegisterTableTN [] = {
   {
     D0F0xBC_xE0104158_TYPE,
     D0F0xBC_xE0104158_ADDRESS,
-    sizeof (D0F0xBC_xE0104158_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0104158_TABLE),
     D0F0xBC_xE0104158_TABLE
   },
   {
     D0F0xBC_xE010415B_TYPE,
     D0F0xBC_xE010415B_ADDRESS,
-    sizeof (D0F0xBC_xE010415B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE010415B_TABLE),
     D0F0xBC_xE010415B_TABLE
   },
   {
     D0F0xBC_xE0104184_TYPE,
     D0F0xBC_xE0104184_ADDRESS,
-    sizeof (D0F0xBC_xE0104184_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0104184_TABLE),
     D0F0xBC_xE0104184_TABLE
   },
   {
     D0F0xBC_xE0104187_TYPE,
     D0F0xBC_xE0104187_ADDRESS,
-    sizeof (D0F0xBC_xE0104187_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0104187_TABLE),
     D0F0xBC_xE0104187_TABLE
   },
   {
     D0F0xBC_xE0104188_TYPE,
     D0F0xBC_xE0104188_ADDRESS,
-    sizeof (D0F0xBC_xE0104188_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0104188_TABLE),
     D0F0xBC_xE0104188_TABLE
   },
   {
     D0F0xBC_xE0106020_TYPE,
     D0F0xBC_xE0106020_ADDRESS,
-    sizeof (D0F0xBC_xE0106020_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0106020_TABLE),
     D0F0xBC_xE0106020_TABLE
   },
   {
     D0F0xBC_xE0106023_TYPE,
     D0F0xBC_xE0106023_ADDRESS,
-    sizeof (D0F0xBC_xE0106023_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0106023_TABLE),
     D0F0xBC_xE0106023_TABLE
   },
   {
     D0F0xBC_xE0106024_TYPE,
     D0F0xBC_xE0106024_ADDRESS,
-    sizeof (D0F0xBC_xE0106024_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0106024_TABLE),
     D0F0xBC_xE0106024_TABLE
   },
   {
     D0F0xBC_xE010705C_TYPE,
     D0F0xBC_xE010705C_ADDRESS,
-    sizeof (D0F0xBC_xE010705C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE010705C_TABLE),
     D0F0xBC_xE010705C_TABLE
   },
   {
     D0F0xBC_xE010705F_TYPE,
     D0F0xBC_xE010705F_ADDRESS,
-    sizeof (D0F0xBC_xE010705F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE010705F_TABLE),
     D0F0xBC_xE010705F_TABLE
   },
   {
     D0F0xBC_xE0107060_TYPE,
     D0F0xBC_xE0107060_ADDRESS,
-    sizeof (D0F0xBC_xE0107060_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0107060_TABLE),
     D0F0xBC_xE0107060_TABLE
   },
   {
     D0F0xBC_xE0107063_TYPE,
     D0F0xBC_xE0107063_ADDRESS,
-    sizeof (D0F0xBC_xE0107063_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0107063_TABLE),
     D0F0xBC_xE0107063_TABLE
   },
   {
     D0F0xBC_xE0107064_TYPE,
     D0F0xBC_xE0107064_ADDRESS,
-    sizeof (D0F0xBC_xE0107064_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0107064_TABLE),
     D0F0xBC_xE0107064_TABLE
   },
   {
     D0F0xBC_xE0107067_TYPE,
     D0F0xBC_xE0107067_ADDRESS,
-    sizeof (D0F0xBC_xE0107067_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0107067_TABLE),
     D0F0xBC_xE0107067_TABLE
   },
   {
     D0F0xBC_xE0107068_TYPE,
     D0F0xBC_xE0107068_ADDRESS,
-    sizeof (D0F0xBC_xE0107068_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0107068_TABLE),
     D0F0xBC_xE0107068_TABLE
   },
   {
     D0F0xBC_xE010706B_TYPE,
     D0F0xBC_xE010706B_ADDRESS,
-    sizeof (D0F0xBC_xE010706B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE010706B_TABLE),
     D0F0xBC_xE010706B_TABLE
   },
   {
     D0F0xBC_xE010706C_TYPE,
     D0F0xBC_xE010706C_ADDRESS,
-    sizeof (D0F0xBC_xE010706C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE010706C_TABLE),
     D0F0xBC_xE010706C_TABLE
   },
   {
     D0F0xBC_xE010706F_TYPE,
     D0F0xBC_xE010706F_ADDRESS,
-    sizeof (D0F0xBC_xE010706F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE010706F_TABLE),
     D0F0xBC_xE010706F_TABLE
   },
   {
     D0F0xBC_xE0107070_TYPE,
     D0F0xBC_xE0107070_ADDRESS,
-    sizeof (D0F0xBC_xE0107070_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0107070_TABLE),
     D0F0xBC_xE0107070_TABLE
   },
   {
     D0F0xBC_xE0107073_TYPE,
     D0F0xBC_xE0107073_ADDRESS,
-    sizeof (D0F0xBC_xE0107073_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0107073_TABLE),
     D0F0xBC_xE0107073_TABLE
   },
   {
     D0F0xBC_xE0107074_TYPE,
     D0F0xBC_xE0107074_ADDRESS,
-    sizeof (D0F0xBC_xE0107074_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0107074_TABLE),
     D0F0xBC_xE0107074_TABLE
   },
   {
     D0F0xBC_xE0107077_TYPE,
     D0F0xBC_xE0107077_ADDRESS,
-    sizeof (D0F0xBC_xE0107077_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0107077_TABLE),
     D0F0xBC_xE0107077_TABLE
   },
   {
     D0F0xBC_xE0107078_TYPE,
     D0F0xBC_xE0107078_ADDRESS,
-    sizeof (D0F0xBC_xE0107078_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0107078_TABLE),
     D0F0xBC_xE0107078_TABLE
   },
   {
     D0F0xBC_xE010707B_TYPE,
     D0F0xBC_xE010707B_ADDRESS,
-    sizeof (D0F0xBC_xE010707B_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE010707B_TABLE),
     D0F0xBC_xE010707B_TABLE
   },
   {
     D0F0xBC_xE010707C_TYPE,
     D0F0xBC_xE010707C_ADDRESS,
-    sizeof (D0F0xBC_xE010707C_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE010707C_TABLE),
     D0F0xBC_xE010707C_TABLE
   },
   {
     D0F0xBC_xE010707F_TYPE,
     D0F0xBC_xE010707F_ADDRESS,
-    sizeof (D0F0xBC_xE010707F_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE010707F_TABLE),
     D0F0xBC_xE010707F_TABLE
   },
   {
     D0F0xBC_xFF000000_TYPE,
     D0F0xBC_xFF000000_ADDRESS,
-    sizeof (D0F0xBC_xFF000000_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xFF000000_TABLE),
     D0F0xBC_xFF000000_TABLE
   },
   {
     D0F0xBC_xE0001008_TYPE,
     D0F0xBC_xE0001008_ADDRESS,
-    sizeof (D0F0xBC_xE0001008_TABLE) / sizeof (FUSE_REGISTER_ENTRY_TN),
+    ARRAY_SIZE(D0F0xBC_xE0001008_TABLE),
     D0F0xBC_xE0001008_TABLE
   }
 };
 
 FUSE_TABLE_TN  FuseTableTN = {
-  sizeof (FuseRegisterTableTN) / sizeof (FUSE_TABLE_ENTRY_TN),
+  ARRAY_SIZE(FuseRegisterTableTN),
   FuseRegisterTableTN
 };
 
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
index b1ac093ab1..a58e918a22 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c
@@ -110,8 +110,8 @@ STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = {
 
 CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN  = {
   &PcieInitEarlyTable[0],
-  sizeof (PcieInitEarlyTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)
-};
+  ARRAY_SIZE(PcieInitEarlyTable)
+  };
 
 STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = {
   {
@@ -160,8 +160,8 @@ STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = {
 
 CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN  = {
   &CoreInitTable[0],
-  sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)
-};
+  ARRAY_SIZE(CoreInitTable)
+  };
 
 
 STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = {
@@ -208,8 +208,8 @@ STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = {
 
 CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitEarlyTableTN  = {
   &PortInitEarlyTable[0],
-  sizeof (PortInitEarlyTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)
-};
+  ARRAY_SIZE(PortInitEarlyTable)
+  };
 
 
 STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = {
@@ -227,5 +227,5 @@ STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitMidTable [] = {
 
 CONST PCIE_PORT_REGISTER_TABLE_HEADER ROMDATA PortInitMidTableTN  = {
   &PortInitMidTable[0],
-  sizeof (PortInitMidTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)
-};
+  ARRAY_SIZE(PortInitMidTable)
+  };
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
index a2aa396035..a0a9bb6aab 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c
@@ -123,7 +123,7 @@ PcieAspmBlackListFeature (
 
   GnbLibPciRead (LinkAsmp->UpstreamPort.AddressValue, AccessWidth32, &UpstreamDeviceId, StdHeader);
   GnbLibPciRead (LinkAsmp->DownstreamPort.AddressValue, AccessWidth32, &DownstreamDeviceId, StdHeader);
-  for (i = 0; i < (sizeof (AspmBrDeviceTable) / sizeof (UINT16)); i = i + 3) {
+  for (i = 0; i < ARRAY_SIZE(AspmBrDeviceTable); i = i + 3) {
     VendorId = AspmBrDeviceTable[i];
     DeviceId = AspmBrDeviceTable[i + 1];
     if (VendorId == (UINT16)UpstreamDeviceId || VendorId == (UINT16)DownstreamDeviceId ) {
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c
index 045315fda4..2bd702a9b3 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV4/PcieMaxPayloadV4.c
@@ -282,7 +282,7 @@ PciePayloadBlackListFeature (
   UINT32  VendorId;
 
   GnbLibPciRead (Device.AddressValue, AccessWidth32, &TargetDeviceId, StdHeader);
-  for (i = 0; i < (sizeof (PayloadBlacklistDeviceTable) / sizeof (UINT16)); i = i + 3) {
+  for (i = 0; i < ARRAY_SIZE(PayloadBlacklistDeviceTable); i = i + 3) {
     VendorId = PayloadBlacklistDeviceTable[i];
     DeviceId = PayloadBlacklistDeviceTable[i + 1];
     if (VendorId == (UINT16)TargetDeviceId) {
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c
index c11e90e30e..c14ab4a8cc 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c
@@ -228,7 +228,7 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorTN[] = {
 
 CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefTN = {
   0,
-  (sizeof (S3PciPreSelfRefDescriptorTN) / sizeof (PCI_REG_DESCRIPTOR)),
+  ARRAY_SIZE(S3PciPreSelfRefDescriptorTN),
   S3PciPreSelfRefDescriptorTN,
   PciSpecialCaseFuncTN
 };
@@ -510,7 +510,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorTN[] = {
 
 CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefTN = {
   0,
-  (sizeof (S3CPciPreSelfDescriptorTN) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  ARRAY_SIZE(S3CPciPreSelfDescriptorTN),
   S3CPciPreSelfDescriptorTN,
   PciSpecialCaseFuncTN
 };
@@ -797,7 +797,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorTN[] = {
 
 CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefTN = {
   0,
-  (sizeof (S3CPciPostSelfDescriptorTN) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  ARRAY_SIZE(S3CPciPostSelfDescriptorTN),
   S3CPciPostSelfDescriptorTN,
   PciSpecialCaseFuncTN
 };
@@ -811,7 +811,7 @@ MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorTN[] = {
 
 CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefTN = {
   0,
-  (sizeof (S3MSRPreSelfRefDescriptorTN) / sizeof (MSR_REG_DESCRIPTOR)),
+  ARRAY_SIZE(S3MSRPreSelfRefDescriptorTN),
   S3MSRPreSelfRefDescriptorTN,
   NULL
 };
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c
index 335934bf5c..dcf62022ab 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mt3.c
@@ -207,12 +207,12 @@ MemConstructTechBlock3 (
       //
       // Initialize the SPD pointers for each Dimm
       //
-      for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) {
+      for (i = 0 ; i < ARRAY_SIZE(ChannelPtr->DimmSpdPtr); i++) {
         ChannelPtr->DimmSpdPtr[i] = NULL;
       }
       for (i = 0 ; i < DimmSlots; i++) {
         ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]);
-        if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) {
+        if ( (i + 2) < ARRAY_SIZE(ChannelPtr->DimmSpdPtr)) {
           if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) {
             if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) {
               ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]);