diff options
| author | Kostr <aladyshev@nicevt.ru> | 2012-10-08 22:04:53 +0400 |
|---|---|---|
| committer | Marc Jones <marcj303@gmail.com> | 2012-10-30 05:49:13 +0100 |
| commit | 335450d0a1f7befe4ca649d7e23dcf8ed15bf314 (patch) | |
| tree | 02c4d49e1ff31c9f2e089ed96144bc224b14b25c /src/vendorcode/amd/agesa/f15/gcccar.inc | |
| parent | 80adfdf8a9dde4b81fc0d0ffacf04835c4eaa883 (diff) | |
Fix ExecuteFinalHltInstruction function in f15h family code
Current ExecuteFinalHltInstruction function doesn't work well.
(at least in configuration
Supermicro board with Orochi AMD Opteron processors (model OS6234WKTCGGU))
System reboots when trying to halt core 2,4,6,8 or 10
(OS6234WKTCGGU is 12 core processor)
Based on this information, i think that code doesn't really work with
f15 compute unit (CU) system.
Replacing ExecuteFinalHltInstruction function with
analogous function from f15tn family code fix this problem.
Both functions written from the same cahalt.asm file, but f15tn version
seems more completed
Change-Id: I3942abcdf21f1b86a44c01cc477714e44a40b9cf
Signed-off-by: Kostr <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/1569
Tested-by: build bot (Jenkins)
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f15/gcccar.inc')
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/gcccar.inc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc index 07e32850e8..423d404469 100644 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15/gcccar.inc @@ -49,6 +49,7 @@ APIC_BASE_ADDRESS = 0x0000001B AMD_MTRR_VARIABLE_BASE0 = 0x0200 AMD_MTRR_VARIABLE_BASE6 = 0x020C +AMD_MTRR_VARIABLE_MASK7 = 0x020F AMD_MTRR_FIX64k_00000 = 0x0250 AMD_MTRR_FIX16k_80000 = 0x0258 AMD_MTRR_FIX16k_A0000 = 0x0259 @@ -61,6 +62,20 @@ AMD_MTRR_FIX4k_E8000 = 0x026D AMD_MTRR_FIX4k_F0000 = 0x026E AMD_MTRR_FIX4k_F8000 = 0x026F +/* Reproduced from AGESA.h */ +AMD_AP_MTRR_FIX64k_00000 = 0x00000250 +AMD_AP_MTRR_FIX16k_80000 = 0x00000258 +AMD_AP_MTRR_FIX16k_A0000 = 0x00000259 +AMD_AP_MTRR_FIX4k_C0000 = 0x00000268 +AMD_AP_MTRR_FIX4k_C8000 = 0x00000269 +AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A +AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B +AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C +AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D +AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E +AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F +CPU_LIST_TERMINAL = 0xFFFFFFFF + AMD_MTRR_DEFTYPE = 0x02FF WB_DRAM_TYPE = 0x1E /* MemType - memory type */ MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */ |