diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-04-19 07:17:35 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-04-20 15:33:25 +0200 |
| commit | ae2963587603c205dfada1a7cf5b5859390ac27e (patch) | |
| tree | 986bd39d3702ea5afc5646a6f0465d8711ccb509 /src/vendorcode/amd/agesa/f15/Proc | |
| parent | 4dcbdb0ab998b18ae209b561ffab33bac96ce4b5 (diff) | |
AGESA vendorcode: Suppress maybe-uninitialized warnings
Compiling libagesa with -O2 would throws error on these.
Change-Id: I04afa42f0ac76677f859ca72f9df2e128762ad3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14413
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/agesa/f15/Proc')
| -rw-r--r-- | src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c index d61c0657f7..83f7aac320 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c +++ b/src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtspd3.c @@ -154,7 +154,7 @@ MemTDIMMPresence3 ( UINT8 Channel; UINT8 i; MEM_PARAMETER_STRUCT *RefPtr; - UINT8 *SpdBufferPtr; + UINT8 *SpdBufferPtr = NULL; DIE_STRUCT *MCTPtr; DCT_STRUCT *DCTPtr; CH_DEF_STRUCT *ChannelPtr; @@ -461,7 +461,7 @@ MemTSPDGetTargetSpeed3 ( IN OUT MEM_TECH_BLOCK *TechPtr ) { - UINT8 *SpdBufferPtr; + UINT8 *SpdBufferPtr = NULL; UINT8 Dimm; UINT8 Dct; UINT8 Channel; @@ -541,8 +541,8 @@ MemTSPDCalcWidth3 ( IN OUT MEM_TECH_BLOCK *TechPtr ) { - UINT8 *SpdBufferAPtr; - UINT8 *SpdBufferBPtr; + UINT8 *SpdBufferAPtr = NULL; + UINT8 *SpdBufferBPtr = NULL; MEM_NB_BLOCK *NBPtr; DIE_STRUCT *MCTPtr; DCT_STRUCT *DCTPtr; @@ -662,7 +662,7 @@ MemTAutoCycTiming3 ( 0 }; - UINT8 *SpdBufferPtr; + UINT8 *SpdBufferPtr = NULL; INT32 MiniMaxTmg[GET_SIZE_OF (SpdIndexes)]; UINT8 MiniMaxTrfc[4]; @@ -788,7 +788,7 @@ MemTSPDSetBanks3 ( IN OUT MEM_TECH_BLOCK *TechPtr ) { - UINT8 *SpdBufferPtr; + UINT8 *SpdBufferPtr = NULL; UINT8 i; UINT8 ChipSel; UINT8 DimmID; @@ -1009,7 +1009,7 @@ MemTSPDGetTCL3 ( IN OUT MEM_TECH_BLOCK *TechPtr ) { - UINT8 *SpdBufferPtr; + UINT8 *SpdBufferPtr = NULL; UINT8 CLdesired; UINT8 CLactual; UINT8 Dimm; |