src: use ARRAY_SIZE where possible

Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci

Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

11 files changed, 47 insertions, 47 deletions

diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c
index 263061d164..1c1a3a7971 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Dmi.c
@@ -315,7 +315,7 @@ CONST PROC_FAMILY_TABLE ROMDATA ProcFamily14DmiTable =
   &DmiF14GetMaxSpeed,
   &DmiF14GetExtClock,
   &DmiF14GetMemInfo,              // Get memory information
-  (sizeof (Family14BrandList) / sizeof (Family14BrandList[0])), // Number of entries in following table
+  ARRAY_SIZE(Family14BrandList), // Number of entries in following table
   &Family14BrandList[0]
 };
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
index 4adb54f265..1694a93cd9 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14PowerPlane.c
@@ -154,7 +154,7 @@ F14PmPwrPlaneInit (
   // Next, round it to the appropriate encoded value.  We will start from encoding 111b which corresponds
   // to the fastest slew rate, and work our way down to 000b, which represents the slowest an acceptable
   // VRM can be.
-  for (VSRampSlamTime = ((sizeof (F14VSRampSlamWaitTimes) / sizeof (F14VSRampSlamWaitTimes[0])) - 1); VSRampSlamTime > 0; VSRampSlamTime--) {
+  for (VSRampSlamTime = (ARRAY_SIZE(F14VSRampSlamWaitTimes)- 1); VSRampSlamTime > 0; VSRampSlamTime--) {
     if (WaitTime <= F14VSRampSlamWaitTimes[VSRampSlamTime]) {
       break;
     }
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
index dd4c69a48e..5531f47ba2 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c
@@ -95,7 +95,7 @@ AMD_WHEA_INIT_DATA F14WheaInitData = {
   0x00,                     // AmdMcbClrStatusOnInit
   0x02,                     // AmdMcbStatusDataFormat
   0x00,                     // AmdMcbConfWriteEn
-  (sizeof (F14HestBankInitData) / sizeof (F14HestBankInitData[0])), // HestBankNum
+  ARRAY_SIZE(F14HestBankInitData), // HestBankNum
   &F14HestBankInitData[0]   // Pointer to Initial data of HEST Bank
 };
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c
index a974108f6d..ee83ae738c 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c
@@ -363,7 +363,7 @@ GMM_REG_ENTRY  GmcDisableClockGating[] = {
 };
 
 TABLE_INDIRECT_PTR GmcDisableClockGatingPtr = {
-  sizeof (GmcDisableClockGating) / sizeof (GMM_REG_ENTRY),
+  ARRAY_SIZE(GmcDisableClockGating),
   GmcDisableClockGating
 };
 
@@ -383,7 +383,7 @@ GMM_REG_ENTRY  GmcEnableClockGating[] = {
 
 
 TABLE_INDIRECT_PTR GmcEnableClockGatingPtr = {
-  sizeof (GmcEnableClockGating) / sizeof (GMM_REG_ENTRY),
+  ARRAY_SIZE(GmcEnableClockGating),
   GmcEnableClockGating
 };
 
@@ -414,7 +414,7 @@ GMM_REG_ENTRY  GmcPerformanceTuningTable [] = {
 };
 
 TABLE_INDIRECT_PTR GmcPerformanceTuningTablePtr = {
-  sizeof (GmcPerformanceTuningTable) / sizeof (GMM_REG_ENTRY),
+  ARRAY_SIZE(GmcPerformanceTuningTable),
   GmcPerformanceTuningTable
 };
 
@@ -431,7 +431,7 @@ GMM_REG_ENTRY  GmcMiscInitTable [] = {
 };
 
 TABLE_INDIRECT_PTR GmcMiscInitTablePtr = {
-  sizeof (GmcMiscInitTable) / sizeof (GMM_REG_ENTRY),
+  ARRAY_SIZE(GmcMiscInitTable),
   GmcMiscInitTable
 };
 
@@ -446,7 +446,7 @@ GMM_REG_ENTRY  GmcRemoveBlackoutTable [] = {
 };
 
 TABLE_INDIRECT_PTR GmcRemoveBlackoutTablePtr = {
-  sizeof (GmcRemoveBlackoutTable) / sizeof (GMM_REG_ENTRY),
+  ARRAY_SIZE(GmcRemoveBlackoutTable),
   GmcRemoveBlackoutTable
 };
 
@@ -522,7 +522,7 @@ GMM_REG_ENTRY GmcRegisterEngineInitTable [] = {
 };
 
 TABLE_INDIRECT_PTR GmcRegisterEngineInitTablePtr = {
-  sizeof (GmcRegisterEngineInitTable) / sizeof (GMM_REG_ENTRY),
+  ARRAY_SIZE(GmcRegisterEngineInitTable),
   GmcRegisterEngineInitTable
 };
 
@@ -633,7 +633,7 @@ REGISTER_COPY_ENTRY CnbToGncRegisterCopyTable [] = {
 
 
 TABLE_INDIRECT_PTR CnbToGncRegisterCopyTablePtr = {
-  sizeof (CnbToGncRegisterCopyTable) / sizeof (REGISTER_COPY_ENTRY),
+  ARRAY_SIZE(CnbToGncRegisterCopyTable),
   CnbToGncRegisterCopyTable
 };
 
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
index 440c5ff68c..e2480ecde4 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c
@@ -239,7 +239,7 @@ GfxIntegratedExtConnectorInfo (
   )
 {
   UINTN Index;
-  for (Index = 0; Index < (sizeof (ConnectorInfoTable) / sizeof (EXT_CONNECTOR_INFO)); Index++) {
+  for (Index = 0; Index < ARRAY_SIZE(ConnectorInfoTable); Index++) {
     if (ConnectorInfoTable[Index].ConnectorType == ConnectorType) {
       return &ConnectorInfoTable[Index];
     }
@@ -317,7 +317,7 @@ GfxIntegratedExtDisplayDeviceInfo (
   UINT8 Index;
   UINT8 LastIndex;
   LastIndex = 0xff;
-  for (Index = 0; Index < (sizeof (DisplayDeviceInfoTable) / sizeof (EXT_DISPLAY_DEVICE_INFO)); Index++) {
+  for (Index = 0; Index < ARRAY_SIZE(DisplayDeviceInfoTable); Index++) {
     if (DisplayDeviceInfoTable[Index].DisplayDeviceEnum == DisplayDeviceEnum) {
       LastIndex = Index;
       if (DisplayDeviceInfoTable[Index].DeviceIndex == DisplayDeviceIndex) {
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
index 827bd7f3f3..d5c16ae866 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c
@@ -209,7 +209,7 @@ NbFmInitLclkDpmRcActivity (
       NbSmuRcuRegisterWrite (
         0x84AC,
         &LclkDpmCacTable[0],
-        sizeof (LclkDpmCacTable) / sizeof (UINT32),
+        ARRAY_SIZE(LclkDpmCacTable),
         TRUE,
         StdHeader
         );
@@ -225,7 +225,7 @@ NbFmInitLclkDpmRcActivity (
         StdHeader
         );
       // Program sampling period
-      for (Index = 0; Index < (sizeof (SamplingPeriod) / sizeof (SamplingPeriod[0])); Index = Index + 2) {
+      for (Index = 0; Index < ARRAY_SIZE(SamplingPeriod); Index = Index + 2) {
         UINT16 Temp;
         Temp = SamplingPeriod[Index];
         SamplingPeriod[Index] = SamplingPeriod[Index + 1];
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c
index d067875aba..dd5e6450ee 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbServices.c
@@ -687,132 +687,132 @@ FUSE_REGISTER_ENTRY FCRxFE00_70D7_TABLE [] = {
 FUSE_TABLE_ENTRY  FuseRegisterTable [] = {
   {
     FCRxFE00_70A2_ADDRESS,
-    sizeof (FCRxFE00_70A2_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70A2_TABLE),
     FCRxFE00_70A2_TABLE
   },
   {
     FCRxFE00_70A4_ADDRESS,
-    sizeof (FCRxFE00_70A4_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70A4_TABLE),
     FCRxFE00_70A4_TABLE
   },
   {
     FCRxFE00_70A5_ADDRESS,
-    sizeof (FCRxFE00_70A5_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70A5_TABLE),
     FCRxFE00_70A5_TABLE
   },
   {
     FCRxFE00_70A8_ADDRESS,
-    sizeof (FCRxFE00_70A8_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70A8_TABLE),
     FCRxFE00_70A8_TABLE
   },
   {
     FCRxFE00_600E_ADDRESS,
-    sizeof (FCRxFE00_600E_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_600E_TABLE),
     FCRxFE00_600E_TABLE
   },
   {
     FCRxFE00_70AA_ADDRESS,
-    sizeof (FCRxFE00_70AA_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70AA_TABLE),
     FCRxFE00_70AA_TABLE
   },
   {
     FCRxFE00_70AE_ADDRESS,
-    sizeof (FCRxFE00_70AE_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70AE_TABLE),
     FCRxFE00_70AE_TABLE
   },
   {
     FCRxFE00_70B1_ADDRESS,
-    sizeof (FCRxFE00_70B1_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70B1_TABLE),
     FCRxFE00_70B1_TABLE
   },
   {
     FCRxFE00_70B4_ADDRESS,
-    sizeof (FCRxFE00_70B4_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70B4_TABLE),
     FCRxFE00_70B4_TABLE
   },
   {
     FCRxFE00_70B5_ADDRESS,
-    sizeof (FCRxFE00_70B5_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70B5_TABLE),
     FCRxFE00_70B5_TABLE
   },
   {
     FCRxFE00_70B8_ADDRESS,
-    sizeof (FCRxFE00_70B8_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70B8_TABLE),
     FCRxFE00_70B8_TABLE
   },
   {
     FCRxFE00_70B9_ADDRESS,
-    sizeof (FCRxFE00_70B9_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70B9_TABLE),
     FCRxFE00_70B9_TABLE
   },
   {
     FCRxFE00_70BC_ADDRESS,
-    sizeof (FCRxFE00_70BC_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70BC_TABLE),
     FCRxFE00_70BC_TABLE
   },
   {
     FCRxFE00_70BF_ADDRESS,
-    sizeof (FCRxFE00_70BF_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70BF_TABLE),
     FCRxFE00_70BF_TABLE
   },
   {
     FCRxFE00_70C0_ADDRESS,
-    sizeof (FCRxFE00_70C0_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70C0_TABLE),
     FCRxFE00_70C0_TABLE
   },
   {
     FCRxFE00_70C1_ADDRESS,
-    sizeof (FCRxFE00_70C1_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70C1_TABLE),
     FCRxFE00_70C1_TABLE
   },
   {
     FCRxFE00_70C4_ADDRESS,
-    sizeof (FCRxFE00_70C4_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70C4_TABLE),
     FCRxFE00_70C4_TABLE
   },
   {
     FCRxFE00_70C7_ADDRESS,
-    sizeof (FCRxFE00_70C7_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70C7_TABLE),
     FCRxFE00_70C7_TABLE
   },
   {
     FCRxFE00_70C8_ADDRESS,
-    sizeof (FCRxFE00_70C8_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70C8_TABLE),
     FCRxFE00_70C8_TABLE
   },
   {
     FCRxFE00_70C9_ADDRESS,
-    sizeof (FCRxFE00_70C9_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70C9_TABLE),
     FCRxFE00_70C9_TABLE
   },
   {
     FCRxFE00_70CC_ADDRESS,
-    sizeof (FCRxFE00_70CC_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70CC_TABLE),
     FCRxFE00_70CC_TABLE
   },
   {
     FCRxFE00_70CF_ADDRESS,
-    sizeof (FCRxFE00_70CF_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70CF_TABLE),
     FCRxFE00_70CF_TABLE
   },
   {
     FCRxFE00_70D2_ADDRESS,
-    sizeof (FCRxFE00_70D2_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70D2_TABLE),
     FCRxFE00_70D2_TABLE
   },
   {
     FCRxFE00_70D4_ADDRESS,
-    sizeof (FCRxFE00_70D4_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70D4_TABLE),
     FCRxFE00_70D4_TABLE
   },
   {
     FCRxFE00_70D7_ADDRESS,
-    sizeof (FCRxFE00_70D7_TABLE) / sizeof (FUSE_REGISTER_ENTRY),
+    ARRAY_SIZE(FCRxFE00_70D7_TABLE),
     FCRxFE00_70D7_TABLE
   },
 };
 
 FUSE_TABLE  FuseTable = {
-  sizeof (FuseRegisterTable) / sizeof (FUSE_TABLE_ENTRY),
+  ARRAY_SIZE(FuseRegisterTable),
   FuseRegisterTable
 };
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
index aec468659f..01feea4c7f 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
@@ -477,7 +477,7 @@ PcieFmPreInit (
     PcieFmExecuteNativeGen1Reconfig (Pcie);
   }
   Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]);
-  for (Index = 0; Index < (sizeof (PcieInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)); Index++) {
+  for (Index = 0; Index < ARRAY_SIZE(PcieInitTable); Index++) {
     PcieSiliconRegisterRMW (
       Silicon,
       PcieInitTable[Index].Reg,
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c
index b83afea231..318bb82566 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/PcieInit.c
@@ -198,7 +198,7 @@ PcieCommonCoreInit (
   if (PcieLibIsPcieWrapper (Wrapper)) {
     IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Enter\n");
     for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) {
-      for (Index = 0; Index < sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY); Index++) {
+      for (Index = 0; Index < ARRAY_SIZE(CoreInitTable); Index++) {
         UINT32 Value;
         Value = PcieRegisterRead (
                   Wrapper,
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c
index aebec59e86..7dc58d00bc 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/ON/mnS3on.c
@@ -240,7 +240,7 @@ PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorON[] = {
 
 CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefON = {
   0,
-  (sizeof (S3PciPreSelfRefDescriptorON) / sizeof (PCI_REG_DESCRIPTOR)),
+  ARRAY_SIZE(S3PciPreSelfRefDescriptorON),
   S3PciPreSelfRefDescriptorON,
   PciSpecialCaseFuncON
 };
@@ -293,7 +293,7 @@ CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorON[] = {
 
 CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefON = {
   0,
-  (sizeof (S3CPciPostSelfDescriptorON) / sizeof (CONDITIONAL_PCI_REG_DESCRIPTOR)),
+  ARRAY_SIZE(S3CPciPostSelfDescriptorON),
   S3CPciPostSelfDescriptorON,
   PciSpecialCaseFuncON
 };
@@ -307,7 +307,7 @@ MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorON[] = {
 
 CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefON = {
   0,
-  (sizeof (S3MSRPreSelfRefDescriptorON) / sizeof (MSR_REG_DESCRIPTOR)),
+  ARRAY_SIZE(S3MSRPreSelfRefDescriptorON),
   S3MSRPreSelfRefDescriptorON,
   NULL
 };
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c
index 64099f20d1..485d32dc96 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mt3.c
@@ -209,12 +209,12 @@ MemConstructTechBlock3 (
       //
       // Initialize the SPD pointers for each Dimm
       //
-      for (i = 0 ; i < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0])) ; i++) {
+      for (i = 0 ; i < ARRAY_SIZE(ChannelPtr->DimmSpdPtr); i++) {
         ChannelPtr->DimmSpdPtr[i] = NULL;
       }
       for (i = 0 ; i < DimmSlots; i++) {
         ChannelPtr->DimmSpdPtr[i] = &(ChannelPtr->SpdPtr[i]);
-        if ( (i + 2) < (sizeof (ChannelPtr->DimmSpdPtr) / sizeof (ChannelPtr->DimmSpdPtr[0]))) {
+        if ( (i + 2) < ARRAY_SIZE(ChannelPtr->DimmSpdPtr)) {
           if (ChannelPtr->DimmSpdPtr[i]->DimmPresent) {
             if ((((ChannelPtr->DimmSpdPtr[i]->Data[SPD_RANKS] >> 3) & 0x07) + 1) > 2) {
               ChannelPtr->DimmSpdPtr[i + 2] = &(ChannelPtr->SpdPtr[i]);