diff options
| author | Paul Menzel <paulepanter@users.sourceforge.net> | 2014-01-25 15:59:31 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-07 17:40:45 +0100 |
| commit | 2e0d9447db22183e2d3393d84e221e8bb1613d45 (patch) | |
| tree | d481c26efa3b5501505f116226d747dd36d730a3 /src/vendorcode/amd/agesa/f14/Proc | |
| parent | f8532b16bec1743b0528a215c71f67c8845e2a0c (diff) | |
src/vendorcode/amd: correct spelling of MTRR
Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/4806
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc')
4 files changed, 6 insertions, 6 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c index f5772e9e9f..329a526b55 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c @@ -280,7 +280,7 @@ AllocateExecutionCache ( RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTTR region, + // Region starts below 1MB - Fixed MTRR region, // turn on modification bit: MtrrFixDramModEn LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -298,7 +298,7 @@ AllocateExecutionCache ( i, RequestStartAddr, RequestSize, 0, StdHeader); } - // Find start MTTR and end MTTR for the requested region + // Find start MTRR and end MTRR for the requested region StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); @@ -324,7 +324,7 @@ AllocateExecutionCache ( } else { - // Region above 1MB - Variable MTTR region + // Region above 1MB - Variable MTRR region // Need to check both VarMTRRs for each requested region for match or overlap // diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm index 3ffe146946..de5201d1b1 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm @@ -173,7 +173,7 @@ EFLoop: .endw .endif - ; restore variable MTTR6 and MTTR7 to default states + ; restore variable MTRR6 and MTRR7 to default states mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6 xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7 xor edx, edx diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S index 48ee5d0238..137261c3be 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S @@ -157,7 +157,7 @@ EFLoop: jmp 5b /* .endw */ 4: /* .endif */ - /* restore variable MTTR6 and MTTR7 to default states */ + /* restore variable MTRR6 and MTRR7 to default states */ movl $AMD_MTRR_VARIABLE_BASE6, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */ xor %edx, %edx diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c index 800f10bffd..e7e66437a5 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c @@ -192,7 +192,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); |