diff options
author | efdesign98 <efdesign98@gmail.com> | 2011-09-14 19:34:13 -0600 |
---|---|---|
committer | Patrick Georgi <patrick@georgi-clan.de> | 2011-09-15 09:56:08 +0200 |
commit | 4d2d5d5b3e661683ab209d068ab7537332fe15f9 (patch) | |
tree | a6fbf33d6c72ad90396e7dfe7262ac46c972fd24 /src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe | |
parent | 3c59158810a6cbf3b8caccb9ff9fbb4bfc669e97 (diff) |
AMD Agesa macro expansion fix
This change fixes the use of a macro that was
previously modified to fix a warning. The macro
was used in a manner that doubly incremented a
pointer. The pointer increment was removed from
the macro call and moved elsewhere. In addition,
an unused macro was removed from both Family 12
and Family 14 code.
Change-Id: I577794bbc55d18f21170dda1d0bbdc6d776ce392
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/217
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe')
-rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c index 330a02e3d0..3821ac7110 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c @@ -263,12 +263,13 @@ PcieOnConfigureGppEnginesLaneAllocation ( CoreLaneIndex = 0; PortIdIndex = 0; do { + if (PortIdIndex > 0) EnginesList++; EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED; EnginesList->Type.Port.PortId = GppPortIdConfigurationTable [ConfigurationId][PortIdIndex++]; EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; - } while (IS_LAST_DESCRIPTOR (EnginesList++)); + } while (IS_LAST_DESCRIPTOR (EnginesList)); return AGESA_SUCCESS; } @@ -305,12 +306,13 @@ PcieOnConfigureDdiEnginesLaneAllocation ( } LaneIndex = 0; do { + if (LaneIndex > 0) EnginesList++; EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED; EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + Wrapper->StartPhyLane; - } while (IS_LAST_DESCRIPTOR (EnginesList++)); + } while (IS_LAST_DESCRIPTOR (EnginesList)); return AGESA_SUCCESS; } |