Update AMD F14 Agesa to support Rev C0 cpus

This change updates the AMD Agesa code to support the Family 14
rev C0 cpus.  It also fixes (again) a ton of warnings, although
not all of them are gone.  The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.

Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

4 files changed, 42 insertions, 12 deletions

diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c
index fed63ed525..64993b0217 100644
--- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c
+++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/Dispatcher.c
@@ -107,7 +107,7 @@ AmdAgesaDispatcher (
 
   // 2. Try next dispatcher if possible, and we have not already got status back
   if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
-    ModuleEntry = (MODULE_ENTRY) (UINT64) mCpuModuleID.NextBlock->ModuleDispatcher;
+    ModuleEntry = (MODULE_ENTRY) mCpuModuleID.NextBlock->ModuleDispatcher;
     if (ModuleEntry != NULL) {
       Status = (*ModuleEntry) (ConfigPtr);
     }
@@ -119,10 +119,10 @@ AmdAgesaDispatcher (
       ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr;
       ImageEnd = ImageStart + 4;
       // Locate/test image base that matches this component
-      AltImagePtr = LibAmdLocateImage ((VOID *) (UINT64)ImageStart, (VOID *) (UINT64)ImageEnd, 4096, AGESA_ID);
+      AltImagePtr = LibAmdLocateImage ((VOID *)ImageStart, (VOID *)ImageEnd, 4096, (CHAR8 *)AGESA_ID);
       if (AltImagePtr != NULL) {
         //Invoke alternative Image
-        ImageEntry = (IMAGE_ENTRY) ((UINT64) AltImagePtr + AltImagePtr->EntryPointAddress);
+        ImageEntry = (IMAGE_ENTRY) (AltImagePtr + AltImagePtr->EntryPointAddress);
         Status = (*ImageEntry) (ConfigPtr);
       }
     }
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c
index ffb712ef0b..350c8918a2 100644
--- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c
+++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/agesaCallouts.c
@@ -71,6 +71,12 @@
  *----------------------------------------------------------------------------------------
  */
 
+AGESA_STATUS
+AgesaGetIdsData  (
+  IN       UINTN              Data,
+  IN OUT   IDS_CALLOUT_STRUCT *IdsCalloutData
+  );
+
 /*----------------------------------------------------------------------------------------
  *                          E X P O R T E D    F U N C T I O N S
  *----------------------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
index d205b5488c..d3987fb5e2 100644
--- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
+++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c
@@ -58,7 +58,8 @@
 #include "cpuCacheInit.h"
 #include "cpuFamilyTranslation.h"
 #include "heapManager.h"
-#include "cpuLateInit.h"
+//#include "cpuLateInit.h"
+#include "cpuEnvInit.h"
 #include "Filecode.h"
 CODE_GROUP (G1_PEICC)
 RDATA_GROUP (G1_PEICC)
@@ -179,8 +180,8 @@ CopyHeapToTempRamAtPost (
     // Region above 1MB
     // Variable MTTR region
     // Get family specific cache Info
-    GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
-    FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader);
+    GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+    FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
 
     // Find an empty MTRRphysBase/MTRRphysMask
     for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
@@ -215,7 +216,7 @@ CopyHeapToTempRamAtPost (
     HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
     HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
 
-    BaseAddressInTempMem = (UINT8 *) UserOptions.CfgHeapDramAddress;
+    BaseAddressInTempMem = (UINT8 *) (UserOptions.CfgHeapDramAddress);
     HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem;
     HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
 
@@ -370,15 +371,15 @@ CopyHeapToMainRamAtPost (
   // if address of heap in temp memory is above 1M, then we must used one variable MTRR.
   if (StdHeader->HeapBasePtr >= 0x100000) {
     // Find out which variable MTRR was used in CopyHeapToTempRamAtPost.
-    GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
-    FamilySpecificServices->GetCacheInfo (FamilySpecificServices, &CacheInfoPtr, &Ignored, StdHeader);
+    GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
+    FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader);
     for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
          HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
          HeapRamVariableMtrr--) {
       LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
       LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
-      if ((VariableMtrrBase == (UINT64) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) &&
-          (VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) {
+      if ((VariableMtrrBase == ((UINT64)(StdHeader->HeapBasePtr) & CacheInfoPtr->HeapBaseMask)) &&
+          (VariableMtrrMask == (CacheInfoPtr->VariableMtrrHeapMask & AMD_HEAP_MTRR_MASK))) {
         break;
       }
     }
diff --git a/src/vendorcode/amd/agesa/f14/Legacy/agesa.inc b/src/vendorcode/amd/agesa/f14/Legacy/agesa.inc
index 65dd0ef7fa..84f9ec7bf1 100644
--- a/src/vendorcode/amd/agesa/f14/Legacy/agesa.inc
+++ b/src/vendorcode/amd/agesa/f14/Legacy/agesa.inc
@@ -9,7 +9,7 @@
 ; * @xrefitem bom "File Content Label" "Release Content"
 ; * @e project:      AGESA
 ; * @e sub-project:  Include
-; * @e \$Revision: 41505 $   @e \$Date: 2010-11-05 22:06:20 +0800 (Fri, 05 Nov 2010) $
+; * @e \$Revision: 47417 $   @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
 ;
 ;*****************************************************************************
 ; 
@@ -714,6 +714,23 @@ PCIE_HDP_TYPE TEXTEQU  <DWORD>
 ;----------------------------------------------------------------------------
 ;
 
+; LVDS Misc Control Field
+LVDS_MISC_CONTROL_FIELD         STRUCT
+  FpdiMode          UINT8       ?
+    ;IN  UINT8     FpdiMode:1;
+    ;IN  UINT8     DlChSwap:1;
+    ;IN  UINT8     VsyncActiveLow:1;
+    ;IN  UINT8     HsyncActiveLow:1;
+    ;IN  UINT8     BLONActiveLow:1;
+    ;IN  UINT8     Reserved:3;
+LVDS_MISC_CONTROL_FIELD         ENDS
+
+; LVDS Misc Control
+LVDS_MISC_CONTROL           UNION
+  Field        LVDS_MISC_CONTROL_FIELD   {}
+  Value        UINT8  ?
+LVDS_MISC_CONTROL           ENDS
+
 ; Configuration settings for GNB.
 GNB_ENV_CONFIGURATION          STRUCT
   Gnb3dStereoPinIndex          UINT8  ?       ;< 3D Stereo Pin ID.
@@ -726,6 +743,8 @@ GNB_ENV_CONFIGURATION          STRUCT
                                               ;  @li 6 = Use processor pin HPD6
   LvdsSpreadSpectrum           UINT16  ?      ; Spread spectrum value in 0.01 %
   LvdsSpreadSpectrumRate       UINT16  ?      ; Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+  LvdsMiscControl              LVDS_MISC_CONTROL   {}      ; This item configures LVDS swap/Hsync/Vsync/BLON
+  PcieRefClkSpreadSpectrum     UINT16  ?      ; Spread spectrum value in 0.01 %
 GNB_ENV_CONFIGURATION          ENDS
 
 ; GNB configuration info
@@ -1916,6 +1935,8 @@ BUILD_OPT_CFG    STRUCT
   CfgGnbPcieSSID                UINT32 ?        ; < Gnb PCIe SSID
   CfgLvdsSpreadSpectrum         UINT16  ?       ; < Lvds Spread Spectrum. Build-time customizable only
   CfgLvdsSpreadSpectrumRate     UINT16  ?       ; < Lvds Spread Spectrum Rate. Build-time customizable only
+  CfgLvdsMiscControl            LVDS_MISC_CONTROL   {}; THe LVDS Misc control
+  CfgPcieRefClkSpreadSpectrum   UINT16  ?       ; PCIe Reference Clock Spread Spectrum
   Reserved                      BOOLEAN ?       ; < reserved...
 BUILD_OPT_CFG    ENDS
 
@@ -2143,6 +2164,7 @@ TYPE17_DMI_INFO    STRUCT
   PartNumber                    CHAR8 (19) DUP (?)      ; < Part Number.
   Attributes                    UINT8 ?                 ; < Bits 7-4: Reserved, Bits 3-0: rank.
   ExtSize                       UINT32 ?                ; < Extended Size.
+  ConfigSpeed                   UINT16 ?                ; < Configured memory clock speed
 TYPE17_DMI_INFO    ENDS
 
  ; Memory DMI Type 17 and 20 - for memory use
@@ -2169,6 +2191,7 @@ MEM_DMI_INFO    STRUCT
   EndingAddr                    UINT32 ?              ; ///< The handle, or instance number, associated with
                                                       ; ///< the Memory Device structure to which this address
                                                       ; ///< range is mapped.
+  ConfigSpeed                   UINT16 ?              ; ///< Configured memory clock speed
 MEM_DMI_INFO    ENDS
 
  ; DMI Type 19 - Memory Array Mapped Address