Update AMD F14 Agesa to support Rev C0 cpus

This change updates the AMD Agesa code to support the Family 14
rev C0 cpus.  It also fixes (again) a ton of warnings, although
not all of them are gone.  The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.

Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

15 files changed, 225 insertions, 99 deletions

diff --git a/src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h b/src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h
index 573650a739..4d59387d0a 100644
--- a/src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h
+++ b/src/vendorcode/amd/agesa/f14/Include/AdvancedApi.h
@@ -10,14 +10,13 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  Include
- * @e \$Revision: 34897 $   @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $
+ * @e \$Revision: 44325 $   @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
  */
-/*
- *****************************************************************************
+/*****************************************************************************
  *
  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -28,7 +27,7 @@
  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
  *       its contributors may be used to endorse or promote products derived 
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -39,7 +38,7 @@
  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
+ *
  * ***************************************************************************
  *
  */
@@ -165,4 +164,11 @@ BOOLEAN
 memDefFalse (
   VOID
   );
+
+VOID
+MemRecDefRet (VOID);
+
+BOOLEAN
+MemRecDefTrue (VOID);
+
 #endif // _ADVANCED_API_H_
diff --git a/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h b/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h
index 67539655ce..b309cd4f9f 100644
--- a/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/BrazosInstall.h
@@ -11,10 +11,9 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  Core
- * @e \$Revision: 40817 $   @e \$Date: 2010-10-28 03:28:12 +0800 (Thu, 28 Oct 2010) $
+ * @e \$Revision: 53801 $   @e \$Date: 2011-05-25 12:03:55 -0600 (Wed, 25 May 2011) $
  */
-/*
- *****************************************************************************
+/*****************************************************************************
  *
  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
@@ -41,7 +40,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  * 
- * ***************************************************************************
+ ****************************************************************************
  *
  */
 
@@ -77,7 +76,7 @@
 
                   // This is the release version number of the AGESA component
                   // This string MUST be exactly 12 characters long
-#define AGESA_VERSION_STRING  {'V', '1', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
+#define AGESA_VERSION_STRING  {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
 
 
 // The Brazos solution is defined to be family 0x14 in the FT1 socket.
diff --git a/src/vendorcode/amd/agesa/f14/Include/Filecode.h b/src/vendorcode/amd/agesa/f14/Include/Filecode.h
index 9ba1b29f8f..bc574cc2db 100644
--- a/src/vendorcode/amd/agesa/f14/Include/Filecode.h
+++ b/src/vendorcode/amd/agesa/f14/Include/Filecode.h
@@ -12,7 +12,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  Include
- * @e \$Revision: 40742 $   @e \$Date: 2010-10-27 04:04:08 +0800 (Wed, 27 Oct 2010) $
+ * @e \$Revision: 46485 $   @e \$Date: 2011-02-03 09:03:14 -0700 (Thu, 03 Feb 2011) $
  */
 /*
  *****************************************************************************
@@ -426,12 +426,15 @@
 #define PROC_CPU_FAMILY_0X14_CPUF14PSTATE_FILECODE                       (0xCA0D)
 #define PROC_CPU_FAMILY_0X14_F14C6STATE_FILECODE                         (0xCA0E)
 #define PROC_CPU_FAMILY_0X14_F14IOCSTATE_FILECODE                        (0xCA0F)
+#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE             (0xCA10)
+#define PROC_CPU_FAMILY_0X14_CPUF14LOWPOWERINIT_FILECODE                 (0xCA11)
 #define PROC_CPU_FAMILY_0X14_ON_F14ONLOGICALIDTABLES_FILECODE            (0xCA21)
 #define PROC_CPU_FAMILY_0X14_ON_F14ONMICROCODEPATCHTABLES_FILECODE       (0xCA22)
 #define PROC_CPU_FAMILY_0X14_ON_F14ONEQUIVALENCETABLE_FILECODE           (0xCA23)
 #define PROC_CPU_FAMILY_0X14_ON_F14ONINITEARLYTABLE_FILECODE             (0xCA24)
-#define PROC_CPU_FAMILY_0X14_CPUF14PERCOREPCITABLES_FILECODE             (0xCA25)
 #define PROC_CPU_FAMILY_0X14_ON_F14ONEARLYSAMPLES_FILECODE               (0xCA26)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONCPB_FILECODE                        (0xCA2C)
+#define PROC_CPU_FAMILY_0X14_ON_F14ONPCITABLES_FILECODE                  (0xCA2D)
 
 // Family 15h
 #define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE              (0xCB01)
diff --git a/src/vendorcode/amd/agesa/f14/Include/GnbInterface.h b/src/vendorcode/amd/agesa/f14/Include/GnbInterface.h
index 761cf3af7e..ed708c9727 100644
--- a/src/vendorcode/amd/agesa/f14/Include/GnbInterface.h
+++ b/src/vendorcode/amd/agesa/f14/Include/GnbInterface.h
@@ -9,7 +9,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:     AGESA
  * @e sub-project: GNB
- * @e \$Revision: 37658 $   @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
+ * @e \$Revision: 44325 $   @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
  *
  */
 /*
@@ -17,7 +17,7 @@
  *
  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -28,7 +28,7 @@
  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
  *       its contributors may be used to endorse or promote products derived 
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -39,8 +39,8 @@
  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
+ *
+ ****************************************************************************
  *
  */
 
diff --git a/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h b/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h
index 0b3ff08223..231e06a801 100644
--- a/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h
+++ b/src/vendorcode/amd/agesa/f14/Include/GnbInterfaceStub.h
@@ -9,40 +9,40 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  GNB
- * @e \$Revision: 37658 $   @e \$Date: 2010-09-09 15:25:38 +0800 (Thu, 09 Sep 2010) $
+ * @e \$Revision: 44325 $   @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
  *
  */
 /*
- *****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- * 
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
- *       its contributors may be used to endorse or promote products derived 
- *       from this software without specific prior written permission.
- * 
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
- * ***************************************************************************
- *
- */
+*****************************************************************************
+*
+* Copyright (c) 2011, Advanced Micro Devices, Inc.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*     * Redistributions of source code must retain the above copyright
+*       notice, this list of conditions and the following disclaimer.
+*     * Redistributions in binary form must reproduce the above copyright
+*       notice, this list of conditions and the following disclaimer in the
+*       documentation and/or other materials provided with the distribution.
+*     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+*       its contributors may be used to endorse or promote products derived 
+*       from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* ***************************************************************************
+*
+*/
 
 /*----------------------------------------------------------------------------------------
  *                             M O D U L E S    U S E D
diff --git a/src/vendorcode/amd/agesa/f14/Include/Ids.h b/src/vendorcode/amd/agesa/f14/Include/Ids.h
index cbd0b131be..7baa67bd0c 100644
--- a/src/vendorcode/amd/agesa/f14/Include/Ids.h
+++ b/src/vendorcode/amd/agesa/f14/Include/Ids.h
@@ -9,14 +9,14 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  IDS
- * @e \$Revision: 38634 $   @e \$Date: 2010-09-27 21:39:01 +0800 (Mon, 27 Sep 2010) $
+ * @e \$Revision: 44325 $   @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
  */
 /*
  *****************************************************************************
  *
  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  * All rights reserved.
- * 
+ *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
@@ -27,7 +27,7 @@
  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
  *       its contributors may be used to endorse or promote products derived 
  *       from this software without specific prior written permission.
- * 
+ *
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -38,7 +38,7 @@
  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- * 
+ *
  * ***************************************************************************
  *
  */
@@ -568,12 +568,12 @@ typedef enum {                        //vv- for debug reference only
         #define IDS_HDT_CONSOLE(f, s, ...)
       #endif
     #else
-      #pragma warning(disable: 4127)
-      #ifdef __GNUC__
+      #ifndef __GNUC__	
+        #pragma warning(disable: 4127)
         #define IDS_HDT_CONSOLE(f, s, ...)
-      #else
-        #define IDS_HDT_CONSOLE(f, s, ...)
-      #endif
+	  #else
+		#define IDS_HDT_CONSOLE(f, s, ...)        printk (BIOS_DEBUG, s, ##__VA_ARGS__);
+      #endif                                            	
     #endif
 
     #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
@@ -625,7 +625,7 @@ typedef enum {                        //vv- for debug reference only
 #endif
 
 ///For IDS feat use
-#define IDS_FAMILY_ALL  0x0ull
+#define IDS_FAMILY_ALL  0xFFFFFFFFFFFFFFFFull
 #define IDS_BSP_ONLY    TRUE
 #define IDS_ALL_CORES   FALSE
 
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionCpbInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionCpbInstall.h
index 45f8498d69..f377a8e1dd 100644
--- a/src/vendorcode/amd/agesa/f14/Include/OptionCpbInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionCpbInstall.h
@@ -56,10 +56,11 @@
 #define OPTION_CPB_FEAT
 #define F10_CPB_SUPPORT
 #define F12_CPB_SUPPORT
+#define F14_ON_CPB_SUPPORT
 #define F15_CPB_SUPPORT
 
 #if OPTION_CPB == TRUE
-  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
+  #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
     // Family 10h
     #ifdef OPTION_FAMILY10H
       #if OPTION_FAMILY10H == TRUE
@@ -88,6 +89,20 @@
       #endif
     #endif
 
+    // Family 14h
+    #ifdef OPTION_FAMILY14H
+      #if OPTION_FAMILY14H == TRUE
+        #if OPTION_FAMILY14H_ON == TRUE
+          extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
+          #undef OPTION_CPB_FEAT
+          #define OPTION_CPB_FEAT &CpuFeatureCpb,
+          extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport;
+          #undef F14_ON_CPB_SUPPORT
+          #define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport},
+        #endif
+      #endif
+    #endif
+
     // Family 15h
     #ifdef OPTION_FAMILY15H
       #if OPTION_FAMILY15H == TRUE
@@ -109,6 +124,7 @@ CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
 {
   F10_CPB_SUPPORT
   F12_CPB_SUPPORT
+  F14_ON_CPB_SUPPORT
   F15_CPB_SUPPORT
   {0, NULL}
 };
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hInstall.h
index 38a287d5c0..1187c03be3 100644
--- a/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionFamily14hInstall.h
@@ -69,7 +69,7 @@ extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString2;
 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14CacheInfo;
 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14SysPmTable;
 extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14WheaInitData;
-extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
+//extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
 extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F14GetPlatformTypeSpecificInfo;
 extern F_CPU_GET_IDD_MAX F14GetProcIddMax;
 extern CONST REGISTER_TABLE ROMDATA F14PciRegisterTable;
@@ -90,6 +90,7 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
   #if OPTION_FAMILY14H_ON == TRUE
     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicroCodePatchesStruct;
     extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicrocodeEquivalenceTable;
+    extern CONST REGISTER_TABLE ROMDATA F14OnPciRegisterTable;
 
     #if USES_REGISTER_TABLES == TRUE
       CONST REGISTER_TABLE ROMDATA *F14OnRegisterTables[] =
@@ -106,6 +107,9 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
             &F14EarlySampleMsrRegisterTable,
           #endif
         #endif
+        #if MODEL_SPECIFIC_PCI == TRUE
+          &F14OnPciRegisterTable,
+        #endif
         // the end.
         NULL
       };
@@ -325,7 +329,8 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
     #if GET_PATCHES == TRUE
       #define F14_ON_UCODE_0B
       #define F14_ON_UCODE_1A
-      #define F14_ON_UCODE_25
+      #define F14_ON_UCODE_28
+      #define F14_ON_UCODE_101
 
       // If a patch is required for recovery mode to function properly, add a
       // conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
@@ -339,16 +344,21 @@ extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
           #undef F14_ON_UCODE_1A
           #define F14_ON_UCODE_1A &CpuF14MicrocodePatch0500001A,
         #endif
-        extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000025;
-        #undef F14_ON_UCODE_25
-        #define F14_ON_UCODE_25 &CpuF14MicrocodePatch05000025,
+        extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000028;
+        #undef F14_ON_UCODE_28
+        #define F14_ON_UCODE_28 &CpuF14MicrocodePatch05000028,
+
+	extern  CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000101;
+        #undef F14_ON_UCODE_101
+        #define F14_ON_UCODE_101 &CpuF14MicrocodePatch05000101,
       #endif
 
       CONST MICROCODE_PATCHES ROMDATA *CpuF14OnMicroCodePatchArray[] =
       {
+        F14_ON_UCODE_101
+        F14_ON_UCODE_28
         F14_ON_UCODE_0B
         F14_ON_UCODE_1A
-        F14_ON_UCODE_25
         NULL
       };
 
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionGnb.h b/src/vendorcode/amd/agesa/f14/Include/OptionGnb.h
index 5f3fbd60fc..ccc2292027 100644
--- a/src/vendorcode/amd/agesa/f14/Include/OptionGnb.h
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionGnb.h
@@ -81,7 +81,12 @@ typedef struct {
   BOOLEAN              LclkDpmEn;               ///< Default for LCLK DPM
   BOOLEAN              GmcPowerGateStutterOnly; ///< Force GMC power gate to stutter only
   BOOLEAN              SmuSclkClockGatingEnable;///< Control SMU SCLK gating
-  BOOLEAN              PcieAspmBlackListEnable;       ///< Control Pcie Aspm Black List
+  BOOLEAN              PcieAspmBlackListEnable;      ///< Control Pcie Aspm Black List
+  UINT32               LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
+  UINT32               LinkL0Pooling;                ///< Pooling for link to get to L0 in us
+  UINT32               LinkGpioResetAssertionTime;   ///< Gpio reset assertion time in us
+  UINT32               LinkResetToTrainingTime;      ///< Time duration between deassert GPIO reset and release training in us                                                      ///
+  UINT8                TrainingAlgorithm;            ///< Training algorithm (see PCIE_TRAINING_ALGORITHM)
 } GNB_BUILD_OPTIONS;
 
 /*----------------------------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionGnbInstall.h
index d8acee7c6d..db4730293d 100644
--- a/src/vendorcode/amd/agesa/f14/Include/OptionGnbInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionGnbInstall.h
@@ -10,7 +10,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  Options
- * @e \$Revision: 40151 $   @e \$Date: 2010-10-20 06:38:17 +0800 (Wed, 20 Oct 2010) $
+ * @e \$Revision: 44325 $   @e \$Date: 2010-12-22 03:29:53 -0700 (Wed, 22 Dec 2010) $
  */
 /*
  *****************************************************************************
@@ -58,6 +58,9 @@
 #define GNB_TYPE_KR FALSE
 #define GNB_TYPE_TN FALSE
 
+#include "Gnb.h"
+#include "GnbPcie.h"
+
 #ifndef CFG_IGFX_AS_PCIE_EP
   #define CFG_IGFX_AS_PCIE_EP     TRUE
 #endif
@@ -94,13 +97,40 @@
   #define CFG_PCIE_ASPM_BLACK_LIST_ENABLE     TRUE
 #endif
 
+#ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
+  #define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING  (60 * 1000)
+#endif
+
+#ifndef CFG_GNB_PCIE_LINK_L0_POOLING
+  #define CFG_GNB_PCIE_LINK_L0_POOLING                  (60 * 1000)
+#endif
+
+#ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
+  #define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME      (2 * 1000)
+#endif
+
+#ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
+  #define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME      (2 * 1000)
+#endif
+
+#ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
+  #define CFG_GNB_PCIE_TRAINING_ALGORITHM               BLDCFG_PCIE_TRAINING_ALGORITHM
+#else
+  #define CFG_GNB_PCIE_TRAINING_ALGORITHM               PcieTrainingStandard
+#endif
+
 GNB_BUILD_OPTIONS  GnbBuildOptions = {
   CFG_IGFX_AS_PCIE_EP,
   CFG_LCLK_DEEP_SLEEP_EN,
   CFG_LCLK_DPM_EN,
   CFG_GMC_POWER_GATE_STUTTER_ONLY,
   CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
-  CFG_PCIE_ASPM_BLACK_LIST_ENABLE
+  CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
+  CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
+  CFG_GNB_PCIE_LINK_L0_POOLING,
+  CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
+  CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
+  CFG_GNB_PCIE_TRAINING_ALGORITHM
 };
 
 
@@ -204,6 +234,16 @@ GNB_BUILD_OPTIONS  GnbBuildOptions = {
     #define OPTION_NBINITATPOST_ENTRY
   #endif
 //---------------------------------------------------------------------------------------------------
+  #ifndef OPTION_PCIE_POST_EALRY_INIT
+    #define OPTION_PCIE_POST_EALRY_INIT TRUE
+  #endif
+  #if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
+    OPTION_GNB_FEATURE                                  PcieInitAtPostEarly;
+    #define OPTION_PCIEINITATPOSTEARLY_ENTRY            {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly},
+  #else
+    #define OPTION_PCIEINITATPOSTEARLY_ENTRY
+  #endif
+//---------------------------------------------------------------------------------------------------
   #ifndef OPTION_PCIE_POST_INIT
     #define OPTION_PCIE_POST_INIT TRUE
   #endif
@@ -215,6 +255,7 @@ GNB_BUILD_OPTIONS  GnbBuildOptions = {
   #endif
 //---------------------------------------------------------------------------------------------------
   OPTION_GNB_CONFIGURATION  GnbPostFeatureTable[] = {
+    OPTION_PCIEINITATPOSTEARLY_ENTRY
     OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
     OPTION_GFXINITATPOST_ENTRY
     {0, NULL}
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionMemory.h b/src/vendorcode/amd/agesa/f14/Include/OptionMemory.h
index 1d4c08f68b..a753c6dac2 100644
--- a/src/vendorcode/amd/agesa/f14/Include/OptionMemory.h
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionMemory.h
@@ -320,10 +320,22 @@ BOOLEAN MemFDefRet (
 BOOLEAN MemMDefRet (
   IN MEM_MAIN_DATA_BLOCK *MMPtr
   );
+
+BOOLEAN MemMDefRetFalse (
+  IN   MEM_MAIN_DATA_BLOCK *MMPtr
+  );
+
 /* Table Feature Default Return */
 UINT8 MemFTableDefRet (
   IN OUT   MEM_TABLE_ALIAS **MTPtr
   );
+
+BOOLEAN MemNIdentifyDimmConstructorRetDef (
+  IN OUT   MEM_NB_BLOCK *NBPtr,
+  IN OUT   MEM_DATA_STRUCT *MemPtr,
+  IN       UINT8 NodeID
+  );
+
 /* S3 Feature Default Return */
 BOOLEAN MemFS3DefConstructorRet (
   IN OUT   VOID *S3NBPtr,
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h
index 2f41757e87..6072cd4d4c 100644
--- a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryInstall.h
@@ -314,74 +314,65 @@ BOOLEAN MemFS3DefConstructorRet (
    *  based upon the number of processor families that the BIOS will support.
    */
 
+  extern MEM_FLOW_CFG MemMFlowDef;
   #if (OPTION_MEMCTLR_DR == TRUE)
     extern MEM_FLOW_CFG MemMFlowDr;
     #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDr,
   #else
-    extern MEM_FLOW_CFG MemMFlowDef;
     #define MEM_MAIN_FLOW_CONTROL_PTR_Dr MemMFlowDef,
   #endif
   #if (OPTION_MEMCTLR_DA == TRUE)
     extern MEM_FLOW_CFG MemMFlowDA;
     #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDA,
   #else
-    extern MEM_FLOW_CFG MemMFlowDef;
     #define MEM_MAIN_FLOW_CONTROL_PTR_DA MemMFlowDef,
   #endif
   #if (OPTION_MEMCTLR_HY == TRUE)
     extern MEM_FLOW_CFG MemMFlowHy;
     #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowHy,
   #else
-    extern MEM_FLOW_CFG MemMFlowDef;
     #define MEM_MAIN_FLOW_CONTROL_PTR_Hy MemMFlowDef,
   #endif
   #if (OPTION_MEMCTLR_OR == TRUE)
     extern MEM_FLOW_CFG MemMFlowOr;
     #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowOr,
   #else
-    extern MEM_FLOW_CFG MemMFlowDef;
     #define MEM_MAIN_FLOW_CONTROL_PTR_OR MemMFlowDef,
   #endif
   #if (OPTION_MEMCTLR_LN == TRUE)
     extern MEM_FLOW_CFG MemMFlowLN;
     #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowLN,
   #else
-    extern MEM_FLOW_CFG MemMFlowDef;
     #define MEM_MAIN_FLOW_CONTROL_PTR_LN MemMFlowDef,
   #endif
   #if (OPTION_MEMCTLR_C32 == TRUE)
     extern MEM_FLOW_CFG MemMFlowC32;
     #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowC32,
   #else
-    extern MEM_FLOW_CFG MemMFlowDef;
     #define MEM_MAIN_FLOW_CONTROL_PTR_C32 MemMFlowDef,
   #endif
   #if (OPTION_MEMCTLR_ON == TRUE)
     extern MEM_FLOW_CFG MemMFlowON;
     #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowON,
   #else
-    extern MEM_FLOW_CFG MemMFlowDef;
     #define MEM_MAIN_FLOW_CONTROL_PTR_ON MemMFlowDef,
   #endif
   #if (OPTION_MEMCTLR_Ni == TRUE)
     extern MEM_FLOW_CFG MemMFlowDA;
     #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDA,
   #else
-    extern MEM_FLOW_CFG MemMFlowDef;
     #define MEM_MAIN_FLOW_CONTROL_PTR_Ni MemMFlowDef,
   #endif
   #if (OPTION_MEMCTLR_RB == TRUE)
     extern MEM_FLOW_CFG MemMFlowRb;
     #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowRb,
   #else
-    extern MEM_FLOW_CFG MemMFlowDef;
     #define MEM_MAIN_FLOW_CONTROL_PTR_RB MemMFlowDef,
   #endif
   #if (OPTION_MEMCTLR_PH == TRUE)
     extern MEM_FLOW_CFG MemMFlowPh;
     #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowPh,
   #else
-    extern MEM_FLOW_CFG MemMFlowDef;
     #define MEM_MAIN_FLOW_CONTROL_PTR_PH MemMFlowDef,
   #endif
 
@@ -464,13 +455,6 @@ BOOLEAN MemFS3DefConstructorRet (
     #define MEM_FEATURE_ECCX8  MemMDefRet
   #endif
 
-  #if (OPTION_EMP == TRUE)
-    extern OPTION_MEM_FEATURE_NB MemFInitEMP;
-    #define MEM_FEATURE_EMP   MemFInitEMP
-  #else
-    #define MEM_FEATURE_EMP   MemFDefRet
-  #endif
-
   extern OPTION_MEM_FEATURE_MAIN MemMMctMemClr;
   #define MEM_MAIN_FEATURE_MEM_CLEAR  MemMMctMemClr
 
@@ -505,11 +489,11 @@ BOOLEAN MemFS3DefConstructorRet (
   extern OPTION_MEM_FEATURE_MAIN MemMUmaAlloc;
   #define MEM_MAIN_FEATURE_UMAALLOC   MemMUmaAlloc
 
+  extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
   #if (OPTION_PARALLEL_TRAINING == TRUE)
     extern OPTION_MEM_FEATURE_MAIN MemMParallelTraining;
     #define MEM_MAIN_FEATURE_TRAINING  MemMParallelTraining
   #else
-    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
   #endif
 
@@ -555,7 +539,7 @@ BOOLEAN MemFS3DefConstructorRet (
       #define  MEM_TECH_FEATURE_HW_DRAMINIT MemTFeatDef
     #endif
     #if (OPTION_SW_DRAM_INIT == TRUE)
-      extern MEM_TECH_FEAT MemTDramInitSw3;
+//      extern MEM_TECH_FEAT MemTDramInitSw3;
       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTDramInitSw3
     #else
       #define MEM_TECH_FEATURE_SW_DRAMINIT  MemTFeatDef
@@ -956,7 +940,6 @@ BOOLEAN MemFS3DefConstructorRet (
 
     #undef MEM_MAIN_FEATURE_TRAINING
     #undef MEM_FEATURE_TRAINING
-    extern OPTION_MEM_FEATURE_MAIN MemMStandardTraining;
     #define MEM_MAIN_FEATURE_TRAINING  MemMStandardTraining
     extern OPTION_MEM_FEATURE_NB MemFStandardTraining;
     #define MEM_FEATURE_TRAINING  MemFStandardTraining
@@ -2284,9 +2267,9 @@ BOOLEAN MemFS3DefConstructorRet (
         TECH_TRAIN_OPT_SW_RD_WR_POS_DDR3,
         TECH_TRAIN_MAX_RD_LAT_DDR3
       };
-      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
+//      extern OPTION_MEM_FEATURE_NB MemNDQSTiming3Nb;
       #define NB_TRAIN_FLOW_DDR3    MemNDQSTiming3Nb
-      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
+//      extern OPTION_MEM_FEATURE_NB memNSequenceDDR3Nb;
       #define MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_ON {MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION,memNSequenceDDR3Nb, memNEnableTrainSequenceON, &memTechTrainingFeatSequenceDDR3ON },
     #else
       #undef TECH_TRAIN_ENTER_HW_TRN_DDR3
@@ -3253,9 +3236,9 @@ BOOLEAN MemFS3DefConstructorRet (
     NULL
   };
   CONST UINTN SIZE_OF_PLATFORM = (sizeof (memPlatformTypeInstalled) / sizeof (MEM_PLATFORM_CFG*));
-  #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
-    #error   Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
-  #endif
+//  #if SIZE_OF_PLATFORM > MAX_PLATFORM_TYPES
+//    #error   Size of memPlatformTypeInstalled array larger than MAX_PLATFORM_TYPES
+//  #endif
 
   /*---------------------------------------------------------------------------------------------------
    * EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryRecoveryInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryRecoveryInstall.h
index 20199473c4..91435dc1ce 100644
--- a/src/vendorcode/amd/agesa/f14/Include/OptionMemoryRecoveryInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionMemoryRecoveryInstall.h
@@ -579,7 +579,7 @@
    *
    *---------------------------------------------------------------------------------------------------
    */
-  MEM_NB_SUPPORT MemRecNBInstalled[] = {
+  MEM_NB_SUPPORT* MemRecNBInstalled[] = {
     NULL
   };
   /*----------------------------------------------------------------------
diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionPstateInstall.h
index 11ae4d3cfe..b289910429 100644
--- a/src/vendorcode/amd/agesa/f14/Include/OptionPstateInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/OptionPstateInstall.h
@@ -101,7 +101,7 @@
     #error  BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
   #endif
   #if (OPTION_ACPI_PSTATES == TRUE)
-    OPTION_SSDT_FEATURE               GenerateSsdt;
+//    OPTION_SSDT_FEATURE               GenerateSsdt;
     #define USER_SSDT_MAIN            GenerateSsdt
     #ifndef OPTION_MULTISOCKET
       #error  BLDOPT: Option not defined: "OPTION_MULTISOCKET"
diff --git a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h
index 31a311b865..d2d032896f 100644
--- a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h
+++ b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h
@@ -11,7 +11,7 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  Core
- * @e \$Revision: 41504 $   @e \$Date: 2010-11-05 21:59:13 +0800 (Fri, 05 Nov 2010) $
+ * @e \$Revision: 47417 $   @e \$Date: 2011-02-18 12:48:20 -0700 (Fri, 18 Feb 2011) $
  */
 /*
  *****************************************************************************
@@ -79,7 +79,7 @@
 VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
   //ModuleHeaderSignature
   // Remove 'DOM$' as temp solution before update BinUtil.exe ,
-  '0000',
+  Int32FromChar ('0', '0', '0', '0'),
   //ModuleIdentifier[8]
   AGESA_ID,
   //ModuleVersion[12]
@@ -1015,6 +1015,8 @@ VOLATILE  AMD_MODULE_HEADER mCpuModuleID = {
     #define OPTION_GFX_RECOVERY  TRUE
     #undef OPTION_C6_STATE
     #define OPTION_C6_STATE  TRUE
+    #undef OPTION_CPB
+    #define OPTION_CPB TRUE
     #undef OPTION_IO_CSTATE
     #define OPTION_IO_CSTATE TRUE
     #undef OPTION_S3SCRIPT
@@ -1937,6 +1939,12 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
   #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE               0
 #endif
 
+#ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
+  #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
+#else
+  #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM               0
+#endif
+
 #ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
   #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
 #else
@@ -1963,6 +1971,35 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE;
   #endif
 #endif
 
+#ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
+  #define CFG_LVDS_MISC_888_FPDI_MODE                 BLDCFG_LVDS_MISC_888_FPDI_MODE
+#else
+  #define CFG_LVDS_MISC_888_FPDI_MODE                 FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
+  #define CFG_LVDS_MISC_DL_CH_SWAP                 BLDCFG_LVDS_MISC_DL_CH_SWAP
+#else
+  #define CFG_LVDS_MISC_DL_CH_SWAP                 FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
+  #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW                 BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
+#else
+  #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW                 FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
+  #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW                 BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
+#else
+  #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW                 FALSE
+#endif
+
+#ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
+  #define CFG_LVDS_MISC_BLON_ACTIVE_LOW                 BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
+#else
+  #define CFG_LVDS_MISC_BLON_ACTIVE_LOW                 FALSE
+#endif
 /*---------------------------------------------------------------------------
  *       Processing the options:  Third, perform the option cross checks
  *--------------------------------------------------------------------------*/
@@ -2281,6 +2318,14 @@ BUILD_OPT_CFG UserOptions = {
   CFG_GFX_LVDS_SPREAD_SPECTRUM,         // CfgLvdsSpreadSpectrum
   CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE,    // CfgLvdsSpreadSpectrumRate
 
+  {{
+	CFG_LVDS_MISC_888_FPDI_MODE,          // CfgLvdsMiscControl
+	CFG_LVDS_MISC_DL_CH_SWAP,             // CfgLvdsMiscControl
+	CFG_LVDS_MISC_VSYNC_ACTIVE_LOW,       // CfgLvdsMiscControl
+	CFG_LVDS_MISC_HSYNC_ACTIVE_LOW,       // CfgLvdsMiscControl
+	CFG_LVDS_MISC_BLON_ACTIVE_LOW,        // CfgLvdsMiscControl
+  }},
+  CFG_PCIE_REFCLK_SPREAD_SPECTRUM,      // CfgPcieRefClkSpreadSpectrum
   0,                                    //reserved...
 };
 
@@ -2384,7 +2429,7 @@ CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
       AMD_LATE_RUN_AP_TASK_HANDLE
     },
   #endif
-  { 0, NULL }
+  { 0, 0, NULL }
 };
 
 CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0])));
@@ -2591,6 +2636,12 @@ CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
 
           MAKE_DBG_STR (\nCfgLvdsSpreadSpectrum  , CFG_GFX_LVDS_SPREAD_SPECTRUM),
           MAKE_DBG_STR (\nCfgLvdsSpreadSpectrumRate , CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE),
+          MAKE_DBG_STR (\nCfgLvdsMiscControl.FpdiMode   , CFG_LVDS_MISC_888_FPDI_MODE),
+          MAKE_DBG_STR (\nCfgLvdsMiscControl.DlChSwap           , CFG_LVDS_MISC_DL_CH_SWAP),
+          MAKE_DBG_STR (\nCfgLvdsMiscControl.VsyncActiveLow     , CFG_LVDS_MISC_VSYNC_ACTIVE_LOW),
+          MAKE_DBG_STR (\nCfgLvdsMiscControl.HsyncActiveLow     , CFG_LVDS_MISC_HSYNC_ACTIVE_LOW),
+          MAKE_DBG_STR (\nCfgLvdsMiscControl.BLONActiveLow      , CFG_LVDS_MISC_BLON_ACTIVE_LOW),
+          MAKE_DBG_STR (\nCfgPcieRefClkSpreadSpectrum   , CFG_PCIE_REFCLK_SPREAD_SPECTRUM),
         #endif
         NULL
       };