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authorKyösti Mälkki <kyosti.malkki@gmail.com>2016-04-19 15:17:50 +0300
committerStefan Reinauer <stefan.reinauer@coreboot.org>2016-04-21 07:39:13 +0200
commitdefbdcf3e58a7148ecd3c448e4d1e6683d54bd22 (patch)
tree6b3f4c44594420b5e88e58045ab810836a3770e0 /src/vendorcode/amd/agesa/f12
parente0383d2ce8b92b9efaa1e10f7234a7bb607a8a23 (diff)
AGESA vendorcode: Fix type mismatch
Fix is required to compile AGESA ramstage without raminit. Change-Id: I783883fa7a12e8a647aa432535bb990a47257e9b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14416 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f12')
-rw-r--r--src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h
index cfb55cc7a5..4fd5354d05 100644
--- a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h
+++ b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h
@@ -4033,7 +4033,7 @@ BOOLEAN MemFS3DefConstructorRet (
*---------------------------------------------------------------------------------------------------
*/
MEM_FEAT_BLOCK_MAIN MemFeatMain = {
- NULL
+ 0
};
/*---------------------------------------------------------------------------------------------------
@@ -4086,18 +4086,18 @@ BOOLEAN MemFS3DefConstructorRet (
*/
#if OPTION_DDR2
MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = {
- NULL
+ 0
};
MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = {
- NULL
+ 0
};
#endif
#if OPTION_DDR3
MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = {
- NULL
+ 0
};
MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = {
- NULL
+ 0
};
#endif
/*---------------------------------------------------------------------------------------------------