From defbdcf3e58a7148ecd3c448e4d1e6683d54bd22 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 19 Apr 2016 15:17:50 +0300 Subject: AGESA vendorcode: Fix type mismatch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix is required to compile AGESA ramstage without raminit. Change-Id: I783883fa7a12e8a647aa432535bb990a47257e9b Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/14416 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh --- src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/vendorcode/amd/agesa/f12') diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h index cfb55cc7a5..4fd5354d05 100644 --- a/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/OptionMemoryInstall.h @@ -4033,7 +4033,7 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ MEM_FEAT_BLOCK_MAIN MemFeatMain = { - NULL + 0 }; /*--------------------------------------------------------------------------------------------------- @@ -4086,18 +4086,18 @@ BOOLEAN MemFS3DefConstructorRet ( */ #if OPTION_DDR2 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { - NULL + 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { - NULL + 0 }; #endif #if OPTION_DDR3 MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { - NULL + 0 }; MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { - NULL + 0 }; #endif /*--------------------------------------------------------------------------------------------------- -- cgit v1.2.3