diff options
| author | Frank Vibrans <frank.vibrans@amd.com> | 2011-02-14 18:30:54 +0000 |
|---|---|---|
| committer | Marc Jones <marc.jones@amd.com> | 2011-02-14 18:30:54 +0000 |
| commit | 2b4c831b4d16b55a7abdea20bce82cccd168232c (patch) | |
| tree | 95a35c737d16119f1dfa9c1c9d7700710d8a04f7 /src/vendorcode/amd/agesa/Proc/GNB/PCIe | |
| parent | 74ad66cdc143e04f976ba21e538e02b20362d7e6 (diff) | |
Add AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.
This code currently generates many warnings that are functionally benign. These are being addressed, but the wheels of bureaucracy turn slowly. This drop supports AMD cpu families 10h and 14h. Only Family 14h is used as an example in this set of patches. Other cpu families are supported by the infrastructure, but their specific support is not included herein. This patch is functionally independent of the other patches in this set.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/vendorcode/amd/agesa/Proc/GNB/PCIe')
32 files changed, 5422 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c new file mode 100644 index 0000000000..e23cc7c543 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c @@ -0,0 +1,72 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe ALIB + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "F14PcieAlibSsdt.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEALIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl new file mode 100644 index 0000000000..d33c341048 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.esl @@ -0,0 +1,126 @@ +/** + * @file + * + * ALIB ASL library + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 31805 $ @e \$Date: 2010-05-21 17:58:16 -0700 (Fri, 21 May 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +DefinitionBlock ( + "F14PcieAlibSsdt.aml", + "SSDT", + 2, + "AMD", + "ALIB", + 0x1 + ) +{ + Scope(\_SB) { + + Name (varMaxPortIndexNumber, 6) + + include ("PcieAlibCore.asl") + include ("PcieSmuLibV1.asl") + include ("PcieAlibPspp.asl") + include ("PcieAlibHotplug.asl") + + /*----------------------------------------------------------------------------------------*/ + /** + * Activate DPM state + * + * Arg0 - 1 - GEN1 2 - GEN2 + * Arg1 - 0 (AC) 1 (DC) + */ + Method (procNbLclkDpmActivate, 2, NotSerialized) { + + Store (procSmuRcuRead (0x8490), Local0) + // Patch state only if at least one state is enable + if (LNotEqual (And (Local0, 0xF0), 0)) { + if (LEqual (Arg0, 2)) { + //If AC/DC, & Gen2 supported, activate state DPM0 and DPM2, + //set SMUx0B_x8490[LclkDpmValid[5, 7] = 1, set SMUx0B_x8490[LclkDpmValid[6]] = 0 + //This is a battery ¡¥idle¡¦ state along with a ¡¥perf¡¦ state that will be programmed to the max LCLK achievable at the Gen2 VID + And (Local0, 0xFFFFFFA0, Local0) + Or (Local0, 0xA0, Local0) + + } else { + if (LEqual (Arg1, 0)) { + //If AC, & if only Gen1 supported, activate state DPM0 and DPM1 + //set SMUx0B_x8490[LclkDpmValid[6, 5]] = 1, set SMUx0B_x8490[LclkDpmValid[7]] = 0 + And (Local0, 0xFFFFFF60, Local0) + Or (Local0, 0x60, Local0) + } else { + //If DC mode & Gen1 supported, activate only state DPM0 + //set SMUx0B_x8490[LclkDpmValid[7, 6]] = 0, set SMUx0B_x8490[LclkDpmValid[5]] = 1 + And (Local0, 0xFFFFFF20, Local0) + Or (Local0, 0x20, Local0) + } + } + procSmuRcuWrite (0x8490, Local0) + } + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Power gate PCIe phy lanes (hotplug support) + * + * Arg0 - Start Lane ID + * Arg1 - End Lane ID + * Arg2 - Power ON(1) / OFF(0) + */ + Method (procPcieLanePowerControl, 3, NotSerialized) { + // stub function + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Read RCU register + * + * Arg0 - 1 - GEN1 2 - GEN2 + * + */ + Method (procPcieAdjustPll, 1, NotSerialized) { + //stub function + } + + } //End of Scope(\_SB) +} //End of DefinitionBlock + + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h new file mode 100644 index 0000000000..533521b4a3 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h @@ -0,0 +1,660 @@ +/** + * @file + * + * ALIB SSDT table + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e $Revision:$ @e $Date:$ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _F14PCIEALIBSSDT_H_ +#define _F14PCIEALIBSSDT_H_ + +UINT8 AlibSsdt[] = { + 0x53, 0x53, 0x44, 0x54, 0xFA, 0x12, 0x00, 0x00, + 0x02, 0xC9, 0x41, 0x4D, 0x44, 0x00, 0x00, 0x00, + 0x41, 0x4C, 0x49, 0x42, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x00, 0x4D, 0x53, 0x46, 0x54, + 0x00, 0x00, 0x00, 0x04, 0x10, 0x85, 0x2D, 0x01, + 0x5C, 0x5F, 0x53, 0x42, 0x5F, 0x08, 0x41, 0x30, + 0x30, 0x31, 0x0A, 0x06, 0x08, 0x41, 0x44, 0x30, + 0x31, 0x0C, 0x00, 0x00, 0x00, 0xE0, 0x06, 0x41, + 0x44, 0x30, 0x31, 0x41, 0x30, 0x39, 0x31, 0x08, + 0x41, 0x44, 0x30, 0x37, 0x12, 0x45, 0x06, 0x07, + 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, + 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x11, 0x0D, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, + 0x0A, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x11, 0x0D, 0x0A, 0x0A, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x06, 0x41, 0x44, 0x30, 0x37, 0x41, + 0x30, 0x39, 0x32, 0x14, 0x41, 0x05, 0x41, 0x4C, + 0x49, 0x42, 0x02, 0xA0, 0x0B, 0x93, 0x68, 0x0A, + 0x01, 0xA4, 0x41, 0x30, 0x31, 0x38, 0x69, 0xA0, + 0x0B, 0x93, 0x68, 0x0A, 0x02, 0xA4, 0x41, 0x30, + 0x32, 0x31, 0x69, 0xA0, 0x0B, 0x93, 0x68, 0x0A, + 0x03, 0xA4, 0x41, 0x30, 0x33, 0x32, 0x69, 0xA0, + 0x0B, 0x93, 0x68, 0x0A, 0x04, 0xA4, 0x41, 0x30, + 0x36, 0x33, 0x69, 0xA0, 0x0A, 0x93, 0x68, 0x0A, + 0x05, 0xA4, 0x41, 0x30, 0x39, 0x33, 0xA0, 0x0B, + 0x93, 0x68, 0x0A, 0x06, 0xA4, 0x41, 0x30, 0x36, + 0x36, 0x69, 0xA4, 0x0A, 0x00, 0x14, 0x09, 0x41, + 0x30, 0x39, 0x33, 0x08, 0xA4, 0x0A, 0x00, 0x14, + 0x31, 0x41, 0x30, 0x33, 0x31, 0x02, 0x72, 0x41, + 0x30, 0x39, 0x31, 0x79, 0x68, 0x0A, 0x0C, 0x00, + 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, 0x80, 0x41, + 0x30, 0x39, 0x34, 0x00, 0x60, 0x0A, 0x04, 0x5B, + 0x81, 0x0B, 0x41, 0x30, 0x39, 0x34, 0x03, 0x41, + 0x30, 0x39, 0x35, 0x20, 0xA4, 0x41, 0x30, 0x39, + 0x35, 0x14, 0x32, 0x41, 0x30, 0x35, 0x39, 0x03, + 0x72, 0x41, 0x30, 0x39, 0x31, 0x79, 0x68, 0x0A, + 0x0C, 0x00, 0x60, 0x72, 0x69, 0x60, 0x60, 0x5B, + 0x80, 0x41, 0x30, 0x39, 0x34, 0x00, 0x60, 0x0A, + 0x04, 0x5B, 0x81, 0x0B, 0x41, 0x30, 0x39, 0x34, + 0x03, 0x41, 0x30, 0x39, 0x35, 0x20, 0x70, 0x6A, + 0x41, 0x30, 0x39, 0x35, 0x14, 0x1C, 0x41, 0x30, + 0x35, 0x35, 0x04, 0x70, 0x41, 0x30, 0x33, 0x31, + 0x68, 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, + 0x6B, 0x60, 0x41, 0x30, 0x35, 0x39, 0x68, 0x69, + 0x60, 0x5B, 0x01, 0x41, 0x30, 0x39, 0x36, 0x00, + 0x14, 0x32, 0x41, 0x30, 0x35, 0x38, 0x02, 0x5B, + 0x23, 0x41, 0x30, 0x39, 0x36, 0xFF, 0xFF, 0x70, + 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, 0x0A, 0x03, + 0x00, 0x60, 0x41, 0x30, 0x35, 0x39, 0x60, 0x0A, + 0xE0, 0x69, 0x70, 0x41, 0x30, 0x33, 0x31, 0x60, + 0x0A, 0xE4, 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39, + 0x36, 0xA4, 0x60, 0x14, 0x2F, 0x41, 0x30, 0x39, + 0x37, 0x03, 0x5B, 0x23, 0x41, 0x30, 0x39, 0x36, + 0xFF, 0xFF, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, + 0x00, 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x35, + 0x39, 0x60, 0x0A, 0xE0, 0x69, 0x41, 0x30, 0x35, + 0x39, 0x60, 0x0A, 0xE4, 0x6A, 0x5B, 0x27, 0x41, + 0x30, 0x39, 0x36, 0x14, 0x1C, 0x41, 0x30, 0x35, + 0x34, 0x04, 0x70, 0x41, 0x30, 0x35, 0x38, 0x68, + 0x69, 0x60, 0x7D, 0x7B, 0x60, 0x6A, 0x00, 0x6B, + 0x60, 0x41, 0x30, 0x39, 0x37, 0x68, 0x69, 0x60, + 0x5B, 0x01, 0x41, 0x30, 0x39, 0x38, 0x00, 0x14, + 0x29, 0x41, 0x30, 0x36, 0x31, 0x03, 0x5B, 0x23, + 0x41, 0x30, 0x39, 0x38, 0xFF, 0xFF, 0x41, 0x30, + 0x35, 0x39, 0x68, 0x69, 0x6A, 0x70, 0x41, 0x30, + 0x33, 0x31, 0x68, 0x72, 0x69, 0x0A, 0x04, 0x00, + 0x60, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x38, 0xA4, + 0x60, 0x14, 0x26, 0x41, 0x30, 0x36, 0x32, 0x04, + 0x5B, 0x23, 0x41, 0x30, 0x39, 0x38, 0xFF, 0xFF, + 0x41, 0x30, 0x35, 0x39, 0x68, 0x69, 0x6A, 0x41, + 0x30, 0x35, 0x39, 0x68, 0x72, 0x69, 0x0A, 0x04, + 0x00, 0x6B, 0x5B, 0x27, 0x41, 0x30, 0x39, 0x38, + 0x14, 0x1E, 0x41, 0x30, 0x35, 0x33, 0x05, 0x70, + 0x41, 0x30, 0x36, 0x31, 0x68, 0x69, 0x6A, 0x60, + 0x7D, 0x7B, 0x60, 0x6B, 0x00, 0x6C, 0x60, 0x41, + 0x30, 0x36, 0x32, 0x68, 0x69, 0x6A, 0x60, 0x14, + 0x0F, 0x41, 0x30, 0x37, 0x33, 0x01, 0xA4, 0x83, + 0x88, 0x41, 0x30, 0x39, 0x32, 0x68, 0x00, 0x14, + 0x42, 0x05, 0x41, 0x30, 0x35, 0x36, 0x02, 0x70, + 0x0A, 0x34, 0x61, 0xA0, 0x11, 0x93, 0x41, 0x30, + 0x33, 0x31, 0x68, 0x0A, 0x00, 0x0C, 0xFF, 0xFF, + 0xFF, 0xFF, 0xA4, 0x0A, 0x00, 0x70, 0x0A, 0x01, + 0x60, 0xA2, 0x2E, 0x93, 0x60, 0x0A, 0x01, 0x70, + 0x7B, 0x41, 0x30, 0x33, 0x31, 0x68, 0x61, 0x0A, + 0xFF, 0x00, 0x61, 0xA0, 0x1C, 0x92, 0x93, 0x61, + 0x0A, 0x00, 0xA0, 0x11, 0x93, 0x7B, 0x41, 0x30, + 0x33, 0x31, 0x68, 0x61, 0x0A, 0xFF, 0x00, 0x69, + 0x70, 0x0A, 0x00, 0x60, 0xA1, 0x03, 0x75, 0x61, + 0xA4, 0x61, 0x14, 0x47, 0x09, 0x41, 0x30, 0x35, + 0x37, 0x02, 0x5B, 0x80, 0x50, 0x4D, 0x49, 0x4F, + 0x01, 0x0B, 0xD6, 0x0C, 0x0A, 0x02, 0x5B, 0x81, + 0x10, 0x50, 0x4D, 0x49, 0x4F, 0x01, 0x50, 0x4D, + 0x52, 0x49, 0x08, 0x50, 0x4D, 0x52, 0x44, 0x08, + 0x5B, 0x86, 0x12, 0x50, 0x4D, 0x52, 0x49, 0x50, + 0x4D, 0x52, 0x44, 0x01, 0x00, 0x40, 0x70, 0x41, + 0x42, 0x41, 0x52, 0x20, 0x5B, 0x80, 0x41, 0x43, + 0x46, 0x47, 0x01, 0x41, 0x42, 0x41, 0x52, 0x0A, + 0x08, 0x5B, 0x81, 0x10, 0x41, 0x43, 0x46, 0x47, + 0x03, 0x41, 0x42, 0x49, 0x58, 0x20, 0x41, 0x42, + 0x44, 0x41, 0x20, 0x70, 0x0A, 0x00, 0x60, 0xA0, + 0x17, 0x93, 0x69, 0x0A, 0x00, 0x70, 0x0C, 0x68, + 0x00, 0x00, 0x80, 0x41, 0x42, 0x49, 0x58, 0x70, + 0x41, 0x42, 0x44, 0x41, 0x60, 0xA4, 0x60, 0xA1, + 0x22, 0x70, 0x0C, 0x68, 0x00, 0x00, 0x80, 0x41, + 0x42, 0x49, 0x58, 0x70, 0x41, 0x42, 0x44, 0x41, + 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFC, 0xFF, 0xFF, + 0xFF, 0x00, 0x68, 0x60, 0x70, 0x60, 0x41, 0x42, + 0x44, 0x41, 0x14, 0x48, 0x05, 0x41, 0x30, 0x38, + 0x36, 0x01, 0x70, 0x41, 0x30, 0x36, 0x31, 0x0A, + 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x75, 0x68, + 0x7D, 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, + 0x00, 0x7B, 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0xFF, + 0xFF, 0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10, + 0x00, 0x60, 0x41, 0x30, 0x36, 0x32, 0x0A, 0x00, + 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70, 0x41, 0x30, + 0x36, 0x31, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCE, + 0x60, 0xA4, 0x60, 0x14, 0x47, 0x0A, 0x41, 0x30, + 0x38, 0x37, 0x03, 0x70, 0x41, 0x30, 0x36, 0x31, + 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, 0x70, + 0x7B, 0x69, 0x0B, 0xFF, 0xFF, 0x00, 0x61, 0x7D, + 0x7B, 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, + 0x7B, 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, + 0x00, 0xFD, 0x00, 0x79, 0x68, 0x0A, 0x10, 0x00, + 0x60, 0x7D, 0x60, 0x0C, 0x00, 0x00, 0x00, 0x02, + 0x60, 0x7D, 0x60, 0x61, 0x60, 0x41, 0x30, 0x36, + 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xCD, 0x60, + 0xA0, 0x4A, 0x04, 0x93, 0x6A, 0x0A, 0x01, 0x70, + 0x7A, 0x69, 0x0A, 0x10, 0x00, 0x61, 0x7D, 0x7B, + 0x60, 0x0C, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x7B, + 0x80, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x01, 0x00, + 0x60, 0x7D, 0x7B, 0x60, 0x0C, 0x00, 0x00, 0x00, + 0xFF, 0x00, 0x79, 0x72, 0x68, 0x0A, 0x01, 0x00, + 0x0A, 0x10, 0x00, 0x60, 0x7D, 0x60, 0x61, 0x60, + 0x41, 0x30, 0x36, 0x32, 0x0A, 0x00, 0x0A, 0x60, + 0x0A, 0xCD, 0x60, 0x14, 0x4F, 0x04, 0x41, 0x30, + 0x38, 0x38, 0x02, 0x7D, 0x79, 0x68, 0x0A, 0x03, + 0x00, 0x0A, 0x01, 0x60, 0x41, 0x30, 0x38, 0x37, + 0x0A, 0x03, 0x60, 0x0A, 0x01, 0xA0, 0x15, 0x90, + 0x69, 0x0A, 0x01, 0xA2, 0x0F, 0x92, 0x93, 0x7B, + 0x41, 0x30, 0x38, 0x36, 0x0A, 0x03, 0x0A, 0x02, + 0x00, 0x0A, 0x02, 0xA0, 0x15, 0x90, 0x69, 0x0A, + 0x02, 0xA2, 0x0F, 0x92, 0x93, 0x7B, 0x41, 0x30, + 0x38, 0x36, 0x0A, 0x03, 0x0A, 0x04, 0x00, 0x0A, + 0x04, 0x41, 0x30, 0x38, 0x37, 0x0A, 0x03, 0x0A, + 0x00, 0x0A, 0x00, 0x14, 0x18, 0x41, 0x30, 0x30, + 0x34, 0x02, 0x41, 0x30, 0x38, 0x37, 0x0A, 0x0B, + 0x68, 0x0A, 0x00, 0x41, 0x30, 0x38, 0x37, 0x0A, + 0x05, 0x69, 0x0A, 0x01, 0x14, 0x19, 0x41, 0x30, + 0x30, 0x33, 0x01, 0x41, 0x30, 0x38, 0x37, 0x0A, + 0x0B, 0x68, 0x0A, 0x00, 0x70, 0x41, 0x30, 0x38, + 0x36, 0x0A, 0x05, 0x60, 0xA4, 0x60, 0x14, 0x49, + 0x07, 0x41, 0x30, 0x38, 0x39, 0x01, 0x70, 0x7D, + 0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C, 0x00, 0x50, + 0x86, 0x01, 0x00, 0x60, 0x70, 0x7D, 0x7B, 0x68, + 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x0A, 0x04, + 0x00, 0x61, 0x70, 0x7D, 0x79, 0x0A, 0x03, 0x0A, + 0x1E, 0x00, 0x79, 0x0A, 0x01, 0x0A, 0x12, 0x00, + 0x00, 0x62, 0x41, 0x30, 0x30, 0x34, 0x0B, 0x00, + 0x86, 0x60, 0x41, 0x30, 0x30, 0x34, 0x0B, 0x04, + 0x86, 0x61, 0x41, 0x30, 0x30, 0x34, 0x0B, 0x08, + 0x86, 0x62, 0xA0, 0x12, 0x93, 0x7A, 0x68, 0x0A, + 0x10, 0x00, 0x0B, 0x00, 0xFE, 0x41, 0x30, 0x38, + 0x38, 0x0A, 0x0D, 0x0A, 0x03, 0xA0, 0x12, 0x93, + 0x7A, 0x68, 0x0A, 0x10, 0x00, 0x0B, 0x30, 0xFE, + 0x41, 0x30, 0x38, 0x38, 0x0A, 0x0B, 0x0A, 0x03, + 0xA4, 0x41, 0x30, 0x30, 0x33, 0x0B, 0x50, 0x86, + 0x14, 0x44, 0x06, 0x41, 0x30, 0x39, 0x30, 0x02, + 0x70, 0x7D, 0x7B, 0x68, 0x0A, 0xFF, 0x00, 0x0C, + 0x00, 0x50, 0x86, 0x01, 0x00, 0x60, 0x70, 0x7D, + 0x7B, 0x68, 0x0C, 0x00, 0xFF, 0xFF, 0xFF, 0x00, + 0x0A, 0x04, 0x00, 0x61, 0x70, 0x7D, 0x79, 0x0A, + 0x03, 0x0A, 0x1E, 0x00, 0x79, 0x0A, 0x01, 0x0A, + 0x12, 0x00, 0x00, 0x62, 0x7D, 0x62, 0x79, 0x0A, + 0x01, 0x0A, 0x10, 0x00, 0x62, 0x41, 0x30, 0x30, + 0x34, 0x0B, 0x00, 0x86, 0x60, 0x41, 0x30, 0x30, + 0x34, 0x0B, 0x04, 0x86, 0x61, 0x41, 0x30, 0x30, + 0x34, 0x0B, 0x08, 0x86, 0x62, 0x41, 0x30, 0x30, + 0x34, 0x0B, 0x50, 0x86, 0x69, 0x41, 0x30, 0x38, + 0x38, 0x0A, 0x0B, 0x0A, 0x03, 0x08, 0x41, 0x44, + 0x30, 0x32, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, + 0x32, 0x41, 0x30, 0x30, 0x37, 0x08, 0x41, 0x44, + 0x30, 0x33, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, + 0x33, 0x41, 0x30, 0x30, 0x38, 0x08, 0x41, 0x44, + 0x30, 0x34, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, + 0x34, 0x41, 0x30, 0x30, 0x39, 0x08, 0x41, 0x44, + 0x30, 0x35, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, + 0x35, 0x41, 0x30, 0x31, 0x30, 0x08, 0x41, 0x44, + 0x30, 0x36, 0x12, 0x10, 0x07, 0x0A, 0x00, 0x0A, + 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, + 0x00, 0x0A, 0x00, 0x06, 0x41, 0x44, 0x30, 0x36, + 0x41, 0x30, 0x31, 0x31, 0x08, 0x41, 0x30, 0x31, + 0x32, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x33, + 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, 0x34, 0x12, + 0x10, 0x07, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, + 0x08, 0x41, 0x30, 0x31, 0x35, 0x12, 0x10, 0x07, + 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, + 0x30, 0x31, 0x36, 0x12, 0x10, 0x07, 0x0A, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x31, + 0x37, 0x12, 0x10, 0x07, 0x0A, 0x02, 0x0A, 0x02, + 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02, + 0x0A, 0x02, 0x14, 0x42, 0x06, 0x41, 0x30, 0x31, + 0x38, 0x09, 0x8C, 0x68, 0x0A, 0x02, 0x41, 0x30, + 0x31, 0x39, 0xA0, 0x0D, 0x93, 0x41, 0x30, 0x31, + 0x39, 0x41, 0x30, 0x31, 0x33, 0xA4, 0x0A, 0x00, + 0x70, 0x41, 0x30, 0x31, 0x39, 0x41, 0x30, 0x31, + 0x33, 0xA0, 0x12, 0x93, 0x41, 0x30, 0x30, 0x37, + 0x0A, 0x04, 0x41, 0x30, 0x30, 0x32, 0x0A, 0x01, + 0x41, 0x30, 0x31, 0x33, 0xA0, 0x15, 0x91, 0x92, + 0x94, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x01, 0x92, + 0x95, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x04, 0xA4, + 0x0A, 0x00, 0xA0, 0x0B, 0x93, 0x41, 0x30, 0x31, + 0x32, 0x0A, 0x00, 0xA4, 0x0A, 0x00, 0x41, 0x30, + 0x32, 0x30, 0xA4, 0x0A, 0x00, 0x14, 0x42, 0x18, + 0x41, 0x30, 0x32, 0x31, 0x01, 0x08, 0x41, 0x30, + 0x32, 0x32, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x32, + 0x33, 0x0A, 0x00, 0x70, 0x11, 0x04, 0x0B, 0x00, + 0x01, 0x67, 0x8B, 0x67, 0x0A, 0x00, 0x41, 0x30, + 0x32, 0x34, 0x70, 0x0A, 0x03, 0x41, 0x30, 0x32, + 0x34, 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30, 0x32, + 0x35, 0x70, 0x0A, 0x01, 0x41, 0x30, 0x32, 0x35, + 0xA0, 0x14, 0x91, 0x92, 0x94, 0x41, 0x30, 0x30, + 0x37, 0x0A, 0x01, 0x92, 0x95, 0x41, 0x30, 0x30, + 0x37, 0x0A, 0x04, 0xA4, 0x67, 0xA0, 0x0A, 0x93, + 0x41, 0x30, 0x31, 0x32, 0x0A, 0x00, 0xA4, 0x67, + 0x8B, 0x68, 0x0A, 0x02, 0x41, 0x30, 0x32, 0x36, + 0x8B, 0x68, 0x0A, 0x04, 0x41, 0x30, 0x32, 0x37, + 0x8B, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x32, 0x38, + 0x8C, 0x68, 0x0A, 0x08, 0x41, 0x30, 0x32, 0x39, + 0x8C, 0x68, 0x0A, 0x09, 0x41, 0x30, 0x33, 0x30, + 0x7B, 0x7A, 0x41, 0x30, 0x32, 0x36, 0x0A, 0x08, + 0x00, 0x0A, 0xFF, 0x41, 0x30, 0x32, 0x32, 0xA2, + 0x4E, 0x0E, 0x92, 0x94, 0x41, 0x30, 0x32, 0x33, + 0x41, 0x30, 0x30, 0x31, 0xA0, 0x15, 0x93, 0x83, + 0x88, 0x41, 0x30, 0x31, 0x31, 0x41, 0x30, 0x32, + 0x33, 0x00, 0x0A, 0x00, 0x75, 0x41, 0x30, 0x32, + 0x33, 0x9F, 0x70, 0x41, 0x30, 0x33, 0x31, 0x79, + 0x72, 0x41, 0x30, 0x32, 0x33, 0x0A, 0x02, 0x00, + 0x0A, 0x03, 0x00, 0x0A, 0x18, 0x61, 0x7B, 0x7A, + 0x61, 0x0A, 0x10, 0x00, 0x0A, 0xFF, 0x62, 0x7B, + 0x7A, 0x61, 0x0A, 0x08, 0x00, 0x0A, 0xFF, 0x61, + 0xA0, 0x14, 0x90, 0x95, 0x41, 0x30, 0x32, 0x32, + 0x61, 0x94, 0x41, 0x30, 0x32, 0x32, 0x62, 0x75, + 0x41, 0x30, 0x32, 0x33, 0x9F, 0xA0, 0x1E, 0x93, + 0x83, 0x88, 0x41, 0x30, 0x31, 0x34, 0x41, 0x30, + 0x32, 0x33, 0x00, 0x0A, 0x00, 0x70, 0x41, 0x30, + 0x32, 0x36, 0x88, 0x41, 0x30, 0x31, 0x34, 0x41, + 0x30, 0x32, 0x33, 0x00, 0xA1, 0x16, 0xA0, 0x14, + 0x92, 0x93, 0x83, 0x88, 0x41, 0x30, 0x31, 0x34, + 0x41, 0x30, 0x32, 0x33, 0x00, 0x41, 0x30, 0x32, + 0x36, 0xA4, 0x67, 0xA0, 0x15, 0x93, 0x41, 0x30, + 0x33, 0x30, 0x0A, 0x00, 0x70, 0x0A, 0x00, 0x88, + 0x41, 0x30, 0x31, 0x34, 0x41, 0x30, 0x32, 0x33, + 0x00, 0xA1, 0x37, 0xA0, 0x24, 0x93, 0x7B, 0x41, + 0x30, 0x32, 0x37, 0x41, 0x30, 0x32, 0x38, 0x00, + 0x0A, 0x01, 0x70, 0x83, 0x88, 0x41, 0x30, 0x31, + 0x31, 0x41, 0x30, 0x32, 0x33, 0x00, 0x88, 0x41, + 0x30, 0x31, 0x35, 0x41, 0x30, 0x32, 0x33, 0x00, + 0xA1, 0x10, 0x70, 0x41, 0x30, 0x33, 0x30, 0x88, + 0x41, 0x30, 0x31, 0x35, 0x41, 0x30, 0x32, 0x33, + 0x00, 0x41, 0x30, 0x32, 0x30, 0x70, 0x0A, 0x02, + 0x41, 0x30, 0x32, 0x35, 0xA4, 0x67, 0xA4, 0x67, + 0x14, 0x41, 0x0C, 0x41, 0x30, 0x33, 0x32, 0x09, + 0x70, 0x11, 0x04, 0x0B, 0x00, 0x01, 0x67, 0x8B, + 0x67, 0x0A, 0x00, 0x41, 0x30, 0x32, 0x34, 0x70, + 0x0A, 0x03, 0x41, 0x30, 0x32, 0x34, 0x8C, 0x67, + 0x0A, 0x02, 0x41, 0x30, 0x32, 0x35, 0x8C, 0x68, + 0x0A, 0x02, 0x41, 0x30, 0x33, 0x33, 0x70, 0x41, + 0x30, 0x33, 0x33, 0x41, 0x30, 0x31, 0x32, 0xA0, + 0x12, 0x93, 0x41, 0x30, 0x30, 0x37, 0x0A, 0x04, + 0x41, 0x30, 0x30, 0x32, 0x0A, 0x01, 0x41, 0x30, + 0x31, 0x33, 0xA0, 0x47, 0x06, 0x90, 0x94, 0x41, + 0x30, 0x30, 0x37, 0x0A, 0x01, 0x95, 0x41, 0x30, + 0x30, 0x37, 0x0A, 0x04, 0xA0, 0x16, 0x93, 0x41, + 0x30, 0x30, 0x37, 0x0A, 0x02, 0x41, 0x30, 0x33, + 0x34, 0x71, 0x41, 0x30, 0x31, 0x31, 0x71, 0x41, + 0x30, 0x31, 0x36, 0xA1, 0x0F, 0x41, 0x30, 0x33, + 0x34, 0x71, 0x41, 0x30, 0x31, 0x37, 0x71, 0x41, + 0x30, 0x31, 0x36, 0xA0, 0x2A, 0x93, 0x41, 0x30, + 0x31, 0x32, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x33, + 0x35, 0x12, 0x0E, 0x06, 0x0A, 0x00, 0x0A, 0x00, + 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, + 0x41, 0x30, 0x33, 0x34, 0x71, 0x41, 0x30, 0x33, + 0x35, 0x71, 0x41, 0x30, 0x31, 0x34, 0x41, 0x30, + 0x32, 0x30, 0x70, 0x0A, 0x03, 0x41, 0x30, 0x32, + 0x34, 0x70, 0x0A, 0x00, 0x41, 0x30, 0x32, 0x35, + 0xA4, 0x67, 0x14, 0x4A, 0x13, 0x41, 0x30, 0x32, + 0x30, 0x08, 0x08, 0x41, 0x30, 0x32, 0x33, 0x0A, + 0x00, 0x08, 0x41, 0x30, 0x33, 0x36, 0x0A, 0x00, + 0x08, 0x41, 0x30, 0x33, 0x37, 0x12, 0x10, 0x07, + 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02, + 0x0A, 0x02, 0x0A, 0x02, 0x0A, 0x02, 0x70, 0x0A, + 0x00, 0x41, 0x30, 0x32, 0x33, 0xA2, 0x34, 0x92, + 0x94, 0x41, 0x30, 0x32, 0x33, 0x41, 0x30, 0x30, + 0x31, 0xA0, 0x23, 0x92, 0x93, 0x83, 0x88, 0x41, + 0x30, 0x31, 0x31, 0x41, 0x30, 0x32, 0x33, 0x00, + 0x0A, 0x00, 0x70, 0x41, 0x30, 0x33, 0x38, 0x41, + 0x30, 0x32, 0x33, 0x88, 0x41, 0x30, 0x33, 0x37, + 0x41, 0x30, 0x32, 0x33, 0x00, 0x75, 0x41, 0x30, + 0x32, 0x33, 0xA0, 0x1F, 0x92, 0x93, 0x89, 0x41, + 0x30, 0x33, 0x37, 0x01, 0x0A, 0x01, 0x00, 0x0A, + 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x33, 0x34, + 0x71, 0x41, 0x30, 0x31, 0x37, 0x71, 0x41, 0x30, + 0x33, 0x37, 0xA0, 0x2B, 0x92, 0x93, 0x89, 0x41, + 0x30, 0x33, 0x37, 0x01, 0x0A, 0x03, 0x00, 0x0A, + 0x00, 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x33, 0x39, + 0x41, 0x30, 0x30, 0x38, 0x0A, 0x01, 0x41, 0x30, + 0x30, 0x36, 0x0A, 0x02, 0x41, 0x30, 0x30, 0x32, + 0x0A, 0x02, 0x41, 0x30, 0x31, 0x33, 0x70, 0x0A, + 0x00, 0x41, 0x30, 0x32, 0x33, 0xA2, 0x44, 0x05, + 0x92, 0x94, 0x41, 0x30, 0x32, 0x33, 0x41, 0x30, + 0x30, 0x31, 0xA0, 0x15, 0x93, 0x83, 0x88, 0x41, + 0x30, 0x31, 0x31, 0x41, 0x30, 0x32, 0x33, 0x00, + 0x0A, 0x00, 0x75, 0x41, 0x30, 0x32, 0x33, 0x9F, + 0x70, 0x41, 0x30, 0x34, 0x30, 0x41, 0x30, 0x32, + 0x33, 0x60, 0x70, 0x83, 0x88, 0x41, 0x30, 0x33, + 0x37, 0x41, 0x30, 0x32, 0x33, 0x00, 0x62, 0xA0, + 0x0A, 0x93, 0x60, 0x62, 0x75, 0x41, 0x30, 0x32, + 0x33, 0x9F, 0x41, 0x30, 0x34, 0x31, 0x41, 0x30, + 0x32, 0x33, 0x62, 0x0A, 0x00, 0x75, 0x41, 0x30, + 0x32, 0x33, 0xA0, 0x2A, 0x93, 0x89, 0x41, 0x30, + 0x33, 0x37, 0x01, 0x0A, 0x03, 0x00, 0x0A, 0x00, + 0x0A, 0x00, 0xFF, 0x41, 0x30, 0x30, 0x32, 0x0A, + 0x01, 0x41, 0x30, 0x31, 0x33, 0x41, 0x30, 0x30, + 0x36, 0x0A, 0x01, 0x41, 0x30, 0x33, 0x39, 0x41, + 0x30, 0x30, 0x39, 0x0A, 0x00, 0x14, 0x3A, 0x41, + 0x30, 0x33, 0x38, 0x01, 0x70, 0x0A, 0x03, 0x60, + 0xA0, 0x21, 0x93, 0x83, 0x88, 0x41, 0x30, 0x31, + 0x34, 0x68, 0x00, 0x0A, 0x00, 0xA0, 0x14, 0x91, + 0x93, 0x41, 0x30, 0x31, 0x33, 0x0A, 0x01, 0x93, + 0x41, 0x30, 0x30, 0x37, 0x0A, 0x03, 0x70, 0x0A, + 0x02, 0x60, 0xA1, 0x0B, 0x70, 0x83, 0x88, 0x41, + 0x30, 0x31, 0x35, 0x68, 0x00, 0x60, 0xA4, 0x60, + 0x14, 0x0F, 0x41, 0x30, 0x34, 0x30, 0x01, 0xA4, + 0x83, 0x88, 0x41, 0x30, 0x31, 0x36, 0x68, 0x00, + 0x14, 0x4C, 0x2E, 0x41, 0x30, 0x34, 0x31, 0x03, + 0xA0, 0x44, 0x2E, 0x91, 0x93, 0x69, 0x0A, 0x02, + 0x93, 0x69, 0x0A, 0x03, 0x08, 0x41, 0x30, 0x34, + 0x32, 0x0C, 0x01, 0x00, 0x00, 0x20, 0x08, 0x41, + 0x30, 0x34, 0x33, 0x0A, 0x00, 0x08, 0x41, 0x30, + 0x34, 0x34, 0x0A, 0x02, 0x08, 0x41, 0x30, 0x34, + 0x35, 0x0A, 0x00, 0x08, 0x41, 0x30, 0x34, 0x36, + 0x0A, 0x00, 0x08, 0x41, 0x30, 0x34, 0x37, 0x0A, + 0x00, 0x08, 0x41, 0x30, 0x34, 0x38, 0x0A, 0x00, + 0x08, 0x41, 0x30, 0x34, 0x39, 0x0A, 0x00, 0x08, + 0x41, 0x30, 0x35, 0x30, 0x0A, 0x00, 0x08, 0x41, + 0x30, 0x35, 0x31, 0x0A, 0x00, 0x08, 0x41, 0x30, + 0x35, 0x32, 0x12, 0x14, 0x09, 0x0A, 0x00, 0x0A, + 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, + 0x00, 0x0A, 0x00, 0x0A, 0x00, 0x0A, 0x00, 0xA0, + 0x15, 0x93, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x35, + 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0x80, 0x80, + 0x0A, 0x40, 0x00, 0x0A, 0x40, 0x70, 0x69, 0x88, + 0x41, 0x30, 0x31, 0x36, 0x68, 0x00, 0xA0, 0x13, + 0x93, 0x69, 0x0A, 0x02, 0x70, 0x0A, 0x00, 0x41, + 0x30, 0x34, 0x32, 0x70, 0x0A, 0x21, 0x41, 0x30, + 0x34, 0x34, 0xA0, 0x1B, 0x92, 0x93, 0x83, 0x88, + 0x41, 0x30, 0x31, 0x34, 0x68, 0x00, 0x0A, 0x00, + 0x41, 0x30, 0x35, 0x34, 0x68, 0x0A, 0xA1, 0x80, + 0x0B, 0x00, 0x10, 0x00, 0x0A, 0x00, 0xA1, 0x10, + 0x41, 0x30, 0x35, 0x34, 0x68, 0x0A, 0xA1, 0x80, + 0x0B, 0x00, 0x10, 0x00, 0x0B, 0x00, 0x10, 0x41, + 0x30, 0x35, 0x34, 0x68, 0x0A, 0xA4, 0x80, 0x0C, + 0x01, 0x00, 0x00, 0x20, 0x00, 0x41, 0x30, 0x34, + 0x32, 0x70, 0x79, 0x72, 0x68, 0x0A, 0x02, 0x00, + 0x0A, 0x03, 0x00, 0x60, 0x41, 0x30, 0x35, 0x35, + 0x60, 0x0A, 0x88, 0x80, 0x0A, 0x2F, 0x00, 0x41, + 0x30, 0x34, 0x34, 0x70, 0x79, 0x72, 0x68, 0x0A, + 0x02, 0x00, 0x0A, 0x03, 0x00, 0x60, 0x7B, 0x41, + 0x30, 0x33, 0x31, 0x60, 0x0A, 0x70, 0x0C, 0x00, + 0x00, 0x40, 0x00, 0x41, 0x30, 0x34, 0x33, 0xA0, + 0x45, 0x1B, 0x92, 0x93, 0x41, 0x30, 0x34, 0x33, + 0x0A, 0x00, 0xA0, 0x4D, 0x0C, 0x92, 0x93, 0x68, + 0x0A, 0x06, 0x70, 0x41, 0x30, 0x33, 0x31, 0x60, + 0x0A, 0x18, 0x63, 0x70, 0x7B, 0x7A, 0x63, 0x0A, + 0x08, 0x00, 0x0A, 0xFF, 0x00, 0x41, 0x30, 0x34, + 0x37, 0x70, 0x79, 0x41, 0x30, 0x34, 0x37, 0x0A, + 0x08, 0x00, 0x63, 0x70, 0x41, 0x30, 0x33, 0x31, + 0x63, 0x0A, 0x0C, 0x63, 0x70, 0x7B, 0x7A, 0x63, + 0x0A, 0x10, 0x00, 0x0A, 0xFF, 0x00, 0x41, 0x30, + 0x34, 0x38, 0xA0, 0x14, 0x92, 0x93, 0x7B, 0x41, + 0x30, 0x34, 0x38, 0x0A, 0x80, 0x00, 0x0A, 0x00, + 0x70, 0x0A, 0x07, 0x41, 0x30, 0x34, 0x39, 0x70, + 0x79, 0x41, 0x30, 0x34, 0x37, 0x0A, 0x08, 0x00, + 0x63, 0x70, 0x0A, 0x00, 0x62, 0xA2, 0x4A, 0x06, + 0x92, 0x94, 0x62, 0x41, 0x30, 0x34, 0x39, 0x70, + 0x41, 0x30, 0x35, 0x36, 0x63, 0x0A, 0x10, 0x41, + 0x30, 0x35, 0x30, 0xA0, 0x40, 0x05, 0x92, 0x93, + 0x41, 0x30, 0x35, 0x30, 0x0A, 0x00, 0x72, 0x41, + 0x30, 0x35, 0x30, 0x0A, 0x10, 0x41, 0x30, 0x35, + 0x30, 0x70, 0x41, 0x30, 0x33, 0x31, 0x63, 0x41, + 0x30, 0x35, 0x30, 0x41, 0x30, 0x35, 0x31, 0x70, + 0x7B, 0x41, 0x30, 0x35, 0x31, 0x0A, 0x03, 0x00, + 0x88, 0x41, 0x30, 0x35, 0x32, 0x62, 0x00, 0xA0, + 0x1C, 0x92, 0x93, 0x7B, 0x41, 0x30, 0x35, 0x31, + 0x0A, 0x03, 0x00, 0x0A, 0x00, 0x41, 0x30, 0x35, + 0x35, 0x63, 0x41, 0x30, 0x35, 0x30, 0x80, 0x0A, + 0x03, 0x00, 0x0A, 0x00, 0x75, 0x62, 0x75, 0x63, + 0xA1, 0x25, 0x70, 0x41, 0x30, 0x35, 0x37, 0x0A, + 0x00, 0x0A, 0x00, 0x41, 0x30, 0x34, 0x35, 0x7B, + 0x41, 0x30, 0x34, 0x35, 0x0A, 0x03, 0x61, 0xA0, + 0x0E, 0x92, 0x93, 0x61, 0x0A, 0x00, 0x41, 0x30, + 0x35, 0x37, 0x0A, 0x00, 0x0A, 0x01, 0x70, 0x0A, + 0x01, 0x62, 0xA2, 0x41, 0x05, 0x62, 0x41, 0x30, + 0x35, 0x35, 0x60, 0x0A, 0x68, 0x80, 0x0A, 0x00, + 0x00, 0x0A, 0x20, 0x5B, 0x22, 0x0A, 0x1E, 0xA2, + 0x13, 0x7B, 0x41, 0x30, 0x33, 0x31, 0x60, 0x0A, + 0x68, 0x0C, 0x00, 0x00, 0x00, 0x08, 0x00, 0x5B, + 0x22, 0x0A, 0x0A, 0x70, 0x0A, 0x00, 0x62, 0xA0, + 0x24, 0x93, 0x69, 0x0A, 0x02, 0x70, 0x41, 0x30, + 0x35, 0x38, 0x68, 0x0A, 0xA4, 0x41, 0x30, 0x34, + 0x36, 0xA0, 0x12, 0x92, 0x93, 0x7B, 0x41, 0x30, + 0x34, 0x36, 0x0B, 0x00, 0x08, 0x00, 0x0A, 0x00, + 0x70, 0x0A, 0x01, 0x62, 0xA0, 0x44, 0x05, 0x92, + 0x93, 0x68, 0x0A, 0x06, 0x70, 0x79, 0x41, 0x30, + 0x34, 0x37, 0x0A, 0x08, 0x00, 0x63, 0x70, 0x0A, + 0x00, 0x62, 0xA2, 0x3E, 0x92, 0x94, 0x62, 0x41, + 0x30, 0x34, 0x39, 0x70, 0x41, 0x30, 0x35, 0x36, + 0x63, 0x0A, 0x10, 0x41, 0x30, 0x35, 0x30, 0xA0, + 0x25, 0x92, 0x93, 0x41, 0x30, 0x35, 0x30, 0x0A, + 0x00, 0x72, 0x41, 0x30, 0x35, 0x30, 0x0A, 0x10, + 0x41, 0x30, 0x35, 0x30, 0x41, 0x30, 0x35, 0x39, + 0x63, 0x41, 0x30, 0x35, 0x30, 0x83, 0x88, 0x41, + 0x30, 0x35, 0x32, 0x62, 0x00, 0x75, 0x62, 0x75, + 0x63, 0xA1, 0x0B, 0x41, 0x30, 0x35, 0x37, 0x41, + 0x30, 0x34, 0x35, 0x0A, 0x01, 0xA1, 0x01, 0xA0, + 0x15, 0x93, 0x68, 0x0A, 0x06, 0x41, 0x30, 0x35, + 0x33, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0x80, 0x80, + 0x0A, 0x40, 0x00, 0x0A, 0x00, 0x5B, 0x01, 0x41, + 0x30, 0x36, 0x30, 0x00, 0x14, 0x4F, 0x07, 0x41, + 0x30, 0x33, 0x39, 0x02, 0x5B, 0x23, 0x41, 0x30, + 0x36, 0x30, 0xFF, 0xFF, 0x70, 0x41, 0x30, 0x36, + 0x31, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61, + 0x7D, 0x61, 0x0A, 0x02, 0x61, 0x41, 0x30, 0x36, + 0x32, 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61, + 0x7B, 0x61, 0x80, 0x79, 0x0A, 0x03, 0x0A, 0x03, + 0x00, 0x00, 0x61, 0x7D, 0x61, 0x79, 0x68, 0x0A, + 0x03, 0x00, 0x61, 0x7B, 0x80, 0x61, 0x00, 0x0A, + 0x04, 0x62, 0x7D, 0x7B, 0x61, 0x80, 0x0A, 0x04, + 0x00, 0x00, 0x62, 0x61, 0x41, 0x30, 0x36, 0x32, + 0x0A, 0x00, 0x0A, 0x60, 0x0A, 0xEA, 0x61, 0xA0, + 0x1E, 0x92, 0x93, 0x69, 0x0A, 0x00, 0xA2, 0x17, + 0x92, 0x93, 0x79, 0x61, 0x0A, 0x02, 0x00, 0x62, + 0x7B, 0x41, 0x30, 0x36, 0x31, 0x0A, 0x00, 0x0A, + 0x60, 0x0A, 0xEB, 0x0A, 0x01, 0x61, 0x5B, 0x27, + 0x41, 0x30, 0x36, 0x30, 0x14, 0x21, 0x41, 0x30, + 0x33, 0x34, 0x02, 0x70, 0x87, 0x68, 0x61, 0x70, + 0x0A, 0x00, 0x60, 0xA2, 0x12, 0x95, 0x60, 0x61, + 0x70, 0x83, 0x88, 0x83, 0x68, 0x60, 0x00, 0x88, + 0x83, 0x69, 0x60, 0x00, 0x75, 0x60, 0x14, 0x37, + 0x41, 0x30, 0x36, 0x33, 0x09, 0x70, 0x11, 0x04, + 0x0B, 0x00, 0x01, 0x67, 0x8B, 0x67, 0x0A, 0x00, + 0x41, 0x30, 0x32, 0x34, 0x8B, 0x67, 0x0A, 0x02, + 0x41, 0x30, 0x36, 0x34, 0x8C, 0x68, 0x0A, 0x02, + 0x41, 0x30, 0x36, 0x35, 0x70, 0x0A, 0x03, 0x41, + 0x30, 0x32, 0x34, 0x70, 0x41, 0x30, 0x36, 0x35, + 0x41, 0x30, 0x36, 0x34, 0xA4, 0x67, 0x14, 0x4A, + 0x07, 0x41, 0x30, 0x36, 0x36, 0x09, 0x70, 0x11, + 0x04, 0x0B, 0x00, 0x01, 0x67, 0x8B, 0x67, 0x0A, + 0x00, 0x41, 0x30, 0x32, 0x34, 0x8C, 0x67, 0x0A, + 0x02, 0x41, 0x30, 0x32, 0x35, 0x8C, 0x67, 0x0A, + 0x03, 0x41, 0x30, 0x36, 0x37, 0x8B, 0x68, 0x0A, + 0x02, 0x41, 0x30, 0x36, 0x38, 0x8C, 0x68, 0x0A, + 0x04, 0x41, 0x30, 0x36, 0x39, 0x74, 0x7A, 0x41, + 0x30, 0x36, 0x38, 0x0A, 0x03, 0x00, 0x0A, 0x02, + 0x61, 0xA0, 0x12, 0x93, 0x41, 0x30, 0x36, 0x39, + 0x0A, 0x01, 0x70, 0x41, 0x30, 0x37, 0x30, 0x61, + 0x41, 0x30, 0x36, 0x39, 0xA1, 0x0B, 0x70, 0x41, + 0x30, 0x37, 0x31, 0x61, 0x41, 0x30, 0x36, 0x39, + 0x70, 0x0A, 0x04, 0x41, 0x30, 0x32, 0x34, 0x70, + 0x0A, 0x00, 0x41, 0x30, 0x32, 0x35, 0x70, 0x41, + 0x30, 0x36, 0x39, 0x41, 0x30, 0x36, 0x37, 0xA4, + 0x67, 0x14, 0x49, 0x11, 0x41, 0x30, 0x37, 0x30, + 0x01, 0x08, 0x41, 0x30, 0x37, 0x32, 0x0A, 0x00, + 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x8C, + 0x67, 0x0A, 0x07, 0x41, 0x30, 0x37, 0x34, 0xA0, + 0x0C, 0x92, 0x93, 0x41, 0x30, 0x37, 0x34, 0x0A, + 0x01, 0xA4, 0x0A, 0x01, 0x8C, 0x67, 0x0A, 0x00, + 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A, 0x01, + 0x41, 0x30, 0x37, 0x36, 0x41, 0x30, 0x30, 0x35, + 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36, + 0x0A, 0x00, 0x8C, 0x67, 0x0A, 0x02, 0x41, 0x30, + 0x37, 0x37, 0x8C, 0x67, 0x0A, 0x03, 0x41, 0x30, + 0x37, 0x38, 0x41, 0x30, 0x37, 0x39, 0x68, 0x41, + 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36, 0x0A, + 0x00, 0x41, 0x30, 0x38, 0x30, 0x68, 0x0A, 0x00, + 0x70, 0x41, 0x30, 0x38, 0x31, 0x68, 0x61, 0xA0, + 0x4B, 0x09, 0x93, 0x61, 0x0A, 0x01, 0x70, 0x41, + 0x30, 0x38, 0x32, 0x68, 0x41, 0x30, 0x37, 0x32, + 0x74, 0x41, 0x30, 0x38, 0x33, 0x68, 0x0A, 0x01, + 0x41, 0x30, 0x38, 0x33, 0x68, 0x0A, 0x00, 0x62, + 0xA0, 0x47, 0x07, 0x92, 0x93, 0x62, 0x0A, 0x00, + 0xA0, 0x16, 0x92, 0x93, 0x41, 0x30, 0x37, 0x32, + 0x0A, 0x00, 0x72, 0x41, 0x30, 0x37, 0x37, 0x62, + 0x63, 0x70, 0x41, 0x30, 0x37, 0x38, 0x64, 0xA1, + 0x0E, 0x74, 0x41, 0x30, 0x37, 0x38, 0x62, 0x64, + 0x70, 0x41, 0x30, 0x37, 0x37, 0x63, 0x41, 0x30, + 0x37, 0x39, 0x68, 0x63, 0x64, 0x0A, 0x01, 0xA0, + 0x16, 0x94, 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, + 0x37, 0x36, 0x70, 0x41, 0x30, 0x37, 0x36, 0x63, + 0x70, 0x41, 0x30, 0x37, 0x35, 0x64, 0xA1, 0x0D, + 0x70, 0x41, 0x30, 0x37, 0x36, 0x64, 0x70, 0x41, + 0x30, 0x37, 0x35, 0x63, 0xA0, 0x0D, 0x92, 0x93, + 0x41, 0x30, 0x37, 0x32, 0x0A, 0x00, 0x72, 0x63, + 0x62, 0x63, 0xA1, 0x05, 0x74, 0x64, 0x62, 0x64, + 0x41, 0x30, 0x30, 0x35, 0x63, 0x64, 0x0A, 0x01, + 0xA4, 0x0A, 0x01, 0x41, 0x30, 0x37, 0x31, 0x68, + 0xA4, 0x0A, 0x00, 0x14, 0x4A, 0x06, 0x41, 0x30, + 0x37, 0x31, 0x01, 0x70, 0x41, 0x30, 0x37, 0x33, + 0x68, 0x67, 0x8C, 0x67, 0x0A, 0x07, 0x41, 0x30, + 0x37, 0x34, 0xA0, 0x0C, 0x92, 0x93, 0x41, 0x30, + 0x37, 0x34, 0x0A, 0x01, 0xA4, 0x0A, 0x00, 0x41, + 0x30, 0x38, 0x30, 0x68, 0x0A, 0x01, 0x8C, 0x67, + 0x0A, 0x02, 0x41, 0x30, 0x37, 0x37, 0x8C, 0x67, + 0x0A, 0x03, 0x41, 0x30, 0x37, 0x38, 0x41, 0x30, + 0x37, 0x39, 0x68, 0x41, 0x30, 0x37, 0x37, 0x41, + 0x30, 0x37, 0x38, 0x0A, 0x01, 0x8C, 0x67, 0x0A, + 0x00, 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A, + 0x01, 0x41, 0x30, 0x37, 0x36, 0x41, 0x30, 0x30, + 0x35, 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, + 0x36, 0x0A, 0x01, 0xA4, 0x0A, 0x00, 0x14, 0x41, + 0x04, 0x41, 0x30, 0x38, 0x32, 0x01, 0x70, 0x41, + 0x30, 0x37, 0x33, 0x68, 0x67, 0x8C, 0x67, 0x0A, + 0x00, 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A, + 0x01, 0x41, 0x30, 0x37, 0x36, 0x70, 0x0A, 0x00, + 0x60, 0xA0, 0x0E, 0x94, 0x41, 0x30, 0x37, 0x35, + 0x41, 0x30, 0x37, 0x36, 0x70, 0x0A, 0x01, 0x60, + 0x7B, 0x41, 0x30, 0x35, 0x38, 0x68, 0x0A, 0x50, + 0x0A, 0x01, 0x61, 0xA4, 0x7F, 0x60, 0x61, 0x00, + 0x14, 0x43, 0x04, 0x41, 0x30, 0x38, 0x30, 0x02, + 0x70, 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x8C, + 0x67, 0x0A, 0x04, 0x41, 0x30, 0x38, 0x34, 0x8B, + 0x67, 0x0A, 0x05, 0x41, 0x30, 0x38, 0x35, 0x41, + 0x30, 0x35, 0x33, 0x0A, 0x00, 0x0A, 0xE0, 0x7D, + 0x79, 0x41, 0x30, 0x38, 0x35, 0x0A, 0x10, 0x00, + 0x72, 0x0B, 0x00, 0x08, 0x77, 0x0B, 0x00, 0x01, + 0x41, 0x30, 0x38, 0x34, 0x00, 0x00, 0x00, 0x80, + 0x0A, 0x01, 0x00, 0x69, 0x14, 0x38, 0x41, 0x30, + 0x38, 0x31, 0x01, 0x70, 0x0A, 0x00, 0x60, 0x70, + 0x0A, 0x00, 0x67, 0xA2, 0x27, 0x95, 0x60, 0x0B, + 0x40, 0x01, 0x7B, 0x41, 0x30, 0x35, 0x38, 0x68, + 0x0A, 0xA5, 0x0A, 0x3F, 0x61, 0xA0, 0x0F, 0x93, + 0x61, 0x0A, 0x10, 0x70, 0x0A, 0x01, 0x67, 0x70, + 0x0B, 0x40, 0x01, 0x60, 0xA5, 0x5B, 0x21, 0x0A, + 0xFA, 0x75, 0x60, 0xA4, 0x67, 0x14, 0x4B, 0x06, + 0x41, 0x30, 0x38, 0x33, 0x02, 0xA0, 0x25, 0x93, + 0x68, 0x0A, 0x00, 0x7B, 0x7A, 0x41, 0x30, 0x35, + 0x38, 0x68, 0x0A, 0xA2, 0x0A, 0x04, 0x00, 0x0A, + 0x07, 0x60, 0x70, 0x83, 0x88, 0x11, 0x0A, 0x0A, + 0x07, 0x00, 0x01, 0x02, 0x04, 0x08, 0x0C, 0x10, + 0x60, 0x00, 0x61, 0xA1, 0x3B, 0x70, 0x41, 0x30, + 0x37, 0x33, 0x68, 0x67, 0x8C, 0x67, 0x0A, 0x00, + 0x41, 0x30, 0x37, 0x35, 0x8C, 0x67, 0x0A, 0x01, + 0x41, 0x30, 0x37, 0x36, 0xA0, 0x14, 0x94, 0x41, + 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36, 0x74, + 0x41, 0x30, 0x37, 0x35, 0x41, 0x30, 0x37, 0x36, + 0x61, 0xA1, 0x0B, 0x74, 0x41, 0x30, 0x37, 0x36, + 0x41, 0x30, 0x37, 0x35, 0x61, 0x75, 0x61, 0xA4, + 0x61, 0x14, 0x4E, 0x0A, 0x41, 0x30, 0x37, 0x39, + 0x04, 0x08, 0x41, 0x30, 0x37, 0x37, 0x0A, 0x00, + 0x08, 0x41, 0x30, 0x37, 0x38, 0x0A, 0x00, 0x70, + 0x41, 0x30, 0x37, 0x33, 0x68, 0x67, 0x70, 0x69, + 0x41, 0x30, 0x37, 0x37, 0x70, 0x6A, 0x41, 0x30, + 0x37, 0x38, 0x8B, 0x67, 0x0A, 0x05, 0x41, 0x30, + 0x38, 0x35, 0xA0, 0x1A, 0x94, 0x41, 0x30, 0x37, + 0x37, 0x41, 0x30, 0x37, 0x38, 0x74, 0x41, 0x30, + 0x37, 0x37, 0x41, 0x30, 0x37, 0x38, 0x61, 0x70, + 0x41, 0x30, 0x37, 0x38, 0x62, 0xA1, 0x11, 0x74, + 0x41, 0x30, 0x37, 0x38, 0x41, 0x30, 0x37, 0x37, + 0x61, 0x70, 0x41, 0x30, 0x37, 0x37, 0x62, 0x79, + 0x74, 0x79, 0x0A, 0x01, 0x72, 0x61, 0x0A, 0x01, + 0x00, 0x00, 0x0A, 0x01, 0x00, 0x62, 0x61, 0xA0, + 0x20, 0x93, 0x6B, 0x0A, 0x00, 0x41, 0x30, 0x35, + 0x33, 0x0A, 0x00, 0x0A, 0xE0, 0x7D, 0x79, 0x41, + 0x30, 0x38, 0x35, 0x0A, 0x10, 0x00, 0x0B, 0x23, + 0x80, 0x00, 0x0C, 0xFF, 0xFF, 0xFF, 0xFF, 0x61, + 0xA1, 0x1B, 0x41, 0x30, 0x35, 0x33, 0x0A, 0x00, + 0x0A, 0xE0, 0x7D, 0x79, 0x41, 0x30, 0x38, 0x35, + 0x0A, 0x10, 0x00, 0x0B, 0x23, 0x80, 0x00, 0x80, + 0x61, 0x00, 0x0A, 0x00, 0x5B, 0x21, 0x0A, 0x0A, + 0x14, 0x4B, 0x05, 0x41, 0x30, 0x30, 0x32, 0x02, + 0x70, 0x41, 0x30, 0x30, 0x33, 0x0B, 0x90, 0x84, + 0x60, 0xA0, 0x4A, 0x04, 0x92, 0x93, 0x7B, 0x60, + 0x0A, 0xF0, 0x00, 0x0A, 0x00, 0xA0, 0x12, 0x93, + 0x68, 0x0A, 0x02, 0x7B, 0x60, 0x0C, 0xA0, 0xFF, + 0xFF, 0xFF, 0x60, 0x7D, 0x60, 0x0A, 0xA0, 0x60, + 0xA1, 0x23, 0xA0, 0x12, 0x93, 0x69, 0x0A, 0x00, + 0x7B, 0x60, 0x0C, 0x60, 0xFF, 0xFF, 0xFF, 0x60, + 0x7D, 0x60, 0x0A, 0x60, 0x60, 0xA1, 0x0E, 0x7B, + 0x60, 0x0C, 0x20, 0xFF, 0xFF, 0xFF, 0x60, 0x7D, + 0x60, 0x0A, 0x20, 0x60, 0x41, 0x30, 0x30, 0x34, + 0x0B, 0x90, 0x84, 0x60, 0x14, 0x06, 0x41, 0x30, + 0x30, 0x35, 0x03, 0x14, 0x06, 0x41, 0x30, 0x30, + 0x36, 0x01 +}; + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c new file mode 100644 index 0000000000..c64fc4bd72 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c @@ -0,0 +1,125 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe configuration data services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "OntarioDefinitions.h" +#include "OntarioComplexData.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXCONFIG_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get total number of silicons/wrappers/engines for this complex + * + * + * @param[in] SocketId Socket ID. + * @param[out] Length Length of configuration info block + * @retval AGESA_SUCCESS Configuration data length is correct + */ +AGESA_STATUS +PcieFmGetComplexDataLength ( + IN UINT32 SocketId, + OUT UINTN *Length + ) +{ + *Length = sizeof (ComplexData); + return AGESA_SUCCESS; +} + + + + +/*----------------------------------------------------------------------------------------*/ +/** + * Build configuration + * + * + * + * + * @param[out] Buffer Pointer to buffer to build internal complex data structure + * @param[out] StdHeader Standard configuration header. + * @retval AGESA_SUCCESS Configuration data build successfully + */ +AGESA_STATUS +PcieFmBuildComplexConfiguration ( + OUT VOID *Buffer, + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + + LibAmdMemCopy (Buffer, &ComplexData, sizeof (ComplexData), StdHeader); + PcieRebaseConfigurationData ((PCIe_SILICON_CONFIG *) Buffer, 0, (UINTN)Buffer); + + return AGESA_SUCCESS; +} + + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c new file mode 100644 index 0000000000..2e789aa4c9 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c @@ -0,0 +1,243 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe complex initialization services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "OntarioDefinitions.h" +#include "GnbRegistersON.h" +#include "NbSmuLib.h" +#include "Filecode.h" +#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIECOMPLEXSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Control port visability + * + * + * @param[in] Control Hide/Unhide + * @param[in] Silicon Pointer to silicon configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieFmPortVisabilityControl ( + IN PCIE_PORT_VISIBILITY Control, + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + switch (Control) { + case UnhidePorts: + PcieSiliconUnHidePorts (Silicon, Pcie); + break; + case HidePorts: + PcieSiliconHidePorts (Silicon, Pcie); + break; + default: + ASSERT (FALSE); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Request boot up voltage + * + * + * + * @param[in] LinkCap Global GEN capability + * @param[in] Pcie Pointer to PCIe configuration data area + */ +VOID +PcieFmSetBootUpVoltage ( + IN PCIE_LINK_SPEED_CAP LinkCap, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + FCRxFE00_70A2_STRUCT FCRxFE00_70A2; + D18F3x15C_STRUCT D18F3x15C; + UINT8 TargetVidIndex; + UINT32 Temp; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Enter\n"); + ASSERT (LinkCap <= PcieGen2); + GnbLibPciRead ( + MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), + AccessWidth32, + &D18F3x15C.Value, + GnbLibGetHeader (Pcie) + ); + Temp = D18F3x15C.Value; + if (LinkCap > PcieGen1) { + FCRxFE00_70A2.Value = NbSmuReadEfuse (FCRxFE00_70A2_ADDRESS, GnbLibGetHeader (Pcie)); + TargetVidIndex = (UINT8) FCRxFE00_70A2.Field.PcieGen2Vid; + } else { + TargetVidIndex = PcieSiliconGetGen1VoltageIndex (GnbLibGetHeader (Pcie)); + } + IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid Index %d\n", LinkCap, TargetVidIndex); + if (TargetVidIndex == 3) { + D18F3x15C.Field.SclkVidLevel2 = D18F3x15C.Field.SclkVidLevel3; + GnbLibPciWrite ( + MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), + AccessWidth32, + &D18F3x15C.Value, + GnbLibGetHeader (Pcie) + ); + PcieSiliconRequestVoltage (2, GnbLibGetHeader (Pcie)); + } + GnbLibPciWrite ( + MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), + AccessWidth32, + &Temp, + GnbLibGetHeader (Pcie) + ); + PcieSiliconRequestVoltage (TargetVidIndex, GnbLibGetHeader (Pcie)); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmSetBootUpVoltage Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Map engine to specific PCI device address + * + * + * + * @param[in] Engine Pointer to engine configuration + * @param[in] Pcie Pointer to PCIe configuration + * @retval AGESA_ERROR Fail to map PCI device address + * @retval AGESA_SUCCESS Successfully allocate PCI address + */ + +AGESA_STATUS +PcieFmMapPortPciAddress ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_WRAPPER_CONFIG *Wrapper; + UINT64 ConfigurationSignature; + + Wrapper = PcieEngineGetParentWrapper (Engine); + + if (Wrapper->WrapId == GPP_WRAP_ID) { + ConfigurationSignature = PcieConfigGetConfigurationSignature (Wrapper, Engine->Type.Port.CoreId); + if ((ConfigurationSignature == GPP_CORE_x4x2x1x1_ST) || (ConfigurationSignature == GPP_CORE_x4x2x2_ST)) { + //Enable device remapping + GnbLibPciIndirectRMW ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + 0x20 | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + ~(UINT32) (1 << 1), + 0x0, + GnbLibGetHeader (Pcie) + ); + } + } + if (Engine->Type.Port.PortData.DeviceNumber == 0 && Engine->Type.Port.PortData.FunctionNumber == 0) { + Engine->Type.Port.PortData.DeviceNumber = Engine->Type.Port.NativeDevNumber; + Engine->Type.Port.PortData.FunctionNumber = Engine->Type.Port.NativeFunNumber; + return AGESA_SUCCESS; + } + if (Engine->Type.Port.PortData.DeviceNumber == Engine->Type.Port.NativeDevNumber && + Engine->Type.Port.PortData.FunctionNumber == Engine->Type.Port.NativeFunNumber) { + return AGESA_SUCCESS; + } + return AGESA_ERROR; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Map engine to specific PCI device address + * + * + * + * @param[in] Engine Pointer to engine configuration + * @param[in] Pcie Pointer to PCIe configuration + */ + + +VOID +PcieFmEnableSlotPowerLimit ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + if (PcieLibIsEngineAllocated (Engine) && Engine->Type.Port.PortData.PortPresent != PortDisabled && !Engine->Type.Port.IsSB) { + IDS_HDT_CONSOLE (PCIE_MISC, " Enable Slot Power Limit for Port % d\n", Engine->Type.Port.Address.Address.Device); + GnbLibPciIndirectRMW ( + MAKE_SBDFO (0, 0, 0, 0, D0F0x60_ADDRESS), + (D0F0x64_x55_ADDRESS + (Engine->Type.Port.Address.Address.Device - 4) * 2) | IOC_WRITE_ENABLE, + AccessS3SaveWidth32, + 0xffffffff, + 1 << D0F0x64_x55_SetPowEn_OFFSET, + GnbLibGetHeader (Pcie) + ); + } +} + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c new file mode 100644 index 0000000000..cb35a59133 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c @@ -0,0 +1,167 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe PHY initialization services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbRegistersON.h" +#include "OntarioDefinitions.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPHYSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * PHY Pll Personality Init + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +PcieFmPhyLetPllPersonalityInit ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + // Stub function + return AGESA_SUCCESS; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Port channel characteristic + * + * + * + * @param[in] Engine Pointer to engine configuration + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieFmPhyChannelCharacteristic ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Point "virtual" PLL clock picker away from PCIe + * + * + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieFmAvertClockPickers ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + // Stub function +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PHY lane ganging + * + * + * + * @param[out] Wrapper Pointer to internal configuration data area + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieFmPhyApplyGanging ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + // Stub function +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Program receiver detection power mode + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PcieFmPifSetRxDetectPowerMode ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + // Stub function +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c new file mode 100644 index 0000000000..31ef7c8980 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c @@ -0,0 +1,120 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe PHY initialization services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 40760 $ @e \$Date: 2010-10-27 08:55:23 +0800 (Wed, 27 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#include "GnbRegistersON.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEPIFSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Set PLL mode for L1 + * + * + * @param[in] LaneBitmap Power down PLL for these lanes + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + */ +VOID +PcieFmPifSetPllModeForL1 ( + IN UINT32 LaneBitmap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 ActiveLaneBitmap; + ActiveLaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_PCIE_HOTPLUG, 0, Wrapper, Pcie); + // This limits PLL setting to be identical for all PLL on wrapper. + if ((ActiveLaneBitmap & LaneBitmap) == ActiveLaneBitmap) { + LaneBitmap &= PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_ALL, 0, Wrapper, Pcie); + PciePifSetPllModeForL1 (LaneBitmap, Wrapper, Pcie); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PLL power up latency + * + * + * @param[in] Wrapper Pointer to Wrapper config descriptor + * @param[in] Pcie Pointer to PICe configuration data area + * @retval Pll wake up latency in us + */ +UINT8 +PcieFmPifGetPllPowerUpLatency ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + return 30; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c new file mode 100644 index 0000000000..88290b19cc --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c @@ -0,0 +1,631 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe wrapper configuration services + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "PcieFamilyServices.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#include "PcieMiscLib.h" +#include "OntarioDefinitions.h" +#include "GnbRegistersON.h" +#include "NbSmuLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_FAMILY_0X14_F14PCIEWRAPPERSERVICES_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +extern BUILD_OPT_CFG UserOptions; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +AGESA_STATUS +STATIC +PcieOnConfigureGppEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ); + +AGESA_STATUS +STATIC +PcieOnConfigureDdiEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ); + +VOID +PcieFmExecuteNativeGen1Reconfig ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +/*---------------------------------------------------------------------------------------- + * T A B L E S + *---------------------------------------------------------------------------------------- + */ +PCIE_HOST_REGISTER_ENTRY PcieInitTable [] = { + { + WRAP_SPACE (0, D0F0xE4_WRAP_8016_ADDRESS), + D0F0xE4_WRAP_8016_CalibAckLatency_MASK, + 0 + }, + { + PHY_SPACE (0, 0, D0F0xE4_PHY_4004_ADDRESS), + D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_MASK | D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_MASK, + (0x1 << D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdVal_OFFSET) | (0x1 << D0F0xE4_PHY_4004_PllBiasGenPdnbOvrdEn_OFFSET) + }, + { + D0F0xE4_x0108_8071_ADDRESS, + D0F0xE4_x0108_8071_RxAdjust_MASK, + 0x3 << D0F0xE4_x0108_8071_RxAdjust_OFFSET + }, + { + D0F0xE4_x0108_8072_ADDRESS, + D0F0xE4_x0108_8072_TxAdjust_MASK, + 0x3 << D0F0xE4_x0108_8072_TxAdjust_OFFSET + }, +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] EngineType Engine Type + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_UNSUPPORTED No more configuration available for given engine type + * @retval AGESA_ERROR Requested configuration not supported + */ +AGESA_STATUS +PcieFmConfigureEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIE_ENGINE_TYPE EngineType, + IN UINT8 ConfigurationId + ) +{ + AGESA_STATUS Status; + Status = AGESA_ERROR; + switch (Wrapper->WrapId) { + case GPP_WRAP_ID: + if (EngineType != PciePortEngine) { + return AGESA_UNSUPPORTED; + } + Status = PcieOnConfigureGppEnginesLaneAllocation (Wrapper, ConfigurationId); + break; + case DDI_WRAP_ID: + if (EngineType != PcieDdiEngine) { + return AGESA_UNSUPPORTED; + } + Status = PcieOnConfigureDdiEnginesLaneAllocation (Wrapper, ConfigurationId); + break; + default: + ASSERT (FALSE); + + } + return Status; +} + +CONST UINT8 GppLaneConfigurationTable [][NUMBER_OF_GPP_PORTS * 2] = { +//4 5 6 7 8 (SB) + 4, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3, + 4, 5, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3, + 4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3, + 4, 5, 6, 6, 7, 7, UNUSED_LANE_ID, UNUSED_LANE_ID, 0, 3, + 4, 5, UNUSED_LANE_ID, UNUSED_LANE_ID, 6, 6, 7, 7, 0, 3, + 4, 4, 5, 5, 6, 6, 7, 7, 0, 3 +}; + +CONST UINT8 GppPortIdConfigurationTable [][NUMBER_OF_GPP_PORTS] = { +//4 5 6 7 8 (SB) + 1, 2, 3, 4, 0, + 1, 2, 3, 4, 0, + 1, 3, 2, 4, 0, + 1, 2, 3, 4, 0, + 1, 4, 2, 3, 0, + 1, 2, 3, 4, 0 +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure GFX engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ + + +AGESA_STATUS +STATIC +PcieOnConfigureGppEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ) +{ + PCIe_ENGINE_CONFIG *EnginesList; + UINTN CoreLaneIndex; + UINTN PortIdIndex; + if (ConfigurationId > ((sizeof (GppLaneConfigurationTable) / (NUMBER_OF_GPP_PORTS * 2)) - 1)) { + return AGESA_ERROR; + } + EnginesList = PcieWrapperGetEngineList (Wrapper); + CoreLaneIndex = 0; + PortIdIndex = 0; + do { + EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED; + EnginesList->Type.Port.PortId = GppPortIdConfigurationTable [ConfigurationId][PortIdIndex++]; + EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; + EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++]; + + } while (IS_LAST_DESCRIPTOR (EnginesList++)); + return AGESA_SUCCESS; +} + + +CONST UINT8 DdiLaneConfigurationTable [][NUMBER_OF_DDIS * 2] = { + 0, 3, 4, 7, 8, 11 +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure DDI engine list to support lane allocation according to configuration ID. + * + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] ConfigurationId Configuration ID + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported + */ + + +AGESA_STATUS +STATIC +PcieOnConfigureDdiEnginesLaneAllocation ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationId + ) +{ + PCIe_ENGINE_CONFIG *EnginesList; + UINTN LaneIndex; + EnginesList = PcieWrapperGetEngineList (Wrapper); + if (ConfigurationId > ((sizeof (DdiLaneConfigurationTable) / (NUMBER_OF_DDIS * 2)) - 1)) { + return AGESA_ERROR; + } + LaneIndex = 0; + do { + EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED; + EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + + Wrapper->StartPhyLane; + EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] + + Wrapper->StartPhyLane; + } while (IS_LAST_DESCRIPTOR (EnginesList++)); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Configure clock to run out of the wrapper at specific speed + * + * + * @param[in] LinkSpeedCapability Link Speed capability + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieFmConfigureClock ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Get configuration Value for GPP wrapper + * + * + * + * @param[in] ConfigurationSignature Configuration signature + * @param[out] ConfigurationValue Configuration value + * @retval AGESA_SUCCESS Correct core configuration value returned by in *ConfigurationValue + * @retval AGESA_ERROR ConfigurationSignature is incorrect + */ +AGESA_STATUS +PcieOnGetGppConfigurationValue ( + IN UINT64 ConfigurationSignature, + OUT UINT8 *ConfigurationValue + ) +{ + switch (ConfigurationSignature) { + case GPP_CORE_x4x1x1x1x1: + *ConfigurationValue = 0x4; + break; + case GPP_CORE_x4x2x1x1: + case GPP_CORE_x4x2x1x1_ST: + //Configuration 2:1:1 - Device Numbers 4:5:6 + //Configuration 2:1:1 - Device Numbers 4:6:7 + *ConfigurationValue = 0x3; + break; + case GPP_CORE_x4x2x2: + case GPP_CORE_x4x2x2_ST: + //Configuration 2:2 - Device Numbers 4:5 + //Configuration 2:2 - Device Numbers 4:6 + *ConfigurationValue = 0x2; + break; + case GPP_CORE_x4x4: + *ConfigurationValue = 0x1; + break; + default: + ASSERT (FALSE); + return AGESA_ERROR; + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration value + * + * + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] CoreId Core ID + * @param[in] ConfigurationSignature Configuration signature + * @param[out] ConfigurationValue Configuration value (for core configuration) + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Core configuration value can not be determined + */ +AGESA_STATUS +PcieFmGetCoreConfigurationValue ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 CoreId, + IN UINT64 ConfigurationSignature, + IN UINT8 *ConfigurationValue + ) +{ + AGESA_STATUS Status; + + if (Wrapper->WrapId == GPP_WRAP_ID) { + Status = PcieOnGetGppConfigurationValue (ConfigurationSignature, ConfigurationValue); + } else { + Status = AGESA_ERROR; + } + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get max link speed capability supported by this port + * + * + * + * @param[in] Flags See Flags PCIE_PORT_GEN_CAP_BOOT / PCIE_PORT_GEN_CAP_MAX + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * @retval PcieGen1/PcieGen2 Max supported link gen capability + */ +PCIE_LINK_SPEED_CAP +PcieFmGetLinkSpeedCap ( + IN UINT32 Flags, + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + ASSERT (Engine->Type.Port.PortData.LinkSpeedCapability < MaxPcieGen); + LinkSpeedCapability = PcieGen2; + if (Engine->Type.Port.PortData.LinkSpeedCapability == PcieGenMaxSupported) { + Engine->Type.Port.PortData.LinkSpeedCapability = (UINT8) LinkSpeedCapability; + } + if (Pcie->PsppPolicy == PsppPowerSaving) { + LinkSpeedCapability = PcieGen1; + } + if (Engine->Type.Port.PortData.LinkSpeedCapability < LinkSpeedCapability) { + LinkSpeedCapability = Engine->Type.Port.PortData.LinkSpeedCapability; + } + if ((Flags & PCIE_PORT_GEN_CAP_BOOT) != 0) { + if (Pcie->PsppPolicy == PsppBalanceLow) { + LinkSpeedCapability = PcieGen1; + } + } + return LinkSpeedCapability; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Various initialization needed prior topology and configuration initialization + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +VOID +PcieFmPreInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Index; + PCIe_SILICON_CONFIG *Silicon; + PCIE_LINK_SPEED_CAP GlobalCapability; + F14_PCIe_WRAPPER_CONFIG *F14PcieWrapper; + + Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]); + F14PcieWrapper = &((F14_COMPLEX_CONFIG*) Silicon)->FmGppWrapper ; + GlobalCapability = PcieUtilGlobalGenCapability ( + PCIE_PORT_GEN_CAP_MAX | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, + Pcie + ); + if ((GlobalCapability == PcieGen1) && (F14PcieWrapper->NativeGen1Support == TRUE)) { + PcieFmExecuteNativeGen1Reconfig (Pcie); + } + Silicon = PcieComplexGetSiliconList (&Pcie->ComplexList[0]); + for (Index = 0; Index < (sizeof (PcieInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY)); Index++) { + PcieSiliconRegisterRMW ( + Silicon, + PcieInitTable[Index].Reg, + PcieInitTable[Index].Mask, + PcieInitTable[Index].Data, + FALSE, + Pcie + ); + } + + // Set PCIe SSID. + PcieSiliconRegisterRMW ( + Silicon, + WRAP_SPACE (0, D0F0xE4_WRAP_8002_ADDRESS), + D0F0xE4_WRAP_8002_SubsystemVendorID_MASK | D0F0xE4_WRAP_8002_SubsystemID_MASK, + UserOptions.CfgGnbPcieSSID, + FALSE, + Pcie + ); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if engine can be remapped to Device/function number requested by user + * defined engine descriptor + * + * Function only called if requested device/function does not much native device/function + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Descriptor can be mapped to engine + * @retval FALSE Descriptor can NOT be mapped to engine + */ + +BOOLEAN +PcieFmCheckPortPciDeviceMapping ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + return FALSE; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get core configuration string + * + * Debug function for logging configuration + * + * @param[in] Wrapper Pointer to internal configuration data area + * @param[in] ConfigurationValue Configuration value + * @retval Configuration string + */ + +CONST CHAR8* +PcieFmDebugGetCoreConfigurationString ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN UINT8 ConfigurationValue + ) +{ + switch (ConfigurationValue) { + case 4: + return "1x4, 4x1"; + case 3: + return "1x4, 1x2, 2x1"; + case 2: + return "1x4, 2x2"; + case 1: + return "1x4, 1x4"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get wrapper name + * + * Debug function for logging wrapper name + * + * @param[in] Wrapper Pointer to internal configuration data area + * @retval Wrapper Name string + */ + +CONST CHAR8* +PcieFmDebugGetWrapperNameString ( + IN PCIe_WRAPPER_CONFIG *Wrapper + ) +{ + switch (Wrapper->WrapId) { + case GPP_WRAP_ID: + return "GPPSB"; + case DDI_WRAP_ID: + return "Virtual DDI"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Get register address name + * + * Debug function for logging register trace + * + * @param[in] AddressFrame Address Frame + * @retval Register address name + */ +CONST CHAR8* +PcieFmDebugGetHostRegAddressSpaceString ( + IN UINT16 AddressFrame + ) +{ + switch (AddressFrame) { + case 0x130: + return "GPP WRAP"; + case 0x110: + return "GPP PIF0"; + case 0x120: + return "GPP PHY0"; + case 0x101: + return "GPP CORE"; + default: + break; + } + return " !!! Something Wrong !!!"; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Execute/clean up reconfiguration for Gen 1 native mode + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieFmExecuteNativeGen1Reconfig ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmExecuteNativeGen1Reconfig Enter\n"); + NbSmuServiceRequest (19, FALSE, GnbLibGetHeader (Pcie)); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmExecuteNativeGen1Reconfig Enter\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Check if the lane can be muxed by link width requested by user + * defined engine descriptor + * + * Check Engine StartCoreLane could be aligned by user requested link width(x1, x2, x4, x8, x16). + * Check Engine StartCoreLane could be aligned by user requested link width x2. + * + * @param[in] PortDescriptor Pointer to user defined engine descriptor + * @param[in] Engine Pointer engine configuration + * @retval TRUE Lane can be muxed + * @retval FALSE LAne can NOT be muxed + */ + +BOOLEAN +PcieFmCheckPortPcieLaneCanBeMuxed ( + IN PCIe_PORT_DESCRIPTOR *PortDescriptor, + IN PCIe_ENGINE_CONFIG *Engine + ) +{ + UINT16 DescriptorHiLane; + UINT16 DescriptorLoLane; + UINT16 DescriptorNumberOfLanes; + PCIe_WRAPPER_CONFIG *Wrapper; + UINT16 NormalizedLoPhyLane; + BOOLEAN Result; + + Result = FALSE; + Wrapper = (PCIe_WRAPPER_CONFIG *)Engine->Wrapper; + DescriptorLoLane = MIN (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); + DescriptorHiLane = MAX (PortDescriptor->EngineData.StartLane, PortDescriptor->EngineData.EndLane); + DescriptorNumberOfLanes = DescriptorHiLane - DescriptorLoLane + 1; + + NormalizedLoPhyLane = DescriptorLoLane - Wrapper->StartPhyLane; + + if (NormalizedLoPhyLane == Engine->Type.Port.StartCoreLane) { + Result = TRUE; + } else { + if (((Engine->Type.Port.StartCoreLane % 2) == 0) || (Engine->Type.Port.StartCoreLane == 0)) { + if (NormalizedLoPhyLane == 0) { + Result = TRUE; + } else { + if (((NormalizedLoPhyLane % 2) == 0) && ((NormalizedLoPhyLane % DescriptorNumberOfLanes) == 0)) { + Result = TRUE; + } + } + } + } + + return Result; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h new file mode 100644 index 0000000000..b9f9a04d0f --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/OntarioComplexData.h @@ -0,0 +1,241 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe configuration data definition + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 37710 $ @e \$Date: 2010-09-10 11:08:20 +0800 (Fri, 10 Sep 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +#ifndef _ONTARIOCOMPLEXDATA_H_ +#define _ONTARIOCOMPLEXDATA_H_ + +STATIC +F14_COMPLEX_CONFIG ComplexData = { + //Silicon + { + DESCRIPTOR_TERMINATE_LIST, + {0}, + offsetof (F14_COMPLEX_CONFIG, GppWrapper), + NULL + }, + //Gpp Wrapper + { + DESCRIPTOR_PCIE_WRAPPER, + GPP_WRAP_ID, + GPP_NUMBER_OF_PIFs, + GPP_START_PHY_LANE, + GPP_END_PHY_LANE, + GPP_CORE_ID, + GPP_CORE_ID, + { + 1, //PowerOffUnusedLanesEnabled, + 1, //PowerOffUnusedPllsEnabled + 1, //ClkGating + 1, //LclkGating + 1, //TxclkGatingPllPowerDown + 1 //PllOffInL1 + }, + offsetof (F14_COMPLEX_CONFIG, Port4), + offsetof (F14_COMPLEX_CONFIG, Silicon), + offsetof (F14_COMPLEX_CONFIG, FmGppWrapper) + }, + //Virtual DDI Wrapper + { + DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_VIRTUAL | DESCRIPTOR_TERMINATE_LIST, + DDI_WRAP_ID, + 0, + DDI_START_PHY_LANE, + DDI_END_PHY_LANE, + 0xff, + 0x0, + { + 1, //PowerOffUnusedLanesEnabled, + 1, //PowerOffUnusedPllsEnabled + 1, //ClkGating + 1, //LclkGating + 1, //TxclkGatingPllPowerDown + 0 //PllOffInL1 + }, + offsetof (F14_COMPLEX_CONFIG, Dpa), + offsetof (F14_COMPLEX_CONFIG, Silicon), + NULL + }, + //Port 4 + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (F14_COMPLEX_CONFIG, GppWrapper), + { PciePortEngine, 4, 4}, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 4, + 4, + 4, + 0, + GPP_CORE_ID, + 1, + 0, + FALSE, + LinkStateResetExit + }, + }, + }, + //Port 5 + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (F14_COMPLEX_CONFIG, GppWrapper), + { PciePortEngine, 5, 5}, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 5, + 5, + 5, + 0, + GPP_CORE_ID, + 2, + 0, + FALSE, + LinkStateResetExit + }, + }, + }, + //Port 6 + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (F14_COMPLEX_CONFIG, GppWrapper), + { PciePortEngine, 6, 6 }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 6, + 6, + 6, + 0, + GPP_CORE_ID, + 3, + 0, + FALSE, + LinkStateResetExit + }, + }, + }, + //Port 7 + { + DESCRIPTOR_PCIE_ENGINE, + offsetof (F14_COMPLEX_CONFIG, GppWrapper), + { PciePortEngine, 7, 7 }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {0}, + 7, + 7, + 7, + 0, + GPP_CORE_ID, + 4, + 0, + FALSE, + LinkStateResetExit + }, + }, + }, + //Port 8 + { + DESCRIPTOR_PCIE_ENGINE | DESCRIPTOR_TERMINATE_LIST, + offsetof (F14_COMPLEX_CONFIG, GppWrapper), + { PciePortEngine, 0, 3 }, + 0, //Initialization Status + 0xFF, //Scratch + { + { + {PortEnabled, 0, 8, 0, PcieGenMaxSupported, AspmL0sL1, HotplugDisabled, 0x0, {0}}, + 0, + 3, + 8, + 0, + GPP_CORE_ID, + 0, + MAKE_SBDFO (0, 0, 8, 0, 0), + TRUE, + LinkStateTrainingSuccess + }, + }, + }, + //Virtual DpA + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL, + offsetof (F14_COMPLEX_CONFIG, DdiWrapper), + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF, //Scratch + }, + //Virtual DpB + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL, + offsetof (F14_COMPLEX_CONFIG, DdiWrapper), + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF, //Scratch + }, + //Virtual VGA + { + DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_VIRTUAL | DESCRIPTOR_TERMINATE_LIST, + offsetof (F14_COMPLEX_CONFIG, DdiWrapper), + {PcieDdiEngine}, + 0, //Initialization Status + 0xFF, //Scratch + }, + //Native Gen Support + //Set to TRUE after bringup + { + TRUE, + } + +}; +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/OntarioDefinitions.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/OntarioDefinitions.h new file mode 100644 index 0000000000..dd78ce9ea6 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/0x14/OntarioDefinitions.h @@ -0,0 +1,102 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Family specific PCIe definitions + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 35664 $ @e \$Date: 2010-07-28 20:02:15 +0800 (Wed, 28 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +#ifndef _LLANODEFINITIONS_H_ +#define _LLANODEFINITIONS_H_ + +#define SOCKET_ID 0 + +#define MAX_NUM_PHYs 2 +#define MAX_NUM_LANE_PER_PHY 8 + + +#define NUMBER_OF_GPP_PORTS 5 +#define NUMBER_OF_DDIS 3 +#define NUMBER_OF_WRAPPERS 2 +#define NUMBER_OF_SILICONS 1 + +#define GPP_WRAP_ID 0 +#define GPP_NUMBER_OF_PIFs 1 +#define GPP_START_PHY_LANE 0 +#define GPP_END_PHY_LANE 7 +#define GPP_CORE_ID 1 + +#define GPP_CORE_x4x1x1x1x1 ((1ull << 32) | (1ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x1x1 ((2ull << 32) | (1ull << 24) | (1ull << 16) | (0ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x1x1_ST ((2ull << 32) | (0ull << 24) | (1ull << 16) | (1ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x2 ((2ull << 32) | (2ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x2x2_ST ((2ull << 32) | (0ull << 24) | (2ull << 16) | (0ull << 8) | (4ull << 0)) +#define GPP_CORE_x4x4 ((4ull << 32) | (0ull << 24) | (0ull << 16) | (0ull << 8) | (4ull << 0)) + +#define DDI_WRAP_ID 2 +#define DDI_NUMBER_OF_PIFs 1 +#define DDI_START_PHY_LANE 8 +#define DDI_END_PHY_LANE 19 + + + +/// F14 PCIe Wrapper Configuration +typedef struct { + BOOLEAN NativeGen1Support; ///< Native Gen1 support +} F14_PCIe_WRAPPER_CONFIG; + + +/// Complex Configuration +typedef struct { + PCIe_SILICON_CONFIG Silicon; ///< Silicon + PCIe_WRAPPER_CONFIG GppWrapper; ///< GPP Wrapper + PCIe_WRAPPER_CONFIG DdiWrapper; ///< Virtual DDI Wrapper + PCIe_ENGINE_CONFIG Port4; ///< Port 4 + PCIe_ENGINE_CONFIG Port5; ///< Port 5 + PCIe_ENGINE_CONFIG Port6; ///< Port 6 + PCIe_ENGINE_CONFIG Port7; ///< Port 7 + PCIe_ENGINE_CONFIG Port8; ///< Port 8 + PCIe_ENGINE_CONFIG Dpa; ///< Virtual DPA + PCIe_ENGINE_CONFIG Dpb; ///< Virtual DPB + PCIe_ENGINE_CONFIG Vga; ///< Virtual VGA + F14_PCIe_WRAPPER_CONFIG FmGppWrapper; ///< F14 Pcie Wrapper +} F14_COMPLEX_CONFIG; + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/PcieFamilyServices.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/PcieFamilyServices.h new file mode 100644 index 0000000000..51fe82ea0c --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Family/PcieFamilyServices.h @@ -0,0 +1,135 @@ +/* $NoKeywords:$ */ + +/** + * @file + * + * Family specific PCIe services. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _PCIECOMPLEXCONFIG_H_ +#define _PCIECOMPLEXCONFIG_H_ + + +VOID +PcieFmPhyApplyGanging ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieFmPhyLetPllPersonalityInitCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmPhyChannelCharacteristic ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmPortVisabilityControl ( + IN PCIE_PORT_VISIBILITY Control, + IN PCIe_SILICON_CONFIG *Silicon, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmPreInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + + +VOID +PcieFmAvertClockPickers ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmSetBootUpVoltage ( + IN PCIE_LINK_SPEED_CAP LinkCap, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmEnableSlotPowerLimit ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmConfigureClock ( + IN PCIE_LINK_SPEED_CAP LinkSpeedCapability, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmPifSetRxDetectPowerMode ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PcieFmPifSetPllModeForL1 ( + IN UINT32 LaneBitmap, + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +UINT8 +PcieFmPifGetPllPowerUpLatency ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PcieFmPhyLaneInitInitCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ); +#endif + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PCieSmuLibV1.esl b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PCieSmuLibV1.esl new file mode 100644 index 0000000000..5ca83524a4 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PCieSmuLibV1.esl @@ -0,0 +1,217 @@ +/** + * @file + * + * ALIB PSPP Pcie Smu Lib V1 + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 25430 $ @e \$Date: 2010-01-18 22:25:55 -0800 (Mon, 18 Jan 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + /*----------------------------------------------------------------------------------------*/ + /** + * SMU indirect register read + * + * Arg0 - Smu register offset + * + */ + Method (procNbSmuIndirectRegisterRead, 1, NotSerialized) { + Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) + // Access 32 bit width + Increment (Arg0) + // Reverse ReqToggle + Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) + // Assign Address and ReqType = 0 + Or (And (Local0, 0xFD00FFFF), ShiftLeft (Arg0, 16), Local0) + + procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) + + Store (procIndirectRegisterRead (0x0, 0x60, 0xCE), Local0) + return (Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * SMU indirect register Write + * + * Arg0 - Smu register offset + * Arg1 - Value + * Arg2 - Width, 0 = 16, 1 = 32 + * + */ + Method (procNbSmuIndirectRegisterWrite, 3, NotSerialized) { + Store (procIndirectRegisterRead (0x0, 0x60, 0xCD), Local0) + // Get low 16 bit value + Store (And (Arg1, 0xFFFF), Local1) + // Reverse ReqToggle + Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) + // Assign Address + Or (And (Local0, 0xFD000000), ShiftLeft (Arg0, 16), Local0) + // ReqType = 1 + Or (Local0, 0x02000000, Local0) + // Assign Low 16 bit value + Or (Local0, Local1, Local0) + + procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) + + if (LEqual (Arg2, 1)) { + // Get high 16 bit value + Store (ShiftRight (Arg1, 16), Local1) + // Reverse ReqToggle + Or (And (Local0, 0xFEFFFFFF), And (Not (And (Local0, 0x01000000)), 0x01000000),Local0) + // Assign Address + Or (And (Local0, 0xFF000000), ShiftLeft (Add (Arg0, 1), 16), Local0) + // Assign High 16 bit value + Or (Local0, Local1, Local0) + + procIndirectRegisterWrite (0x0, 0x60, 0xCD, Local0) + } + + } + + /*----------------------------------------------------------------------------------------*/ + /** + * SMU Service request + * + * Arg0 - Smu service id + * Arg1 - Flags - Poll Ack = 1, Poll down = 2 + * + */ + Method (procNbSmuServiceRequest, 2, NotSerialized) { + Store ("NbSmuServiceRequest Enter", Debug) + Store ("Request id =", Debug) + Store (Arg0, Debug) + + Or (ShiftLeft (Arg0, 3), 0x1, Local0) + procNbSmuIndirectRegisterWrite (0x3, Local0, 1) + + if (LAnd (Arg1, 1)) { + while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x2), 0x2)) { + Store ("--Wait Ack--", Debug) + } + } + if (LAnd (Arg1, 2)) { + while (LNotEqual (AND(procNbSmuIndirectRegisterRead (0x3), 0x4), 0x4)) { + Store ("--Wait Done--", Debug) + } + } + // Clear IRQ register + procNbSmuIndirectRegisterWrite (0x3, 0, 0) + Store ("NbSmuServiceRequest Exit", Debug) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Write RCU register + * + * Arg0 - Register Address + * Arg1 - Register Data + * + */ + Method (procSmuRcuWrite, 2, NotSerialized) { + procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) + procNbSmuIndirectRegisterWrite (0x5, Arg1, 1) + + } + + /*----------------------------------------------------------------------------------------*/ + /** + * Read RCU register + * + * Arg0 - Register Address + * Retval - RCU register value + */ + Method (procSmuRcuRead, 1, NotSerialized) { + procNbSmuIndirectRegisterWrite (0xB, Arg0, 0) + Store (procNbSmuIndirectRegisterRead (0x5), Local0) + return (Local0) + } + + /*----------------------------------------------------------------------------------------*/ + /** + * SMU SRBM Register Read + * + * Arg0 - FCR register address + * + */ + Method (procNbSmuSrbmRegisterRead, 1, NotSerialized) { + //SMUx0B_x8600 + Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) + //SMUx0B_x8604 + Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) + //SMUx0B_x8608 + Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) + //Write SMU RCU + procSmuRcuWrite (0x8600, Local0) + procSmuRcuWrite (0x8604, Local1) + procSmuRcuWrite (0x8608, Local2) + // ServiceId + if (LEqual (ShiftRight (Arg0, 16), 0xFE00)) { + procNbSmuServiceRequest (0xD, 0x3) + } + if (LEqual (ShiftRight (Arg0, 16), 0xFE30)) { + procNbSmuServiceRequest (0xB, 0x3) + } + return (procSmuRcuRead(0x8650)) + } + + + /*----------------------------------------------------------------------------------------*/ + /** + * SMU SRBM Register Write + * + * Arg0 - FCR register address + * Arg1 - Value + * + */ + Method (procNbSmuSrbmRegisterWrite, 2, NotSerialized) { + //SMUx0B_x8600 + Store (Or (And (Arg0, 0xFF), 0x01865000), Local0) + //SMUx0B_x8604 + Store (Or (And (Arg0, 0xFFFFFF00), 4), Local1) + //SMUx0B_x8608 + Store (Or (ShiftLeft (3, 30), ShiftLeft (1, 18)), Local2) + Or (Local2, ShiftLeft (1, 16), Local2) + //Write SMU RCU + procSmuRcuWrite (0x8600, Local0) + procSmuRcuWrite (0x8604, Local1) + procSmuRcuWrite (0x8608, Local2) + //Write Data + procSmuRcuWrite (0x8650, Arg1) + // ServiceId + procNbSmuServiceRequest (0xB, 0x3) + } diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PciePowerGate.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PciePowerGate.c new file mode 100644 index 0000000000..68ce8103a4 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PciePowerGate.c @@ -0,0 +1,372 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe power gate + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "amdlib.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "PcieInit.h" +#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "PciePowerGate.h" +#include "GnbRegistersON.h" +#include "NbSmuLib.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_FEATURE_PCIEPOWERGATE_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +#define FORCE_PCIE_POWERGATING_DISABLE (1 << 2) +#define FORCE_PCIE_PHY_POWERGATING_DISABLE (1 << 1) + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +POWER_GATE_DATA PciePowerGatingData = { + 113, 50, 50, 50, 50, 50 +}; + + +/// PCIe power gating +UINT32 PciePowerGatingTable_1[] = { +// SMUx0B_x8408_ADDRESS + 0, +// SMUx0B_x840C_ADDRESS + 0, +// SMUx0B_x8410_ADDRESS + (0x0 << SMUx0B_x8410_PwrGatingEn_OFFSET) | + (0x1 << SMUx0B_x8410_PsoControlValidNum_OFFSET) | + (0x3 << SMUx0B_x8410_PwrGaterSel_OFFSET) +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Power Gating + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @param[in] Flags Force Powergating disable or Phy disable flag. + * @param[in] PowerGateData Power Gate data + */ + + +VOID +STATIC +PcieSmuPowerGatingInit ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT8 Flags, + IN POWER_GATE_DATA *PowerGateData + ) +{ + + NbSmuRcuRegisterWrite ( + SMUx0B_x8408_ADDRESS, + &PciePowerGatingTable_1[0], + sizeof (PciePowerGatingTable_1) / sizeof (UINT32), + TRUE, + StdHeader + ); + + NbSmuRcuRegisterWrite ( + SMUx0B_x84A0_ADDRESS, + (UINT32 *) PowerGateData, + sizeof (POWER_GATE_DATA) / sizeof (UINT32), + TRUE, + StdHeader + ); + if (Flags != 0) { + UINT32 Value; + ASSERT ((Flags & (~(BIT1 | BIT2))) == 0); + NbSmuRcuRegisterRead (SMUx0B_x8410_ADDRESS, &Value, 1, StdHeader); + Value |= (Flags & (BIT1 | BIT2)); + NbSmuRcuRegisterWrite (SMUx0B_x8410_ADDRESS, &Value, 1, TRUE, StdHeader); + } + NbSmuServiceRequest (0x01, TRUE, StdHeader); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe PowerGate PHY lanes + * + * + * @param[in] WrapperLaneBitMap Lane bitmap on wrapper + * @param[in] WrapperStartlaneId Start Line Id of the wrapper + * @param[in] Service Power gate service + * @param[in] Core Core power gate request + * @param[in] Tx Tx power gate request + * @param[in] Rx Rx power gate request + * @param[in] Pcie PCIe configuration data + */ + +VOID +STATIC +PcieSmuPowerGateLanes ( + IN UINT32 WrapperLaneBitMap, + IN UINT16 WrapperStartlaneId, + IN UINT8 Service, + IN UINT8 Core, + IN UINT8 Tx, + IN UINT8 Rx, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_PHY_POWER_GATE LaneSegment; + UINT8 NumberOfLanes; + UINT8 Index; + LaneSegment.Tx = Tx; + LaneSegment.Rx = Rx; + LaneSegment.Core = Core; + NumberOfLanes = 0; + for (Index = 0; Index <= 32; Index++) { + if ((WrapperLaneBitMap & 1) != 0) { + NumberOfLanes++; + } else { + if (NumberOfLanes != 0) { + LaneSegment.LowerLaneId = Index - NumberOfLanes + WrapperStartlaneId; + LaneSegment.UpperLaneId = Index - 1 + WrapperStartlaneId; + IDS_HDT_CONSOLE (PCIE_MISC, " Powergate Phy Lanes %d - %d (Service = 0x%x, Core = 0x%x, Tx = 0x%x, Rx = 0x%x)\n", + LaneSegment.LowerLaneId, LaneSegment.UpperLaneId, Service, Core, Tx, Rx + ); + NbSmuRcuRegisterWrite ( + 0x858C, + (UINT32*) &LaneSegment, + 1, + TRUE, + GnbLibGetHeader (Pcie) + ); + NbSmuServiceRequest (Service, TRUE, GnbLibGetHeader (Pcie)); + NumberOfLanes = 0; + } + } + WrapperLaneBitMap >>= 1; + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Pll access required + * + * @param[in] PllId Pll ID + * @param[in] AccessRequired Access required + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +STATIC +PciePowerGatePllControl ( + IN UINT8 PllId, + IN BOOLEAN AccessRequired, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 Value; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Enter\n"); + NbSmuRcuRegisterRead (0x859C, &Value, 1, GnbLibGetHeader (Pcie)); + Value = (Value & 0xFFFFFF00) | PllId; + NbSmuRcuRegisterWrite (0x859C, &Value, 1, TRUE, GnbLibGetHeader (Pcie)); + NbSmuServiceRequest (AccessRequired ? 0x18 : 0x17, TRUE, GnbLibGetHeader (Pcie)); + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePllControl Exit\n"); +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Report used lanes to SMU. + * + * + * @param[in] Wrapper Wrapper configuration descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +STATIC +PciePowerGateReportUsedLanesCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 LaneBitmap; + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE | LANE_TYPE_PCIE_HOTPLUG, 0, Wrapper, Pcie); + if (LaneBitmap != 0) { + PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x14, 0x1, 0x0, 0x0, Pcie); + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe PowerGate PHY lanes + * + * + * @param[in] Wrapper Wrapper configuration descriptor + * @param[out] Buffer Pointer to Boolean to report if DDI lanes present + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +STATIC +PciePowerGatePhyLaneCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT32 LaneBitmap; + BOOLEAN *IsDdiPresent; + IsDdiPresent = (BOOLEAN*) Buffer; + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE | LANE_TYPE_PCIE_HOTPLUG, Wrapper, Pcie); + if (LaneBitmap != 0) { + PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x1, 0x1, 0x1, Pcie); + } + // Powergate inactive hotplug lanes + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_PCIE_HOTPLUG, LANE_TYPE_PCIE_ACTIVE, Wrapper, Pcie); + if (LaneBitmap != 0) { + PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x0, 0x1, 0x1, Pcie); + } + // Powergate DDI lanes + LaneBitmap = PcieUtilGetWrapperLaneBitMap (LANE_TYPE_DDI_ACTIVE, 0, Wrapper, Pcie); + if (LaneBitmap != 0) { + *IsDdiPresent = TRUE; + PcieSmuPowerGateLanes (LaneBitmap, Wrapper->StartPhyLane, 0x13, 0x0, 0x0, 0x1, Pcie); + } + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe PowerGate PHY lanes + * + * + * + * @param[in] StdHeader Standard Configuration Header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +STATIC +PciePowerGatePhyLane ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + BOOLEAN IsDdiPresent; + PCIe_PLATFORM_CONFIG *Pcie; + AgesaStatus = AGESA_SUCCESS; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePhyLane Enter\n"); + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + ASSERT (Status == AGESA_SUCCESS); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControl (UnhidePorts, Pcie); + IsDdiPresent = FALSE; + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePowerGateReportUsedLanesCallback, NULL, Pcie ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + PciePowerGatePllControl (0x1, TRUE, Pcie); + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PciePowerGatePhyLaneCallback, &IsDdiPresent, Pcie ); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (!IsDdiPresent) { + PciePowerGatePllControl (0x1, FALSE, Pcie); + } + PciePortsVisibilityControl (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGatePhyLane Exit\n"); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Power PCIe block + * + * + * + * @param[in] StdHeader Pointer to Standard configuration + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PciePowerGateFeature ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + PCIE_POWERGATE_CONFIG PciePowerGate; + AGESA_STATUS Status; + UINT8 Flags; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateFeature Enter\n"); + Status = AGESA_SUCCESS; + PciePowerGate.Services.PciePowerGate = 0x1; + PciePowerGate.Services.PciePhyLanePowerGate = 0x1; + LibAmdMemCopy (&PciePowerGate.Pcie, &PciePowerGatingData, sizeof (POWER_GATE_DATA), StdHeader); + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG, &PciePowerGate, StdHeader); + Flags = 0; + if (PciePowerGate.Services.PciePowerGate == 0x0) { + IDS_HDT_CONSOLE (PCIE_MISC, " Pcie Power Gating - Disabled\n"); + Flags |= FORCE_PCIE_POWERGATING_DISABLE; + } + if (PciePowerGate.Services.PciePhyLanePowerGate == 0x0) { + IDS_HDT_CONSOLE (PCIE_MISC, " Pcie Phy Power Gating - Disabled\n"); + Flags |= FORCE_PCIE_PHY_POWERGATING_DISABLE; + } + PcieSmuPowerGatingInit (StdHeader, Flags, &PciePowerGate.Pcie); + Status = PciePowerGatePhyLane (StdHeader); + IDS_HDT_CONSOLE (GNB_TRACE, "PciePowerGateFeature Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PciePowerGate.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PciePowerGate.h new file mode 100644 index 0000000000..34aef56f29 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/Feature/PciePowerGate.h @@ -0,0 +1,69 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Service procedure to calculate PCIe topology segment maximum exit latency + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _PCIEPOWERGATE_H_ +#define _PCIEPOWERGATE_H_ + +/// PCIe power gate configuration +typedef struct { + struct { + UINT32 PciePowerGate :1; ///< Enable core power gating + UINT32 PciePhyLanePowerGate:1; ///< Enable phy lane power gating + } Services; ///< Power gating services + POWER_GATE_DATA Pcie; ///< PCIe Power gating Data +} PCIE_POWERGATE_CONFIG; + +/// PCIe PHY power gate config +typedef struct { + UINT32 Rx :1; ///< RX state + UINT32 Tx :1; ///< TX state + UINT32 Core :1; ///< Core + UINT32 Reserved :13; ///< reserved + UINT32 LowerLaneId :8; ///< Lower lane ID + UINT32 UpperLaneId :8; ///< Upper lane ID +} PCIe_PHY_POWER_GATE; + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.c new file mode 100644 index 0000000000..08588fdcda --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.c @@ -0,0 +1,351 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Pre-training PCIe subsystem initialization routines. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "PcieFamilyServices.h" +#include "PcieInit.h" +#include "PcieMiscLib.h" +#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1) +#include "GnbRegistersON.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_PCIEINIT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Control port visibility in PCI config space + * + * + * @param[in] Control Make port Hide/Unhide ports + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PciePortsVisibilityControl ( + IN PCIE_PORT_VISIBILITY Control, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIe_COMPLEX_CONFIG *ComplexList; + ComplexList = &Pcie->ComplexList[0]; + while (ComplexList != NULL) { + PCIe_SILICON_CONFIG *SiliconList; + SiliconList = PcieComplexGetSiliconList (ComplexList); + while (SiliconList != NULL) { + PcieFmPortVisabilityControl (Control, SiliconList, Pcie); + SiliconList = PcieLibGetNextDescriptor (SiliconList); + } + ComplexList = PcieLibGetNextDescriptor (ComplexList); + } +} + + +PCIE_HOST_REGISTER_ENTRY CoreInitTable [] = { + { + D0F0xE4_CORE_0020_ADDRESS, + D0F0xE4_CORE_0020_CiRcOrderingDis_MASK | + D0F0xE4_CORE_0020_CiSlvOrderingDis_MASK, + (0x1 << D0F0xE4_CORE_0020_CiRcOrderingDis_OFFSET) + }, + { + D0F0xE4_CORE_0010_ADDRESS, + D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_MASK, + (0x4 << D0F0xE4_CORE_0010_RxUmiAdjPayloadSize_OFFSET) + }, + { + D0F0xE4_CORE_001C_ADDRESS, + D0F0xE4_CORE_001C_TxArbRoundRobinEn_MASK | + D0F0xE4_CORE_001C_TxArbSlvLimit_MASK | + D0F0xE4_CORE_001C_TxArbMstLimit_MASK, + (0x1 << D0F0xE4_CORE_001C_TxArbRoundRobinEn_OFFSET) | + (0x4 << D0F0xE4_CORE_001C_TxArbSlvLimit_OFFSET) | + (0x4 << D0F0xE4_CORE_001C_TxArbMstLimit_OFFSET) + }, + { + D0F0xE4_CORE_0040_ADDRESS, + D0F0xE4_CORE_0040_PElecIdleMode_MASK, + (0x2 << D0F0xE4_CORE_0040_PElecIdleMode_OFFSET) + }, + { + D0F0xE4_CORE_0002_ADDRESS, + D0F0xE4_CORE_0002_HwDebug_0__MASK, + (0x1 << D0F0xE4_CORE_0002_HwDebug_0__OFFSET) + }, + { + D0F0xE4_CORE_00C1_ADDRESS, + D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_MASK | + D0F0xE4_CORE_00C1_StrapGen2Compliance_MASK, + (0x1 << D0F0xE4_CORE_00C1_StrapLinkBwNotificationCapEn_OFFSET) | + (0x1 << D0F0xE4_CORE_00C1_StrapGen2Compliance_OFFSET) + }, + { + D0F0xE4_CORE_00B0_ADDRESS, + D0F0xE4_CORE_00B0_StrapF0MsiEn_MASK | + D0F0xE4_CORE_00B0_StrapF0AerEn_MASK, + (0x1 << D0F0xE4_CORE_00B0_StrapF0MsiEn_OFFSET) + } +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Common Core Init + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ +VOID +PcieCommonCoreInit ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + UINT8 CoreId; + UINTN Index; + if (PcieLibIsPcieWrapper (Wrapper)) { + IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Enter\n"); + for (CoreId = Wrapper->StartPcieCoreId; CoreId <= Wrapper->EndPcieCoreId; CoreId++) { + for (Index = 0; Index < sizeof (CoreInitTable) / sizeof (PCIE_HOST_REGISTER_ENTRY); Index++) { + UINT32 Value; + Value = PcieRegisterRead ( + Wrapper, + CORE_SPACE (CoreId, CoreInitTable[Index].Reg), + Pcie + ); + Value &= (~CoreInitTable[Index].Mask); + Value |= CoreInitTable[Index].Data; + PcieRegisterWrite ( + Wrapper, + CORE_SPACE (CoreId, CoreInitTable[Index].Reg), + Value, + FALSE, + Pcie + ); + } + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieCommonCoreInit Exit\n"); + } +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Init SRBM reset prior Aaccess to wrapper registers. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +PcieInitSrbmCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PcieTopologyInitSrbmReset (TRUE, Wrapper, Pcie); + return AGESA_SUCCESS; +} +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Init prior training. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +PcieInitCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + PcieTopologyPrepareForReconfig (Wrapper, Pcie); + Status = PcieTopologySetCoreConfig (Wrapper, Pcie); + ASSERT (Status == AGESA_SUCCESS); + PcieTopologyApplyLaneMux (Wrapper, Pcie); + PcieFmPifSetRxDetectPowerMode (Wrapper, Pcie); + PciePifSetLs2ExitTime (Wrapper, Pcie); + PcieTopologySelectMasterPll (Wrapper, Pcie); + PcieTopologyExecuteReconfig (Wrapper, Pcie); + PcieTopologySetLinkReversal (Wrapper, Pcie); + PciePifApplyGanging (Wrapper, Pcie); + PcieFmPhyApplyGanging (Wrapper, Pcie); + PciePifPllInitForDdi (Wrapper, Pcie); + PcieTopologyLaneControl ( + DisableLanes, + PcieUtilGetWrapperLaneBitMap (LANE_TYPE_ALL, LANE_TYPE_PCIE_ALLOCATED, Wrapper, Pcie), + Wrapper, + Pcie + ); + PcieSetDdiOwnPhy (Wrapper, Pcie); + PciePollPifForCompeletion (Wrapper, Pcie); + PcieFmAvertClockPickers (Wrapper, Pcie); + PcieFmConfigureClock (PcieGen1, Wrapper, Pcie); + PcieCommonCoreInit (Wrapper, Pcie); + PciePifDisableFifoReset (Wrapper, Pcie); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Init + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +PcieInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitSrbmCallback, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + PcieFmPreInit (Pcie); + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieInitCallback, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + PcieFmSetBootUpVoltage (PcieGen1, Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInit Exit [%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Init prior training. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +PciePostInitCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + + Status = AGESA_SUCCESS; + PcieFmConfigureClock ( + PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie), + Wrapper, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Init + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +PciePostInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + AGESA_STATUS AgesaStatus; + + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_PCIE_WRAPPER, PciePostInitCallback, NULL, Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + PcieFmSetBootUpVoltage ( + PcieUtilGlobalGenCapability (PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_ALL_PORTS, Pcie), + Pcie + ); + IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInit Exit [%x]\n", AgesaStatus); + return AgesaStatus; +} + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.h new file mode 100644 index 0000000000..4e2f83ae6e --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInit.h @@ -0,0 +1,67 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Pre-training PCIe subsystem initialization routines. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +#ifndef _PCIEINIT_H_ +#define _PCIEINIT_H_ + +AGESA_STATUS +PcieInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PciePostInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +VOID +PciePortsVisibilityControl ( + IN PCIE_PORT_VISIBILITY Control, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEarlyPost.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEarlyPost.c new file mode 100644 index 0000000000..7da85e495e --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEarlyPost.c @@ -0,0 +1,125 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe early post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "PcieInit.h" +#include "PciePortInit.h" +#include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1) +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "PcieInitAtEarlyPost.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_PCIEINITATEARLYPOST_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Early Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ + +AGESA_STATUS +PcieInitAtEarly ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtEarly Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status != AGESA_FATAL) { + + PciePortsVisibilityControl (UnhidePorts, Pcie); + + Status = PcieInit (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PciePortInit (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControl (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtEarly Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEarlyPost.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEarlyPost.h new file mode 100644 index 0000000000..cd3c738900 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEarlyPost.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe early post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 38641 $ @e \$Date: 2010-09-27 23:16:17 +0800 (Mon, 27 Sep 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _PCIEINITATEARLYPOST_H_ +#define _PCIEINITATEARLYPOST_H_ + +AGESA_STATUS +PcieInitAtEarly ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEnv.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEnv.c new file mode 100644 index 0000000000..3bdc2b9cba --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEnv.c @@ -0,0 +1,93 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "PcieInit.h" +#include "PcieInitAtPost.h" +#include "PcieInitAtEnv.h" +#include "S3SaveState.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_PCIEINITATENV_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Env Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieInitAtEnv ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + S3_SAVE_DISPATCH (StdHeader, S3DispatchGnbPcieLateRestore, 0, NULL); + return AGESA_SUCCESS; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEnv.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEnv.h new file mode 100644 index 0000000000..1e1765f1e4 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtEnv.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _PCIEINITATPOST_H_ +#define _PCIEINITATPOST_H_ + +AGESA_STATUS +PcieInitAtEnv ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtLatePost.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtLatePost.c new file mode 100644 index 0000000000..2aa4ff9e92 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtLatePost.c @@ -0,0 +1,114 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "PcieInit.h" +#include "PcieLateInit.h" +#include "PciePortLateInit.h" +#include "PcieInitAtLatePost.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_PCIEINITATLATEPOST_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Mid Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieInitAtMid ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtMid Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControl (UnhidePorts, Pcie); + + Status = PciePortLateInit (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieLateInit (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControl (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtMid Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtLatePost.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtLatePost.h new file mode 100644 index 0000000000..28768d69c9 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtLatePost.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _PCIEINITATLATEPOST_H_ +#define _PCIEINITATLATEPOST_H_ + +AGESA_STATUS +PcieInitAtMid ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtPost.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtPost.c new file mode 100644 index 0000000000..0ee02f4614 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtPost.c @@ -0,0 +1,139 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "PcieInit.h" +#include "PciePortInit.h" +#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1) +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_PCIEINITATPOST_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe Post Init + * + * + * + * @param[in] StdHeader Standard configuration header + * @retval AGESA_STATUS + */ +AGESA_STATUS +PcieInitAtPost ( + IN AMD_CONFIG_PARAMS *StdHeader + ) +{ + AGESA_STATUS AgesaStatus; + AGESA_STATUS Status; + PCIe_PLATFORM_CONFIG *Pcie; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPost Enter\n"); + AgesaStatus = AGESA_SUCCESS; + Status = PcieLocateConfigurationData (StdHeader, &Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + if (Status == AGESA_SUCCESS) { + PciePortsVisibilityControl (UnhidePorts, Pcie); + + Status = PciePostInit (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PciePortPostInit (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + Status = PcieTraining (Pcie); + AGESA_STATUS_UPDATE (Status, AgesaStatus); + ASSERT (Status == AGESA_SUCCESS); + + PciePortsVisibilityControl (HidePorts, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PcieInitAtPost Exit [0x%x]\n", AgesaStatus); + return AgesaStatus; +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * PCIe S3 restore + * + * + * + * @param[in] StdHeader Standard configuration header + * @param[in] ContextLength Context Length (not used) + * @param[in] Context Context pointer (not used) + */ +VOID +PcieLateRestoreS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ) +{ + PcieInitAtPost (StdHeader); +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtPost.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtPost.h new file mode 100644 index 0000000000..8d04b4ee1b --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieInitAtPost.h @@ -0,0 +1,62 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe late post initialization. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _PCIEINITATPOST_H_ +#define _PCIEINITATPOST_H_ + +AGESA_STATUS +PcieInitAtPost ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +VOID +PcieLateRestoreS3Script ( + IN AMD_CONFIG_PARAMS *StdHeader, + IN UINT16 ContextLength, + IN VOID* Context + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieLateInit.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieLateInit.c new file mode 100644 index 0000000000..a979511279 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieLateInit.c @@ -0,0 +1,154 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Pre-training PCIe subsystem initialization routines. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "PcieLateInit.h" +#include "PcieFamilyServices.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "GnbRegistersON.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_PCIELATEINIT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Power down inactive lanes + * + * + * @param[in] Wrapper Pointer to wrapper config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + */ + +VOID +PciePwrPowerDownPllInL1 ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + + UINT32 LaneBitmapForPllOffInL1; + UINT8 PllPowerUpLatency; + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownPllInL1 Enter\n"); + PllPowerUpLatency = PcieFmPifGetPllPowerUpLatency (Wrapper, Pcie); + LaneBitmapForPllOffInL1 = PcieLanesToPowerDownPllInL1 (PllPowerUpLatency, Wrapper, Pcie); + if (LaneBitmapForPllOffInL1 != 0) { + PcieFmPifSetPllModeForL1 (LaneBitmapForPllOffInL1, Wrapper, Pcie); + } + IDS_HDT_CONSOLE (GNB_TRACE, "PciePwrPowerDownPllInL1 Exir\n"); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Per wrapper Pcie Late Init. + * + * + * @param[in] Wrapper Pointer to wrapper configuration descriptor + * @param[in] Buffer Pointer buffer + * @param[in] Pcie Pointer to global PCIe configuration + */ +AGESA_STATUS +PcieLateInitCallback ( + IN PCIe_WRAPPER_CONFIG *Wrapper, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePwrPowerDownUnusedLanes (Wrapper, Pcie); + PciePwrPowerDownPllInL1 (Wrapper, Pcie); + PciePwrClockGating (Wrapper, Pcie); + PcieLockRegisters (Wrapper, Pcie); + return AGESA_SUCCESS; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Pcie Late Init + * + * Late PCIe initialization + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_SUCCESS Topology successfully mapped + * @retval AGESA_ERROR Topology can not be mapped + */ + +AGESA_STATUS +PcieLateInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + IDS_HDT_CONSOLE (GNB_TRACE, "PcieLateInit Enter\n"); + Status = PcieConfigRunProcForAllWrappers (DESCRIPTOR_ALL_WRAPPERS, PcieLateInitCallback, NULL, Pcie); + IDS_HDT_CONSOLE (GNB_TRACE, "PcieLateInit Exit [0x%x]\n", Status); + return Status; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieLateInit.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieLateInit.h new file mode 100644 index 0000000000..c5fe6568e2 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieLateInit.h @@ -0,0 +1,56 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * Late initialization routine. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _PCIELATEINIT_H_ +#define _PCIELATEINIT_H_ + +AGESA_STATUS +PcieLateInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieMiscLib.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieMiscLib.c new file mode 100644 index 0000000000..97eb370759 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieMiscLib.c @@ -0,0 +1,158 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe utility. Various supporting functions. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 38931 $ @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "GnbRegistersON.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_PCIEMISCLIB_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +typedef struct { + UINT32 Flags; + PCIE_LINK_SPEED_CAP LinkSpeedCapability; +} PCIE_GLOBAL_GEN_CAP_WORKSPACE; + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + + +/*----------------------------------------------------------------------------------------*/ +/** + * Training state handling + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Indicate if engine in non final state + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieUtilGlobalGenCapabilityCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_GLOBAL_GEN_CAP_WORKSPACE *GlobalGenCapability; + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + PCIE_HOTPLUG_TYPE HotPlugType; + UINT32 Flags; + + Flags = PCIE_GLOBAL_GEN_CAP_ALL_PORTS; + GlobalGenCapability = (PCIE_GLOBAL_GEN_CAP_WORKSPACE*) Buffer; + LinkSpeedCapability = PcieGen1; + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS)) { + Flags |= PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS; + } + HotPlugType = Engine->Type.Port.PortData.LinkHotplug; + if ((HotPlugType == HotplugBasic) || (HotPlugType == HotplugServer) || (HotPlugType == HotplugEnhanced)) { + Flags |= PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS; + } + if ((GlobalGenCapability->Flags & Flags) != 0) { + ASSERT ((GlobalGenCapability->Flags & (PCIE_PORT_GEN_CAP_MAX | PCIE_PORT_GEN_CAP_BOOT)) != 0); + LinkSpeedCapability = PcieFmGetLinkSpeedCap (GlobalGenCapability->Flags, Engine, Pcie); + if (GlobalGenCapability->LinkSpeedCapability < LinkSpeedCapability) { + GlobalGenCapability->LinkSpeedCapability = LinkSpeedCapability; + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Determine global GEN capability + * + * + * @param[in] Flags global GEN capability flags + * @param[in] Pcie Pointer to global PCIe configuration + * + */ +PCIE_LINK_SPEED_CAP +PcieUtilGlobalGenCapability ( + IN UINT32 Flags, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP GlobalCapability; + PCIE_GLOBAL_GEN_CAP_WORKSPACE GlobalGenCap; + + GlobalGenCap.LinkSpeedCapability = PcieGen1; + GlobalGenCap.Flags = Flags; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PcieUtilGlobalGenCapabilityCallback, + &GlobalGenCap, + Pcie + ); + + GlobalCapability = GlobalGenCap.LinkSpeedCapability; + + return GlobalCapability; +} + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieMiscLib.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieMiscLib.h new file mode 100644 index 0000000000..baf4d75eaa --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PcieMiscLib.h @@ -0,0 +1,56 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe utility. Various supporting functions. + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 38935 $ @e \$Date: 2010-10-01 18:45:23 -0700 (Fri, 01 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _PCIEMISCLIB_H_ +#define _PCIEMISCLIB_H_ + +PCIE_LINK_SPEED_CAP +PcieUtilGlobalGenCapability ( + IN UINT32 Flags, + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.c new file mode 100644 index 0000000000..2802ba21f7 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.c @@ -0,0 +1,256 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe port initialization service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "GnbPcieFamServices.h" +#include "PcieFamilyServices.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include GNB_MODULE_DEFINITIONS (GnbPcieTrainingV1) +#include "GnbRegistersON.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_PCIEPORTINIT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +PCIE_PORT_REGISTER_ENTRY PortInitTable [] = { + { + DxF0xE4_x02_ADDRESS, + DxF0xE4_x02_RegsLcAllowTxL1Control_MASK, + (0x1 << DxF0xE4_x02_RegsLcAllowTxL1Control_OFFSET) + }, + { + DxF0xE4_x70_ADDRESS, + DxF0xE4_x70_RxRcbCplTimeoutMode_MASK, + (0x1 << DxF0xE4_x70_RxRcbCplTimeoutMode_OFFSET) + }, + { + DxF0xE4_xA0_ADDRESS, + DxF0xE4_xA0_Lc16xClearTxPipe_MASK | DxF0xE4_xA0_LcL1ImmediateAck_MASK, + (0x3 << DxF0xE4_xA0_Lc16xClearTxPipe_OFFSET) | + (0x1 << DxF0xE4_xA0_LcL1ImmediateAck_OFFSET) + }, + { + DxF0xE4_xA1_ADDRESS, + DxF0xE4_xA1_LcDontGotoL0sifL1Armed_MASK, + (0x1 << DxF0xE4_xA1_LcDontGotoL0sifL1Armed_OFFSET) + }, + { + DxF0xE4_xA2_ADDRESS, + DxF0xE4_xA2_LcRenegotiateEn_MASK | DxF0xE4_xA2_LcUpconfigureSupport_MASK, + (0x1 << DxF0xE4_xA2_LcRenegotiateEn_OFFSET) | + (0x1 << DxF0xE4_xA2_LcUpconfigureSupport_OFFSET) + }, + { + DxF0xE4_xA3_ADDRESS, + DxF0xE4_xA3_LcXmitFtsBeforeRecovery_MASK, + (0x1 << DxF0xE4_xA3_LcXmitFtsBeforeRecovery_OFFSET) + }, + { + DxF0xE4_xB1_ADDRESS, + DxF0xE4_xB1_LcDeassertRxEnInL0s_MASK | DxF0xE4_xB1_LcBlockElIdleinL0_MASK, + (0x1 << DxF0xE4_xB1_LcDeassertRxEnInL0s_OFFSET) | + (0x1 << DxF0xE4_xB1_LcBlockElIdleinL0_OFFSET) + } +}; + + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePortInitCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + PciePortProgramRegisterTable (PortInitTable, (sizeof (PortInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, FALSE, Pcie); + PcieSetLinkSpeedCap (PcieGen1, Engine, Pcie); + PcieSetLinkWidthCap (Engine, Pcie); + PcieCompletionTimeout (Engine, Pcie); + PcieLinkSetSlotCap (Engine, Pcie); + PcieLinkInitHotplug (Engine, Pcie); + PcieFmPhyChannelCharacteristic (Engine, Pcie); + if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { + PcieLinkSafeMode (Engine, Pcie); + } + if (Engine->Type.Port.PortData.PortPresent == PortDisabled) { + ASSERT (Engine->Type.Port.IsSB == FALSE); + PcieTrainingSetPortState (Engine, LinkStateDeviceNotPresent, FALSE, Pcie); + } + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + PcieTrainingSetPortState (Engine, LinkStateTrainingCompleted, FALSE, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +PciePortInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PciePortInitCallback, + NULL, + Pcie + ); + return Status; +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePortPostInitCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PCIE_LINK_SPEED_CAP LinkSpeedCapability; + ASSERT (Engine->EngineData.EngineType == PciePortEngine); + if (Engine->Type.Port.PortData.MiscControls.LinkSafeMode == PcieGen1) { + PcieLinkSafeMode (Engine, Pcie); + } + LinkSpeedCapability = PcieFmGetLinkSpeedCap (PCIE_PORT_GEN_CAP_BOOT, Engine, Pcie); + PcieSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) && (LinkSpeedCapability > PcieGen1) && !Engine->Type.Port.IsSB) { + PcieTrainingSetPortState (Engine, LinkStateRetrain, FALSE, Pcie); + PcieConfigUpdatePortStatus (Engine, 0, INIT_STATUS_PCIE_TRAINING_SUCCESS); + } + if (Engine->Type.Port.PortData.MiscControls.LinkComplianceMode == 0x1) { + PcieForceCompliance (Engine, Pcie); + PcieTrainingSetPortState (Engine, LinkStateResetExit, FALSE, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +PciePortPostInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PciePortPostInitCallback, + NULL, + Pcie + ); + return Status; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.h new file mode 100644 index 0000000000..6e65c8d1c9 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortInit.h @@ -0,0 +1,62 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe port initialization service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ +#ifndef _PCIEPORTINITG_H_ +#define _PCIEPORTINITG_H_ + + +AGESA_STATUS +PciePortInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +AGESA_STATUS +PciePortPostInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif + + diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortLateInit.c b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortLateInit.c new file mode 100644 index 0000000000..e3a2b5ab21 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortLateInit.c @@ -0,0 +1,229 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe port initialization service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 39275 $ @e \$Date: 2010-10-09 08:22:05 +0800 (Sat, 09 Oct 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include "AGESA.h" +#include "Ids.h" +#include "Gnb.h" +#include "GnbPcie.h" +#include "PcieFamilyServices.h" +#include "PcieMiscLib.h" +#include GNB_MODULE_DEFINITIONS (GnbCommonLib) +#include GNB_MODULE_DEFINITIONS (GnbPcieInitLibV1) +#include GNB_MODULE_DEFINITIONS (GnbPcieConfig) +#include "GnbRegistersON.h" +#include "Filecode.h" +#define FILECODE PROC_GNB_PCIE_PCIEPORTLATEINIT_FILECODE +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ + +PCIE_PORT_REGISTER_ENTRY PortLateInitTable [] = { + { + DxF0xE4_xA2_ADDRESS, + DxF0xE4_xA2_LcDynLanesPwrState_MASK, + (0x3 << DxF0xE4_xA2_LcDynLanesPwrState_OFFSET) + }, + { + DxF0xE4_xC0_ADDRESS, + DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_MASK, + (0x1 << DxF0xE4_xC0_StrapAutoRcSpeedNegotiationDis_OFFSET) + } +}; + +/*----------------------------------------------------------------------------------------*/ +/** + * Enable ASPM + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PcieEnableAspm ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + if (Engine->Type.Port.PortData.LinkAspm != AspmDisabled) { + if (Engine->Type.Port.IsSB != 0) { + PcieSbLinkAspmControl (Engine, Pcie); + } else { + PcieLinkAspmEnable ( + Engine->Type.Port.Address, + Engine->Type.Port.PortData.LinkAspm, + GnbLibGetHeader (Pcie) + ); + } + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Set slot power limit + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +PcieSlotPowerLimit ( + IN PCIe_ENGINE_CONFIG *Engine, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + DxF0x6C_STRUCT DxF0x6C; + GnbLibPciRead ( + Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, + AccessWidth32, + &DxF0x6C.Value, + GnbLibGetHeader (Pcie) + ); + + DxF0x6C.Field.SlotPwrLimitValue = 75; + DxF0x6C.Field.PhysicalSlotNumber = Engine->Type.Port.Address.Address.Device; + + GnbLibPciWrite ( + Engine->Type.Port.Address.AddressValue | DxF0x6C_ADDRESS, + AccessS3SaveWidth32, + &DxF0x6C.Value, + GnbLibGetHeader (Pcie) + ); + PcieFmEnableSlotPowerLimit (Engine, Pcie); +} + + +/*----------------------------------------------------------------------------------------*/ +/** + * Callback to init various features on all active ports + * + * + * + * + * @param[in] Engine Pointer to engine config descriptor + * @param[in, out] Buffer Not used + * @param[in] Pcie Pointer to global PCIe configuration + * + */ + +VOID +STATIC +PciePortLateInitCallback ( + IN PCIe_ENGINE_CONFIG *Engine, + IN OUT VOID *Buffer, + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + PciePortProgramRegisterTable (PortLateInitTable, (sizeof (PortLateInitTable) / sizeof (PCIE_PORT_REGISTER_ENTRY)), Engine, TRUE, Pcie); + if (PcieConfigCheckPortStatus (Engine, INIT_STATUS_PCIE_TRAINING_SUCCESS) || Engine->Type.Port.PortData.LinkHotplug != HotplugDisabled) { + PcieSlotPowerLimit (Engine, Pcie); + } + PcieEnableAspm (Engine, Pcie); + if (Engine->Type.Port.IsSB != 0) { + PcieSbLinkVcEnable (Engine, Pcie); + } +} + +/*----------------------------------------------------------------------------------------*/ +/** + * Master procedure to init various features on all active ports + * + * + * + * + * @param[in] Pcie Pointer to global PCIe configuration + * @retval AGESA_STATUS + * + */ + +AGESA_STATUS +PciePortLateInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ) +{ + AGESA_STATUS Status; + PCIE_LINK_SPEED_CAP GlobalSpeedCap; + + Status = AGESA_SUCCESS; + PcieConfigRunProcForAllEngines ( + DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, + PciePortLateInitCallback, + NULL, + Pcie + ); + + GlobalSpeedCap = PcieUtilGlobalGenCapability ( + PCIE_PORT_GEN_CAP_BOOT | PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS | PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS, + Pcie + ); + + PcieFmSetBootUpVoltage (GlobalSpeedCap, Pcie); + + return Status; +} diff --git a/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortLateInit.h b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortLateInit.h new file mode 100644 index 0000000000..d3321558c9 --- /dev/null +++ b/src/vendorcode/amd/agesa/Proc/GNB/PCIe/PciePortLateInit.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * PCIe port initialization service procedure + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: 34897 $ @e \$Date: 2010-07-14 10:07:10 +0800 (Wed, 14 Jul 2010) $ + * + */ +/* + ***************************************************************************** + * + * Copyright (c) 2011, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * *************************************************************************** + * + */ + +#ifndef _PCIEPORTLATEINIT_H_ +#define _PCIEPORTLATEINIT_H_ + +AGESA_STATUS +PciePortLateInit ( + IN PCIe_PLATFORM_CONFIG *Pcie + ); + +#endif |