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authorNico Huber <nico.h@gmx.de>2022-08-05 13:09:25 +0200
committerFelix Held <felix-coreboot@felixheld.de>2022-08-17 16:29:39 +0000
commitbba97354b05cc8770d6d913bfe5777b46450bbb8 (patch)
tree3a9eef1f44a1c4e102d705d7918b5d980189b3b9 /src/superio
parent9099feaa94670af2dd558de35b74452570452028 (diff)
pciexp_device: Properly search for Intel's 0xcafe capability
We have this quirk in our tree since the introduction of L1-substate support[1]. The way we searched for this capability was rather crude: We simply assumed that it would show up in the first data word of another capability. As it turned out that it is actually a proper vendor-specific capa- bility that we are looking for, we can drop some of the mystic code. This was confirmed to work on the device that was originally used during development, Google/Samus. [1] commit 31c6e632cf (PCIe: Add L1 Sub-State support.) Change-Id: I886fb96e9a92387bc0e2a7feb746f7842cee5476 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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