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author | Michał Żygowski <michal.zygowski@3mdeb.com> | 2024-02-16 19:54:39 +0100 |
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committer | Nico Huber <nico.h@gmx.de> | 2024-04-04 21:06:26 +0000 |
commit | c72a65dccde199ef3e9b7ab51db86791b58e7b43 (patch) | |
tree | cb65a03361339893420651c291e8ff4c4ed4e3a7 /src/superio/smsc/sio10n268 | |
parent | 722565671618baeec9690a70a94c75467cb44117 (diff) |
soc/intel/common/block/fast_spi: probe for 2nd flash component
Fast SPI code assumes only one SPI flash is present. The SPI flash
driver for older southbridges is able to detect multichip. See the
spi_is_multichip() in src/southbridge/intel/common/spi.c.
Some boards (e.g. Lenovo ThinkCentre M920 Tiny) still come with two
chips populated instead of one. With this change, both chips are probed,
and the correct total size is calculated. Otherwise, only the first one
was probed, which resulted in an error such as:
SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x1800000!!
Change-Id: I8d7449f9e1470dc234fe5ba5217d3ce4c142b49c
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/superio/smsc/sio10n268')
0 files changed, 0 insertions, 0 deletions