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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-12-04 02:24:31 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-12-14 18:42:19 +0000 |
| commit | 551bd92b2b33fb71e74eb8d22db3aea69280a9b7 (patch) | |
| tree | da207596e6962fd3f8bd6c821da5dff923c30780 /src/superio/smsc/sch5147/acpi/superio.asl | |
| parent | 1a2b70284895a9daef667aada307405039dc8cce (diff) | |
soc/intel/jasperlake: Enables CSE Lite driver for JSL platform in the romstage
This patch sets up cse_fw_sync() call in the romstage.The cse_fw_sync()
must be called after DRAM initialization.
BUG=b:174694480
Test=Verified on Drawlet
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48280
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/superio/smsc/sch5147/acpi/superio.asl')
0 files changed, 0 insertions, 0 deletions