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| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-18 00:52:26 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-18 10:12:43 +0000 |
| commit | 0a20872de0b0de6354fa3164c998619b3218dd9f (patch) | |
| tree | f7b7807217cd875ddf2858439ab1ba1dafe74849 /src/superio/smsc/lpc47m10x/early_serial.c | |
| parent | fe276fb250df01aadc85ca8a6d6d0091bcf7dc93 (diff) | |
nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400
The 100 MHz reference clock seems to be unstable when using high
multipliers. Use the 133 MHz reference clock instead.
Change-Id: I400e4f91776306d54d818fa249d7a845020ac37b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45503
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/superio/smsc/lpc47m10x/early_serial.c')
0 files changed, 0 insertions, 0 deletions