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authorBrandon Breitenstein <brandon.breitenstein@intel.com>2016-10-03 15:38:54 -0700
committerMartin Roth <martinroth@google.com>2016-10-07 19:13:53 +0200
commit7692807f4f27a045c0e3638319528c7ae0873d57 (patch)
treeeec86d5bd8bea597d0f33c3a612b991010a8ca4a /src/superio/smsc/lpc47b397/lpc47b397.h
parent2e6aeba9ca442f5db23a3eef73f7eead82f596e9 (diff)
vendorcode/intel/fsp: Update UPD headers for FSP 157_10
These header files contain a few new UPDs. The EnableS3Heci2 UPD will be used to save ~100ms from the S3 resume time on Apollolake chrome platforms. BUG=chrome-os-partner:58121 BRANCH=none TEST=built coreboot for reef and verified no regressions Change-Id: I1f324d00237c7150697800258a2f7b7eed856417 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/16869 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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