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author | Angel Pons <th3fanbus@gmail.com> | 2024-04-28 21:34:20 +0200 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-29 21:59:40 +0000 |
commit | 1fa0fcbd7b47dce6b7726e8a37e8294e899521c6 (patch) | |
tree | 36de895a52603ebf42688b98116e0977b5e6cb50 /src/superio/renesas | |
parent | 0b90b0fb053f88959a81bd01e6d9988d2c533363 (diff) |
soc/intel/cmn/graphics: Make DDI-A 4 lanes configurable
As described in Intel document 336464 (8th gen S series datasheet volume
1), the CPU's 4 eDP lanes can be bifurcated, so that DDI-A (eDP) ends up
with 2 lanes, and DDI-E (DP, typically used for VGA) has the remaining 2
lanes. This lets mainboards provide a VGA output without sacrificing one
of the main 4-lane DDIs. Newer platforms seem to be lacking this.
However, the way this is structured in coreboot does not allow boards to
choose whether bifurcation should be enabled. Most boards in the tree do
not use DDI-E (it doesn't exist on mobile platforms), but there are some
boards (e.g. hp/280_g2) that use DDI-E and a DP-to-VGA converter chip to
provide a VGA output.
Replace `SOC_INTEL_CONFIGURE_DDI_A_4_LANES` with two new Kconfig options
to allow boards to decide. Use `SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION` to
specify whether a platform supports DDI-A bifurcation at all (do nothing
otherwise, maintaining the original code's behaviour). If bifurcation is
supported, the `SOC_INTEL_GFX_ENABLE_DDI_E_BIFURCATION` is used to clear
or set the `DDI_A_4_LANES` bit in the `DDI_BUF_CTL_A` register.
Change-Id: I516538db77509209d371f3f49c920476e06b052f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82113
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/superio/renesas')
0 files changed, 0 insertions, 0 deletions