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author | Arthur Heymans <arthur@aheymans.xyz> | 2020-12-08 12:49:38 +0100 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-01 08:45:05 +0000 |
commit | 98cc7830e77d9395034a9346ce890b69c23f00e8 (patch) | |
tree | 6548c22a05ac2ce7d682a020959c23347bf968ed /src/superio/nsc | |
parent | 33c0aac3b642b1f2a3cef5d3c32b150148eee90a (diff) |
drivers/intel/fsp2_0: Use coreboot postcar with FSP-T
Allow platforms to use the coreboot postcar code instead of calling
into FSP-M TempRamExit API.
There are several reasons to do this:
- Tearing down CAR is easy.
- Allows having control over MTRR's and caching in general.
- The MTRR's set up in postcar be it by coreboot or FSP-M are
overwritten later on during CPU init so it does not matter.
- Avoids having to find a CBFS file before cbmem is up (this
causes problems with cbfs_mcache)
Change-Id: I6cf10c7580f3183bfee1cd3c827901cbcf695db7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48466
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/superio/nsc')
0 files changed, 0 insertions, 0 deletions