diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-03-30 16:44:54 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-03-31 18:59:08 +0000 |
| commit | 8dcadc9189d538dfcc0d8247bcd027afd5697244 (patch) | |
| tree | f8163fe7eeb54c7c4d1ff6c771b473d7864e71c1 /src/superio/fintek/f81866d | |
| parent | 3e666898cd99f4e15a39e360bb594d499e738b2d (diff) | |
superio/fintek: Improve code formatting
Change-Id: I5ae2a2da1994fcc587540586d7404ebf18eb2ca0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/superio/fintek/f81866d')
| -rw-r--r-- | src/superio/fintek/f81866d/f81866d_hwm.c | 32 | ||||
| -rw-r--r-- | src/superio/fintek/f81866d/f81866d_uart.c | 4 |
2 files changed, 18 insertions, 18 deletions
diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c index e6333f5818..3d3a301f8c 100644 --- a/src/superio/fintek/f81866d/f81866d_hwm.c +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -14,29 +14,29 @@ /* Register addresses */ // Choose between AMD and Intel -#define HWM_AMD_TSI_ADDR 0x08 -#define HWM_AMD_TSI_CONTROL_REG 0x0A +#define HWM_AMD_TSI_ADDR 0x08 +#define HWM_AMD_TSI_CONTROL_REG 0x0A // Set temp sensors type -#define TEMP_SENS_TYPE_REG 0x6B +#define TEMP_SENS_TYPE_REG 0x6B // FAN prog sel -#define HWM_FAN3_CONTROL 0x9A -#define HWM_FAN_SEL 0x94 -#define HWM_FAN_MODE 0x96 -#define HWM_FAN2_TEMP_MAP_SEL 0xBF +#define HWM_FAN3_CONTROL 0x9A +#define HWM_FAN_SEL 0x94 +#define HWM_FAN_MODE 0x96 +#define HWM_FAN2_TEMP_MAP_SEL 0xBF // Fan 2 - 4 Boundaries -#define HWM_FAN2_BOUND1 0xB6 -#define HWM_FAN2_BOUND2 0xB7 -#define HWM_FAN2_BOUND3 0xB8 -#define HWM_FAN2_BOUND4 0xB9 +#define HWM_FAN2_BOUND1 0xB6 +#define HWM_FAN2_BOUND2 0xB7 +#define HWM_FAN2_BOUND3 0xB8 +#define HWM_FAN2_BOUND4 0xB9 // Fan 2 - 5 Segment speeds -#define HWM_FAN2_SEG1_SPEED_COUNT 0xBA -#define HWM_FAN2_SEG2_SPEED_COUNT 0xBB -#define HWM_FAN2_SEG3_SPEED_COUNT 0xBC -#define HWM_FAN2_SEG4_SPEED_COUNT 0xBD -#define HWM_FAN2_SEG5_SPEED_COUNT 0xBE +#define HWM_FAN2_SEG1_SPEED_COUNT 0xBA +#define HWM_FAN2_SEG2_SPEED_COUNT 0xBB +#define HWM_FAN2_SEG3_SPEED_COUNT 0xBC +#define HWM_FAN2_SEG4_SPEED_COUNT 0xBD +#define HWM_FAN2_SEG5_SPEED_COUNT 0xBE void f81866d_hwm_init(struct device *dev) diff --git a/src/superio/fintek/f81866d/f81866d_uart.c b/src/superio/fintek/f81866d/f81866d_uart.c index c6c18890b0..9590dc4e9c 100644 --- a/src/superio/fintek/f81866d/f81866d_uart.c +++ b/src/superio/fintek/f81866d/f81866d_uart.c @@ -36,13 +36,13 @@ void f81866d_uart_init(struct device *dev) pnp_write_config(dev, PORT_SELECT_REGISTER, tmp & 0xFE); // Set UART 3 function (Bit 4/5), otherwise pin 36-43 are GPIO - if (dev->path.pnp.device == F81866D_SP3) { + if (dev->path.pnp.device == F81866D_SP3) { tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG); pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0x30); } // Set UART 4 function (Bit 6/7), otherwise pin 44-51 are GPIO - if (dev->path.pnp.device == F81866D_SP4) { + if (dev->path.pnp.device == F81866D_SP4) { tmp = pnp_read_config(dev, MULTI_FUNC_SEL3_REG); pnp_write_config(dev, MULTI_FUNC_SEL3_REG, tmp | 0xC0); } |