diff options
| author | Fabian Kunkel <fabi@adv.bruhnspace.com> | 2016-07-07 15:15:18 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-08-02 18:57:36 +0200 |
| commit | 145796e171fdba246bb7a224f33dc050a16f0a30 (patch) | |
| tree | e53f3a8663a00a532a398dfb22816a90289237ac /src/superio/fintek/f81866d/superio.c | |
| parent | ae39fc45a8577ea0dab093a7aefcc336ecae88ea (diff) | |
superio/fintek/f81866d: Add support for UART 3/4
Pins for UART 3/4 are by default GPIO pins.
This patch sets the pins in UART mode.
Since UART 1/3 and 2/4 share the same interrupt line,
the patch needs to enable also shared interrupts.
Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P
Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html
Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e
Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com>
Reviewed-on: https://review.coreboot.org/15564
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/superio/fintek/f81866d/superio.c')
| -rw-r--r-- | src/superio/fintek/f81866d/superio.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c index a61629083d..775e2e8169 100644 --- a/src/superio/fintek/f81866d/superio.c +++ b/src/superio/fintek/f81866d/superio.c @@ -40,6 +40,22 @@ static void f81866d_init(struct device *dev) // Fixing temp sensor read out and init Fan control f81866d_hwm_init(dev); break; + case F81866D_SP1: + // Enable Uart1 and IRQ share register + f81866d_uart_init(dev); + break; + case F81866D_SP2: + // Enable Uart2 and IRQ share register + f81866d_uart_init(dev); + break; + case F81866D_SP3: + // Enable Uart3 and IRQ share register + f81866d_uart_init(dev); + break; + case F81866D_SP4: + // Enable Uart4 and IRQ share register + f81866d_uart_init(dev); + break; } } |