From 145796e171fdba246bb7a224f33dc050a16f0a30 Mon Sep 17 00:00:00 2001 From: Fabian Kunkel Date: Thu, 7 Jul 2016 15:15:18 +0200 Subject: superio/fintek/f81866d: Add support for UART 3/4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pins for UART 3/4 are by default GPIO pins. This patch sets the pins in UART mode. Since UART 1/3 and 2/4 share the same interrupt line, the patch needs to enable also shared interrupts. Datasheet: Name: F81866D/A-I, Release Date: Jan 2012, Version: V0.12P Link: http://www.alldatasheet.com/datasheet-pdf/pdf/459085/FINTEK/F81866AD-I.html Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e Signed-off-by: Fabian Kunkel Reviewed-on: https://review.coreboot.org/15564 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/superio/fintek/f81866d/superio.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/superio/fintek/f81866d/superio.c') diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c index a61629083d..775e2e8169 100644 --- a/src/superio/fintek/f81866d/superio.c +++ b/src/superio/fintek/f81866d/superio.c @@ -40,6 +40,22 @@ static void f81866d_init(struct device *dev) // Fixing temp sensor read out and init Fan control f81866d_hwm_init(dev); break; + case F81866D_SP1: + // Enable Uart1 and IRQ share register + f81866d_uart_init(dev); + break; + case F81866D_SP2: + // Enable Uart2 and IRQ share register + f81866d_uart_init(dev); + break; + case F81866D_SP3: + // Enable Uart3 and IRQ share register + f81866d_uart_init(dev); + break; + case F81866D_SP4: + // Enable Uart4 and IRQ share register + f81866d_uart_init(dev); + break; } } -- cgit v1.2.3