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| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2017-06-12 10:06:33 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2017-06-13 10:27:32 +0200 |
| commit | c21ba2cd3e6af194cc4d933d4f7bd434dfb2ff04 (patch) | |
| tree | 0b53d4b4fc18c266242325567107d64fda17addf /src/superio/fintek/f81865f | |
| parent | c4ff1de8bf65718a7fcb1aa3a77f7024140fecef (diff) | |
siemens/mc_apl1: Use Siemens NC FPGA driver
- use Siemens NC FPGA driver for backlight brightness and PWM control
- set Dsave time for board reset after falling edge of signal xdsave
Change-Id: I5077d4af162e54a3993e5e0d784a8356f51bd0c9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/superio/fintek/f81865f')
0 files changed, 0 insertions, 0 deletions