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authorElyes HAOUAS <ehaouas@noos.fr>2020-03-30 16:44:54 +0200
committerFelix Held <felix-coreboot@felixheld.de>2020-03-31 18:59:08 +0000
commit8dcadc9189d538dfcc0d8247bcd027afd5697244 (patch)
treef8163fe7eeb54c7c4d1ff6c771b473d7864e71c1 /src/superio/fintek/f81216h
parent3e666898cd99f4e15a39e360bb594d499e738b2d (diff)
superio/fintek: Improve code formatting
Change-Id: I5ae2a2da1994fcc587540586d7404ebf18eb2ca0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/superio/fintek/f81216h')
-rw-r--r--src/superio/fintek/f81216h/f81216h.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/superio/fintek/f81216h/f81216h.h b/src/superio/fintek/f81216h/f81216h.h
index 865cecbf6a..0c8463e55b 100644
--- a/src/superio/fintek/f81216h/f81216h.h
+++ b/src/superio/fintek/f81216h/f81216h.h
@@ -7,11 +7,11 @@
#include <device/pnp_type.h>
/* Logical Device Numbers (LDN). */
-#define F81216H_SP1 0x00 /* UART1 (+CIR mode) */
-#define F81216H_SP2 0x01 /* UART2 */
-#define F81216H_SP3 0x02 /* UART3 */
-#define F81216H_SP4 0x03 /* UART4 */
-#define F81216H_WDT 0x08 /* WDT */
+#define F81216H_SP1 0x00 /* UART1 (+CIR mode) */
+#define F81216H_SP2 0x01 /* UART2 */
+#define F81216H_SP3 0x02 /* UART3 */
+#define F81216H_SP4 0x03 /* UART4 */
+#define F81216H_WDT 0x08 /* WDT */
/**
* The PNP config entry key is parameterised