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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-04-23 21:52:25 +1000
committerPatrick Georgi <patrick@georgi-clan.de>2014-04-26 18:22:11 +0200
commitcf7b4989083cb3fd1adf34dc5e07d4ac253e8f85 (patch)
tree47aba25be42b14b74d97bb68e9e1a4df3f986ca0 /src/superio/fintek/f71872
parent4566d2e7cd32c1c2bdcc85a09c580e9f00f6b1dd (diff)
superio/fintek/*: Factor out generic romstage component
The romstage of Fintek Super I/O's is identical, leading to replication of essentially the same code prone to bitrot. Herein we consolidate the early pre-ram UART initialisation code into fintek/common, rather we leave the exceptions to be implemented under model/. More precisely we provide a well documented version of early_serial.c under fintek/common and select by way of Kconfig as a generic romstage component to Super I/O support. We leave future Super I/O's the option to implement `non-standard` initialisation code should such a (unlikely) need araise. A primary advantage is that new support for romstage serial is now trival to add. We also provide some Kconfig documentation while here. Change-Id: I3c62561558a62ece944a167ba302fb7076bba001 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5575 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/superio/fintek/f71872')
-rw-r--r--src/superio/fintek/f71872/Makefile.inc1
-rw-r--r--src/superio/fintek/f71872/early_serial.c48
-rw-r--r--src/superio/fintek/f71872/f71872.h2
3 files changed, 0 insertions, 51 deletions
diff --git a/src/superio/fintek/f71872/Makefile.inc b/src/superio/fintek/f71872/Makefile.inc
index 58ba5d562a..ed40eb0ab5 100644
--- a/src/superio/fintek/f71872/Makefile.inc
+++ b/src/superio/fintek/f71872/Makefile.inc
@@ -18,5 +18,4 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-romstage-$(CONFIG_SUPERIO_FINTEK_F71872) += early_serial.c
ramstage-$(CONFIG_SUPERIO_FINTEK_F71872) += superio.c
diff --git a/src/superio/fintek/f71872/early_serial.c b/src/superio/fintek/f71872/early_serial.c
deleted file mode 100644
index bbfc26430a..0000000000
--- a/src/superio/fintek/f71872/early_serial.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-/* Pre-RAM driver for the Fintek F71872F/FG Super I/O chip. */
-
-#include <arch/io.h>
-#include <device/pnp.h>
-#include "f71872.h"
-
-static void pnp_enter_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_conf_state(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-void f71872_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_conf_state(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_conf_state(dev);
-}
diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h
index fb8076248a..629d42deb8 100644
--- a/src/superio/fintek/f71872/f71872.h
+++ b/src/superio/fintek/f71872/f71872.h
@@ -32,6 +32,4 @@
#define F71872_VID 0x07 /* VID */
#define F71872_PM 0x0a /* ACPI/PME */
-void f71872_enable_serial(device_t dev, u16 iobase);
-
#endif /* SUPERIO_FINTEK_F71872_H */