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authorFelix Held <felix-coreboot@felixheld.de>2021-01-14 01:16:56 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-01-24 18:15:59 +0000
commit57419de1879ca5d40669fb2690428bc0e0addb31 (patch)
tree343796e13d08b9a622e83fcd98942a2152970381 /src/superio/common/ssdt.h
parent8d0a609e6d1bfb48de781e7223f73ff979d0ce2e (diff)
soc/amd/cezanne: add basic romstage
This currently only initializes the console, calls into the FSP driver that then calls into FSP-M and then jumps to ramstage after the FSP-M returns. Right now, this mainly unblocks the FSP-M development. Change-Id: I9f3cdaac573e365bb4d59364d44727677f53e91b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/superio/common/ssdt.h')
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