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authorFelix Held <felix-coreboot@felixheld.de>2022-01-11 16:39:44 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-01-25 03:19:24 +0000
commitaf356d313d915e65dba880c907c39488e147586f (patch)
tree09141c8f281fb76b4b91e663729038ff68fce86f /src/superio/aspeed
parenta8d7c043f67aee61280b3851e938f2c1de252f06 (diff)
soc/amd/sabrina: use correct PCI IDs
Replace the Renoir/Cezanne PCI IDs with the Sabrina ones that were added in commit 27b02c2eee68f4b6c8520c4737224aaaf81f137d (include/device/ pci_ids.h: add PCI IDs for AMD Family 17h Model A0h SoC). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I427df6f8e8c08fb47ae8513b6cf1085d4294e28f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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