header files: Fix guard name comments to match guard names

This just updates existing guard name comments on the header files
to match the actual #define name.
As a side effect, if there was no newline at the end of these files,
one was added.

Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12900
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

9 files changed, 9 insertions, 9 deletions

diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
index 45dda17425..7562417dd7 100644
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ b/src/southbridge/amd/cimx/sb700/Platform.h
@@ -82,4 +82,4 @@ void    TraceCode ( UINT32 Level, UINT32 Code);
 
 #define DMSG_SB_TRACE   0x02
 
-#endif  //#ifndef _AMD_SB_CIMx_PLATFORM_H_
+#endif /* _AMD_SB_CIMx_PLATFORM_H_ */
diff --git a/src/southbridge/amd/cs5535/chip.h b/src/southbridge/amd/cs5535/chip.h
index d4dde3d6ee..37e5eadddd 100644
--- a/src/southbridge/amd/cs5535/chip.h
+++ b/src/southbridge/amd/cs5535/chip.h
@@ -5,4 +5,4 @@ struct southbridge_amd_cs5535_config {
 	int setupflash;
 };
 
-#endif	/* _SOUTHBRIDGE_AMD_CS5536 */
+#endif /* _SOUTHBRIDGE_AMD_CS5535 */
diff --git a/src/southbridge/amd/rs690/rs690.h b/src/southbridge/amd/rs690/rs690.h
index c0f13ac06f..9a2fec5196 100644
--- a/src/southbridge/amd/rs690/rs690.h
+++ b/src/southbridge/amd/rs690/rs690.h
@@ -134,4 +134,4 @@ void avoid_lpc_dma_deadlock(device_t nb_dev, device_t sb_dev);
 void config_gpp_core(device_t nb_dev, device_t sb_dev);
 void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port);
 u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port);
-#endif				/* RS690_H */
+#endif /* __RS690_H__ */
diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h
index 341de0d487..ffd0e15172 100644
--- a/src/southbridge/amd/rs780/rs780.h
+++ b/src/southbridge/amd/rs780/rs780.h
@@ -210,4 +210,4 @@ int cpuidFamily(void);
 int is_family0Fh(void);
 int is_family10h(void);
 void pcie_hide_unused_ports(device_t nb_dev);
-#endif				/* RS780_H */
+#endif /* __RS780_H__ */
diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h
index c6db26da5a..ea7005c9ef 100644
--- a/src/southbridge/amd/sr5650/sr5650.h
+++ b/src/southbridge/amd/sr5650/sr5650.h
@@ -132,4 +132,4 @@ void sr5650_nb_pci_table(device_t nb_dev);
 void init_gen2(device_t nb_dev, device_t dev, u8 port);
 void sr56x0_lock_hwinitreg(void);
 struct resource * sr5650_retrieve_cpu_mmio_resource(void);
-#endif /* SR5650_H */
+#endif /* __SR5650_H__ */
diff --git a/src/southbridge/intel/fsp_bd82x6x/chip.h b/src/southbridge/intel/fsp_bd82x6x/chip.h
index 8147c513fb..9d6a9e4dbd 100644
--- a/src/southbridge/intel/fsp_bd82x6x/chip.h
+++ b/src/southbridge/intel/fsp_bd82x6x/chip.h
@@ -88,4 +88,4 @@ struct southbridge_intel_fsp_bd82x6x_config {
 	int c2_latency;
 };
 
-#endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
+#endif /* SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h
index 3018455cef..045c2285af 100644
--- a/src/southbridge/intel/fsp_bd82x6x/pch.h
+++ b/src/southbridge/intel/fsp_bd82x6x/pch.h
@@ -582,4 +582,4 @@ void display_fd_settings(void);
 #define SPIBAR_FDATA(n)             (0x3810 + (4 * n)) /* SPI flash data */
 
 #endif /* __ACPI__ */
-#endif				/* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */
+#endif /* SOUTHBRIDGE_INTEL_FSP_BD82X6X_PCH_H */
diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h
index 90610acb6a..ba0fa4e8c5 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.h
+++ b/src/southbridge/intel/fsp_rangeley/soc.h
@@ -445,4 +445,4 @@ void rangeley_sb_early_initialization(void);
 
 
 #endif /* __ACPI__ */
-#endif				/* SOUTHBRIDGE_INTEL_RANGELEY_PCH_H */
+#endif /* SOUTHBRIDGE_INTEL_RANGELEY_SOC_H */
diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h
index 69a59b3d53..f77413d671 100644
--- a/src/southbridge/intel/i82801dx/chip.h
+++ b/src/southbridge/intel/i82801dx/chip.h
@@ -37,4 +37,4 @@ struct southbridge_intel_i82801dx_config {
 	uint8_t ide1_enable;
 };
 
-#endif				/* I82801DBM_CHIP_H */
+#endif /* I82801DX_CHIP_H */