diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-11-10 20:29:08 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-29 12:21:03 +0000 |
| commit | f5b974e4b7a54d2ab9b59101ce17576e2e16e3f0 (patch) | |
| tree | 67b2a1022c43e7ffd9c3680382125f23970fa665 /src/southbridge | |
| parent | 95370e1f041f0236770937599286e020d6e75c19 (diff) | |
arch/acpi.h: Add some update to version 6.2a
Some tables updated to comply with ACPI version 6.2a.
Change-Id: I91291c8202d1562b720b9922791c6282e572601f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/amd/agesa/hudson/fadt.c | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb800/fadt.c | 5 | ||||
| -rw-r--r-- | src/southbridge/amd/pi/hudson/fadt.c | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/acpi.c | 6 |
4 files changed, 8 insertions, 14 deletions
diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 1cb9875d10..e8483a045c 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -138,10 +138,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_value = 6; - fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32; diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 59e61da252..15e05c398e 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -153,9 +153,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_reg.addrh = 0x0; fadt->reset_value = 6; - fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32; diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index c2a3ff4a46..c2d5d19ddb 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -130,9 +130,8 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_value = 6; - fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ fadt->x_firmware_ctl_h = 0; diff --git a/src/southbridge/intel/fsp_rangeley/acpi.c b/src/southbridge/intel/fsp_rangeley/acpi.c index ca711dce24..efe5412c9f 100644 --- a/src/southbridge/intel/fsp_rangeley/acpi.c +++ b/src/southbridge/intel/fsp_rangeley/acpi.c @@ -120,10 +120,8 @@ void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->reset_reg.addrh = 0x00; fadt->reset_value = 6; - /* Reserved Bits */ - fadt->res3 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res4 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ - fadt->res5 = 0x00; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ + fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ /* Extended ACPI Pointers */ fadt->x_firmware_ctl_l = (unsigned long)facs; |