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| author | Jonathan Zhang <jonzhang@fb.com> | 2020-06-26 14:36:01 -0700 |
|---|---|---|
| committer | Philipp Deppenwiese <zaolin.daisuki@gmail.com> | 2020-07-07 22:24:41 +0000 |
| commit | e4aab352ee2d3981f5ec8d28a77ee93163fdf365 (patch) | |
| tree | 41a4bc751ff65cc9e2cbcc5265c9fad26a50fd06 /src/southbridge | |
| parent | e69b1af925e489930f7b441840c7d8b9cb71be62 (diff) | |
vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc
CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also
update memory map HOB definition file accordingly.
The CPX-SP soc code is updated to direct FSP log to SOL.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions