diff options
| author | Jimmy Zhang <jimmzhang@nvidia.com> | 2014-08-01 16:36:35 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-03-25 22:31:36 +0100 |
| commit | dabf0ebec03772cac320dc950cac57a48e1bd3c9 (patch) | |
| tree | bd53788b1c1edd1f8e1201bf115c5b9d79102730 /src/southbridge | |
| parent | 654d8051d48aa9c735edf2bbdaf097506ce47d2f (diff) | |
ryu: Add three more full LPDDR3 SDRAM BCTs
Add in the following BCTs to source code tree:
Hynix 4GB 924MHz BCT
Micron 4GB 924MHz BCT
Samsung 4GB 924MHz BCT
BUG=none
BRANCH=none
TEST=Built and tested Micron 924 bct on A44 board with Elpida memory chip.
Change-Id: I59a5cc1133bf41a51f40a771ff0a7b7ef8d549fe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0a72f1b704928fad341bda460ecc349914ec612c
Original-Change-Id: I9e5b54c3eb7ee4c4010b5aaf5dad030eba75108b
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/210872
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: http://review.coreboot.org/8904
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge')
0 files changed, 0 insertions, 0 deletions