diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-07-27 15:29:21 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-01 14:37:39 +0000 |
| commit | b9c049a3680f82fd62637f9e4bae1d5ef67fd504 (patch) | |
| tree | 7f23df95441475ef66b86d53f0563c7ca900d8e7 /src/southbridge | |
| parent | 07bc3251a9c74ecb4f96878b99e3537307c6c685 (diff) | |
sb/intel/i82801gx: Select INTEL_TOP_SWAP_BOOTBLOCK_SIZE
This effectively means it is possible to run another bootblock located at
top_of_flash - 64K.
The i82801gx southbridge has the ability to swap the two top 64K ranges by
flipping the BUC.TS bit (RCBA[3414] bit0).
This allows coreboot to build roms with a bootblock at the top swap offset by
selecting CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK.
Change-Id: Id96e10aea3e5fd955d45287134eb8643be414de9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/southbridge')
| -rw-r--r-- | src/southbridge/intel/i82801gx/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 7e48848c7b..fbae6452eb 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -28,6 +28,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_INTEL_COMMON_SPI select HAVE_INTEL_CHIPSET_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ + select INTEL_HAS_TOP_SWAP if SOUTHBRIDGE_INTEL_I82801GX @@ -43,4 +44,9 @@ config HPET_MIN_TICKS hex default 0x80 +config INTEL_TOP_SWAP_BOOTBLOCK_SIZE + hex + # Always 64K, all other options are invalid + default 0x10000 + endif |